RegAllocBasic.cpp revision a8bd9a68f7c00fe1d895bb5e27ff804aa33abd64
1//===-- RegAllocBasic.cpp - Basic Register Allocator ----------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the RABasic function pass, which provides a minimal 11// implementation of the basic register allocator. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "regalloc" 16#include "RegAllocBase.h" 17#include "LiveDebugVariables.h" 18#include "LiveRangeEdit.h" 19#include "RenderMachineFunction.h" 20#include "Spiller.h" 21#include "VirtRegMap.h" 22#include "llvm/Analysis/AliasAnalysis.h" 23#include "llvm/Function.h" 24#include "llvm/PassAnalysisSupport.h" 25#include "llvm/CodeGen/CalcSpillWeights.h" 26#include "llvm/CodeGen/LiveIntervalAnalysis.h" 27#include "llvm/CodeGen/LiveStackAnalysis.h" 28#include "llvm/CodeGen/MachineFunctionPass.h" 29#include "llvm/CodeGen/MachineInstr.h" 30#include "llvm/CodeGen/MachineLoopInfo.h" 31#include "llvm/CodeGen/MachineRegisterInfo.h" 32#include "llvm/CodeGen/Passes.h" 33#include "llvm/CodeGen/RegAllocRegistry.h" 34#include "llvm/Target/TargetMachine.h" 35#include "llvm/Target/TargetOptions.h" 36#include "llvm/Target/TargetRegisterInfo.h" 37#include "llvm/Support/Debug.h" 38#include "llvm/Support/raw_ostream.h" 39 40#include <cstdlib> 41#include <queue> 42 43using namespace llvm; 44 45static RegisterRegAlloc basicRegAlloc("basic", "basic register allocator", 46 createBasicRegisterAllocator); 47 48namespace { 49 struct CompSpillWeight { 50 bool operator()(LiveInterval *A, LiveInterval *B) const { 51 return A->weight < B->weight; 52 } 53 }; 54} 55 56namespace { 57/// RABasic provides a minimal implementation of the basic register allocation 58/// algorithm. It prioritizes live virtual registers by spill weight and spills 59/// whenever a register is unavailable. This is not practical in production but 60/// provides a useful baseline both for measuring other allocators and comparing 61/// the speed of the basic algorithm against other styles of allocators. 62class RABasic : public MachineFunctionPass, public RegAllocBase 63{ 64 // context 65 MachineFunction *MF; 66 67 // analyses 68 LiveStacks *LS; 69 RenderMachineFunction *RMF; 70 71 // state 72 std::auto_ptr<Spiller> SpillerInstance; 73 std::priority_queue<LiveInterval*, std::vector<LiveInterval*>, 74 CompSpillWeight> Queue; 75public: 76 RABasic(); 77 78 /// Return the pass name. 79 virtual const char* getPassName() const { 80 return "Basic Register Allocator"; 81 } 82 83 /// RABasic analysis usage. 84 virtual void getAnalysisUsage(AnalysisUsage &AU) const; 85 86 virtual void releaseMemory(); 87 88 virtual Spiller &spiller() { return *SpillerInstance; } 89 90 virtual float getPriority(LiveInterval *LI) { return LI->weight; } 91 92 virtual void enqueue(LiveInterval *LI) { 93 Queue.push(LI); 94 } 95 96 virtual LiveInterval *dequeue() { 97 if (Queue.empty()) 98 return 0; 99 LiveInterval *LI = Queue.top(); 100 Queue.pop(); 101 return LI; 102 } 103 104 virtual unsigned selectOrSplit(LiveInterval &VirtReg, 105 SmallVectorImpl<LiveInterval*> &SplitVRegs); 106 107 /// Perform register allocation. 108 virtual bool runOnMachineFunction(MachineFunction &mf); 109 110 // Helper for spilling all live virtual registers currently unified under preg 111 // that interfere with the most recently queried lvr. Return true if spilling 112 // was successful, and append any new spilled/split intervals to splitLVRs. 113 bool spillInterferences(LiveInterval &VirtReg, unsigned PhysReg, 114 SmallVectorImpl<LiveInterval*> &SplitVRegs); 115 116 void spillReg(LiveInterval &VirtReg, unsigned PhysReg, 117 SmallVectorImpl<LiveInterval*> &SplitVRegs); 118 119 static char ID; 120}; 121 122char RABasic::ID = 0; 123 124} // end anonymous namespace 125 126RABasic::RABasic(): MachineFunctionPass(ID) { 127 initializeLiveDebugVariablesPass(*PassRegistry::getPassRegistry()); 128 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry()); 129 initializeSlotIndexesPass(*PassRegistry::getPassRegistry()); 130 initializeStrongPHIEliminationPass(*PassRegistry::getPassRegistry()); 131 initializeRegisterCoalescerPass(*PassRegistry::getPassRegistry()); 132 initializeCalculateSpillWeightsPass(*PassRegistry::getPassRegistry()); 133 initializeLiveStacksPass(*PassRegistry::getPassRegistry()); 134 initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry()); 135 initializeMachineLoopInfoPass(*PassRegistry::getPassRegistry()); 136 initializeVirtRegMapPass(*PassRegistry::getPassRegistry()); 137 initializeRenderMachineFunctionPass(*PassRegistry::getPassRegistry()); 138} 139 140void RABasic::getAnalysisUsage(AnalysisUsage &AU) const { 141 AU.setPreservesCFG(); 142 AU.addRequired<AliasAnalysis>(); 143 AU.addPreserved<AliasAnalysis>(); 144 AU.addRequired<LiveIntervals>(); 145 AU.addPreserved<SlotIndexes>(); 146 AU.addRequired<LiveDebugVariables>(); 147 AU.addPreserved<LiveDebugVariables>(); 148 if (StrongPHIElim) 149 AU.addRequiredID(StrongPHIEliminationID); 150 AU.addRequiredTransitiveID(RegisterCoalescerPassID); 151 AU.addRequired<CalculateSpillWeights>(); 152 AU.addRequired<LiveStacks>(); 153 AU.addPreserved<LiveStacks>(); 154 AU.addRequiredID(MachineDominatorsID); 155 AU.addPreservedID(MachineDominatorsID); 156 AU.addRequired<MachineLoopInfo>(); 157 AU.addPreserved<MachineLoopInfo>(); 158 AU.addRequired<VirtRegMap>(); 159 AU.addPreserved<VirtRegMap>(); 160 DEBUG(AU.addRequired<RenderMachineFunction>()); 161 MachineFunctionPass::getAnalysisUsage(AU); 162} 163 164void RABasic::releaseMemory() { 165 SpillerInstance.reset(0); 166 RegAllocBase::releaseMemory(); 167} 168 169// Helper for spillInterferences() that spills all interfering vregs currently 170// assigned to this physical register. 171void RABasic::spillReg(LiveInterval& VirtReg, unsigned PhysReg, 172 SmallVectorImpl<LiveInterval*> &SplitVRegs) { 173 LiveIntervalUnion::Query &Q = query(VirtReg, PhysReg); 174 assert(Q.seenAllInterferences() && "need collectInterferences()"); 175 const SmallVectorImpl<LiveInterval*> &PendingSpills = Q.interferingVRegs(); 176 177 for (SmallVectorImpl<LiveInterval*>::const_iterator I = PendingSpills.begin(), 178 E = PendingSpills.end(); I != E; ++I) { 179 LiveInterval &SpilledVReg = **I; 180 DEBUG(dbgs() << "extracting from " << 181 TRI->getName(PhysReg) << " " << SpilledVReg << '\n'); 182 183 // Deallocate the interfering vreg by removing it from the union. 184 // A LiveInterval instance may not be in a union during modification! 185 unassign(SpilledVReg, PhysReg); 186 187 // Spill the extracted interval. 188 LiveRangeEdit LRE(SpilledVReg, SplitVRegs, 0, &PendingSpills); 189 spiller().spill(LRE); 190 } 191 // After extracting segments, the query's results are invalid. But keep the 192 // contents valid until we're done accessing pendingSpills. 193 Q.clear(); 194} 195 196// Spill or split all live virtual registers currently unified under PhysReg 197// that interfere with VirtReg. The newly spilled or split live intervals are 198// returned by appending them to SplitVRegs. 199bool RABasic::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg, 200 SmallVectorImpl<LiveInterval*> &SplitVRegs) { 201 // Record each interference and determine if all are spillable before mutating 202 // either the union or live intervals. 203 unsigned NumInterferences = 0; 204 // Collect interferences assigned to any alias of the physical register. 205 for (const unsigned *asI = TRI->getOverlaps(PhysReg); *asI; ++asI) { 206 LiveIntervalUnion::Query &QAlias = query(VirtReg, *asI); 207 NumInterferences += QAlias.collectInterferingVRegs(); 208 if (QAlias.seenUnspillableVReg()) { 209 return false; 210 } 211 } 212 DEBUG(dbgs() << "spilling " << TRI->getName(PhysReg) << 213 " interferences with " << VirtReg << "\n"); 214 assert(NumInterferences > 0 && "expect interference"); 215 216 // Spill each interfering vreg allocated to PhysReg or an alias. 217 for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI) 218 spillReg(VirtReg, *AliasI, SplitVRegs); 219 return true; 220} 221 222// Driver for the register assignment and splitting heuristics. 223// Manages iteration over the LiveIntervalUnions. 224// 225// This is a minimal implementation of register assignment and splitting that 226// spills whenever we run out of registers. 227// 228// selectOrSplit can only be called once per live virtual register. We then do a 229// single interference test for each register the correct class until we find an 230// available register. So, the number of interference tests in the worst case is 231// |vregs| * |machineregs|. And since the number of interference tests is 232// minimal, there is no value in caching them outside the scope of 233// selectOrSplit(). 234unsigned RABasic::selectOrSplit(LiveInterval &VirtReg, 235 SmallVectorImpl<LiveInterval*> &SplitVRegs) { 236 // Populate a list of physical register spill candidates. 237 SmallVector<unsigned, 8> PhysRegSpillCands; 238 239 // Check for an available register in this class. 240 ArrayRef<unsigned> Order = 241 RegClassInfo.getOrder(MRI->getRegClass(VirtReg.reg)); 242 for (ArrayRef<unsigned>::iterator I = Order.begin(), E = Order.end(); I != E; 243 ++I) { 244 unsigned PhysReg = *I; 245 246 // Check interference and as a side effect, intialize queries for this 247 // VirtReg and its aliases. 248 unsigned interfReg = checkPhysRegInterference(VirtReg, PhysReg); 249 if (interfReg == 0) { 250 // Found an available register. 251 return PhysReg; 252 } 253 Queries[interfReg].collectInterferingVRegs(1); 254 LiveInterval *interferingVirtReg = 255 Queries[interfReg].interferingVRegs().front(); 256 257 // The current VirtReg must either be spillable, or one of its interferences 258 // must have less spill weight. 259 if (interferingVirtReg->weight < VirtReg.weight ) { 260 PhysRegSpillCands.push_back(PhysReg); 261 } 262 } 263 // Try to spill another interfering reg with less spill weight. 264 for (SmallVectorImpl<unsigned>::iterator PhysRegI = PhysRegSpillCands.begin(), 265 PhysRegE = PhysRegSpillCands.end(); PhysRegI != PhysRegE; ++PhysRegI) { 266 267 if (!spillInterferences(VirtReg, *PhysRegI, SplitVRegs)) continue; 268 269 assert(checkPhysRegInterference(VirtReg, *PhysRegI) == 0 && 270 "Interference after spill."); 271 // Tell the caller to allocate to this newly freed physical register. 272 return *PhysRegI; 273 } 274 275 // No other spill candidates were found, so spill the current VirtReg. 276 DEBUG(dbgs() << "spilling: " << VirtReg << '\n'); 277 if (!VirtReg.isSpillable()) 278 return ~0u; 279 LiveRangeEdit LRE(VirtReg, SplitVRegs); 280 spiller().spill(LRE); 281 282 // The live virtual register requesting allocation was spilled, so tell 283 // the caller not to allocate anything during this round. 284 return 0; 285} 286 287bool RABasic::runOnMachineFunction(MachineFunction &mf) { 288 DEBUG(dbgs() << "********** BASIC REGISTER ALLOCATION **********\n" 289 << "********** Function: " 290 << ((Value*)mf.getFunction())->getName() << '\n'); 291 292 MF = &mf; 293 DEBUG(RMF = &getAnalysis<RenderMachineFunction>()); 294 295 RegAllocBase::init(getAnalysis<VirtRegMap>(), getAnalysis<LiveIntervals>()); 296 SpillerInstance.reset(createInlineSpiller(*this, *MF, *VRM)); 297 298 allocatePhysRegs(); 299 300 addMBBLiveIns(MF); 301 302 // Diagnostic output before rewriting 303 DEBUG(dbgs() << "Post alloc VirtRegMap:\n" << *VRM << "\n"); 304 305 // optional HTML output 306 DEBUG(RMF->renderMachineFunction("After basic register allocation.", VRM)); 307 308 // FIXME: Verification currently must run before VirtRegRewriter. We should 309 // make the rewriter a separate pass and override verifyAnalysis instead. When 310 // that happens, verification naturally falls under VerifyMachineCode. 311#ifndef NDEBUG 312 if (VerifyEnabled) { 313 // Verify accuracy of LiveIntervals. The standard machine code verifier 314 // ensures that each LiveIntervals covers all uses of the virtual reg. 315 316 // FIXME: MachineVerifier is badly broken when using the standard 317 // spiller. Always use -spiller=inline with -verify-regalloc. Even with the 318 // inline spiller, some tests fail to verify because the coalescer does not 319 // always generate verifiable code. 320 MF->verify(this, "In RABasic::verify"); 321 322 // Verify that LiveIntervals are partitioned into unions and disjoint within 323 // the unions. 324 verify(); 325 } 326#endif // !NDEBUG 327 328 // Run rewriter 329 VRM->rewrite(LIS->getSlotIndexes()); 330 331 // Write out new DBG_VALUE instructions. 332 getAnalysis<LiveDebugVariables>().emitDebugValues(VRM); 333 334 // The pass output is in VirtRegMap. Release all the transient data. 335 releaseMemory(); 336 337 return true; 338} 339 340FunctionPass* llvm::createBasicRegisterAllocator() 341{ 342 return new RABasic(); 343} 344