1f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune//===--------------------- R600MergeVectorRegisters.cpp -------------------===// 2f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune// 3f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune// The LLVM Compiler Infrastructure 4f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune// 5f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune// This file is distributed under the University of Illinois Open Source 6f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune// License. See LICENSE.TXT for details. 7f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune// 8f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune//===----------------------------------------------------------------------===// 9f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune// 10f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune/// \file 11f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune/// This pass merges inputs of swizzeable instructions into vector sharing 12f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune/// common data and/or have enough undef subreg using swizzle abilities. 13f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune/// 14f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune/// For instance let's consider the following pseudo code : 15f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune/// vreg5<def> = REG_SEQ vreg1, sub0, vreg2, sub1, vreg3, sub2, undef, sub3 16f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune/// ... 17f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune/// vreg7<def> = REG_SEQ vreg1, sub0, vreg3, sub1, undef, sub2, vreg4, sub3 18f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune/// (swizzable Inst) vreg7, SwizzleMask : sub0, sub1, sub2, sub3 19f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune/// 20f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune/// is turned into : 21f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune/// vreg5<def> = REG_SEQ vreg1, sub0, vreg2, sub1, vreg3, sub2, undef, sub3 22f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune/// ... 23f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune/// vreg7<def> = INSERT_SUBREG vreg4, sub3 24f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune/// (swizzable Inst) vreg7, SwizzleMask : sub0, sub2, sub1, sub3 25f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune/// 26f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune/// This allow regalloc to reduce register pressure for vector registers and 27f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune/// to reduce MOV count. 28f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune//===----------------------------------------------------------------------===// 29f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune 30f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune#include "AMDGPU.h" 3137ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines#include "AMDGPUSubtarget.h" 32de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar#include "R600Defines.h" 334c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar#include "R600InstrInfo.h" 34f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune#include "llvm/CodeGen/DFAPacketizer.h" 35f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune#include "llvm/CodeGen/MachineDominators.h" 36f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune#include "llvm/CodeGen/MachineFunctionPass.h" 3736b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines#include "llvm/CodeGen/MachineInstrBuilder.h" 38f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune#include "llvm/CodeGen/MachineLoopInfo.h" 3936b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines#include "llvm/CodeGen/MachineRegisterInfo.h" 40f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune#include "llvm/CodeGen/Passes.h" 414c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar#include "llvm/Support/Debug.h" 42f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune#include "llvm/Support/raw_ostream.h" 43f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune 44f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeuneusing namespace llvm; 45f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune 46dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines#define DEBUG_TYPE "vec-merger" 47dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 48f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeunenamespace { 49f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune 50f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeunestatic bool 51f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent LejeuneisImplicitlyDef(MachineRegisterInfo &MRI, unsigned Reg) { 5236b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines for (MachineRegisterInfo::def_instr_iterator It = MRI.def_instr_begin(Reg), 5336b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines E = MRI.def_instr_end(); It != E; ++It) { 54f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune return (*It).isImplicitDef(); 55f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune } 566b88cdb34cc78f815946b8ebe6c2332d084526adTom Stellard if (MRI.isReserved(Reg)) { 576b88cdb34cc78f815946b8ebe6c2332d084526adTom Stellard return false; 586b88cdb34cc78f815946b8ebe6c2332d084526adTom Stellard } 59f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune llvm_unreachable("Reg without a def"); 60f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune return false; 61f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune} 62f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune 63f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeuneclass RegSeqInfo { 64f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeunepublic: 65f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune MachineInstr *Instr; 66f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune DenseMap<unsigned, unsigned> RegToChan; 67f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune std::vector<unsigned> UndefReg; 68f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune RegSeqInfo(MachineRegisterInfo &MRI, MachineInstr *MI) : Instr(MI) { 6936b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines assert(MI->getOpcode() == AMDGPU::REG_SEQUENCE); 70f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune for (unsigned i = 1, e = Instr->getNumOperands(); i < e; i+=2) { 71f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune MachineOperand &MO = Instr->getOperand(i); 72f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune unsigned Chan = Instr->getOperand(i + 1).getImm(); 73f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune if (isImplicitlyDef(MRI, MO.getReg())) 74f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune UndefReg.push_back(Chan); 75f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune else 76f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune RegToChan[MO.getReg()] = Chan; 77f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune } 78f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune } 79f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune RegSeqInfo() {} 80f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune 81f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune bool operator==(const RegSeqInfo &RSI) const { 82f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune return RSI.Instr == Instr; 83f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune } 84f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune}; 85f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune 86f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeuneclass R600VectorRegMerger : public MachineFunctionPass { 87f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeuneprivate: 88f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune MachineRegisterInfo *MRI; 89f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune const R600InstrInfo *TII; 90f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune bool canSwizzle(const MachineInstr &) const; 91f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune bool areAllUsesSwizzeable(unsigned Reg) const; 92f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune void SwizzleInput(MachineInstr &, 93f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune const std::vector<std::pair<unsigned, unsigned> > &) const; 94f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune bool tryMergeVector(const RegSeqInfo *, RegSeqInfo *, 95f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune std::vector<std::pair<unsigned, unsigned> > &Remap) const; 96f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune bool tryMergeUsingCommonSlot(RegSeqInfo &RSI, RegSeqInfo &CompatibleRSI, 97f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune std::vector<std::pair<unsigned, unsigned> > &RemapChan); 98f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune bool tryMergeUsingFreeSlot(RegSeqInfo &RSI, RegSeqInfo &CompatibleRSI, 99f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune std::vector<std::pair<unsigned, unsigned> > &RemapChan); 100f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune MachineInstr *RebuildVector(RegSeqInfo *MI, 101f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune const RegSeqInfo *BaseVec, 102f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune const std::vector<std::pair<unsigned, unsigned> > &RemapChan) const; 103f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune void RemoveMI(MachineInstr *); 104f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune void trackRSI(const RegSeqInfo &RSI); 105f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune 106f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune typedef DenseMap<unsigned, std::vector<MachineInstr *> > InstructionSetMap; 107f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune DenseMap<MachineInstr *, RegSeqInfo> PreviousRegSeq; 108f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune InstructionSetMap PreviousRegSeqByReg; 109f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune InstructionSetMap PreviousRegSeqByUndefCount; 110f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeunepublic: 111f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune static char ID; 112f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune R600VectorRegMerger(TargetMachine &tm) : MachineFunctionPass(ID), 113dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines TII(nullptr) { } 114f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune 115dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines void getAnalysisUsage(AnalysisUsage &AU) const override { 116f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune AU.setPreservesCFG(); 117f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune AU.addRequired<MachineDominatorTree>(); 118f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune AU.addPreserved<MachineDominatorTree>(); 119f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune AU.addRequired<MachineLoopInfo>(); 120f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune AU.addPreserved<MachineLoopInfo>(); 121f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune MachineFunctionPass::getAnalysisUsage(AU); 122f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune } 123f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune 124dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines const char *getPassName() const override { 125f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune return "R600 Vector Registers Merge Pass"; 126f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune } 127f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune 128dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines bool runOnMachineFunction(MachineFunction &Fn) override; 129f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune}; 130f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune 131f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeunechar R600VectorRegMerger::ID = 0; 132f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune 133f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeunebool R600VectorRegMerger::canSwizzle(const MachineInstr &MI) 134f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune const { 135f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune if (TII->get(MI.getOpcode()).TSFlags & R600_InstFlag::TEX_INST) 136f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune return true; 137f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune switch (MI.getOpcode()) { 138f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune case AMDGPU::R600_ExportSwz: 139f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune case AMDGPU::EG_ExportSwz: 140f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune return true; 141f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune default: 142f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune return false; 143f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune } 144f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune} 145f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune 146f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeunebool R600VectorRegMerger::tryMergeVector(const RegSeqInfo *Untouched, 147f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune RegSeqInfo *ToMerge, std::vector< std::pair<unsigned, unsigned> > &Remap) 148f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune const { 149f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune unsigned CurrentUndexIdx = 0; 150f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune for (DenseMap<unsigned, unsigned>::iterator It = ToMerge->RegToChan.begin(), 151f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune E = ToMerge->RegToChan.end(); It != E; ++It) { 152f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune DenseMap<unsigned, unsigned>::const_iterator PosInUntouched = 153f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune Untouched->RegToChan.find((*It).first); 154f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune if (PosInUntouched != Untouched->RegToChan.end()) { 155f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune Remap.push_back(std::pair<unsigned, unsigned> 156f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune ((*It).second, (*PosInUntouched).second)); 157f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune continue; 158f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune } 159f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune if (CurrentUndexIdx >= Untouched->UndefReg.size()) 160f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune return false; 161f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune Remap.push_back(std::pair<unsigned, unsigned> 162f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune ((*It).second, Untouched->UndefReg[CurrentUndexIdx++])); 163f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune } 164f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune 165f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune return true; 166f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune} 167f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune 16881c5d11c25690cdb6282eb0ceb79f487325ce1e6Vincent Lejeunestatic 16981c5d11c25690cdb6282eb0ceb79f487325ce1e6Vincent Lejeuneunsigned getReassignedChan( 17081c5d11c25690cdb6282eb0ceb79f487325ce1e6Vincent Lejeune const std::vector<std::pair<unsigned, unsigned> > &RemapChan, 17181c5d11c25690cdb6282eb0ceb79f487325ce1e6Vincent Lejeune unsigned Chan) { 17281c5d11c25690cdb6282eb0ceb79f487325ce1e6Vincent Lejeune for (unsigned j = 0, je = RemapChan.size(); j < je; j++) { 17374f03455e5ee463a43a0f82efbd2fbd364e2cbdaVincent Lejeune if (RemapChan[j].first == Chan) 17481c5d11c25690cdb6282eb0ceb79f487325ce1e6Vincent Lejeune return RemapChan[j].second; 17581c5d11c25690cdb6282eb0ceb79f487325ce1e6Vincent Lejeune } 17681c5d11c25690cdb6282eb0ceb79f487325ce1e6Vincent Lejeune llvm_unreachable("Chan wasn't reassigned"); 17781c5d11c25690cdb6282eb0ceb79f487325ce1e6Vincent Lejeune} 17881c5d11c25690cdb6282eb0ceb79f487325ce1e6Vincent Lejeune 179f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent LejeuneMachineInstr *R600VectorRegMerger::RebuildVector( 180f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune RegSeqInfo *RSI, const RegSeqInfo *BaseRSI, 181f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune const std::vector<std::pair<unsigned, unsigned> > &RemapChan) const { 182f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune unsigned Reg = RSI->Instr->getOperand(0).getReg(); 183f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune MachineBasicBlock::iterator Pos = RSI->Instr; 184f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune MachineBasicBlock &MBB = *Pos->getParent(); 185f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune DebugLoc DL = Pos->getDebugLoc(); 186f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune 187f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune unsigned SrcVec = BaseRSI->Instr->getOperand(0).getReg(); 188f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune DenseMap<unsigned, unsigned> UpdatedRegToChan = BaseRSI->RegToChan; 189f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune std::vector<unsigned> UpdatedUndef = BaseRSI->UndefReg; 190f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune for (DenseMap<unsigned, unsigned>::iterator It = RSI->RegToChan.begin(), 191f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune E = RSI->RegToChan.end(); It != E; ++It) { 192f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune unsigned DstReg = MRI->createVirtualRegister(&AMDGPU::R600_Reg128RegClass); 193f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune unsigned SubReg = (*It).first; 194f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune unsigned Swizzle = (*It).second; 19581c5d11c25690cdb6282eb0ceb79f487325ce1e6Vincent Lejeune unsigned Chan = getReassignedChan(RemapChan, Swizzle); 19681c5d11c25690cdb6282eb0ceb79f487325ce1e6Vincent Lejeune 197f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune MachineInstr *Tmp = BuildMI(MBB, Pos, DL, TII->get(AMDGPU::INSERT_SUBREG), 198f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune DstReg) 199f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune .addReg(SrcVec) 200f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune .addReg(SubReg) 201f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune .addImm(Chan); 202f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune UpdatedRegToChan[SubReg] = Chan; 2032e0cebd8817bb8bd61a23597bcae6bab9b2845a6Benjamin Kramer std::vector<unsigned>::iterator ChanPos = 2042e0cebd8817bb8bd61a23597bcae6bab9b2845a6Benjamin Kramer std::find(UpdatedUndef.begin(), UpdatedUndef.end(), Chan); 2052e0cebd8817bb8bd61a23597bcae6bab9b2845a6Benjamin Kramer if (ChanPos != UpdatedUndef.end()) 2062e0cebd8817bb8bd61a23597bcae6bab9b2845a6Benjamin Kramer UpdatedUndef.erase(ChanPos); 2072e0cebd8817bb8bd61a23597bcae6bab9b2845a6Benjamin Kramer assert(std::find(UpdatedUndef.begin(), UpdatedUndef.end(), Chan) == 2082e0cebd8817bb8bd61a23597bcae6bab9b2845a6Benjamin Kramer UpdatedUndef.end() && 2092e0cebd8817bb8bd61a23597bcae6bab9b2845a6Benjamin Kramer "UpdatedUndef shouldn't contain Chan more than once!"); 210f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune DEBUG(dbgs() << " ->"; Tmp->dump();); 2117b6d32a361f0f24716b39a37a08302aec0f36723NAKAMURA Takumi (void)Tmp; 212f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune SrcVec = DstReg; 213f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune } 214de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MachineInstr *NewMI = 215de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar BuildMI(MBB, Pos, DL, TII->get(AMDGPU::COPY), Reg).addReg(SrcVec); 216de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar DEBUG(dbgs() << " ->"; NewMI->dump();); 217f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune 218f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune DEBUG(dbgs() << " Updating Swizzle:\n"); 21936b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines for (MachineRegisterInfo::use_instr_iterator It = MRI->use_instr_begin(Reg), 22036b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines E = MRI->use_instr_end(); It != E; ++It) { 221f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune DEBUG(dbgs() << " ";(*It).dump(); dbgs() << " ->"); 222f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune SwizzleInput(*It, RemapChan); 223f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune DEBUG((*It).dump()); 224f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune } 225f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune RSI->Instr->eraseFromParent(); 226f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune 227f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune // Update RSI 228de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar RSI->Instr = NewMI; 229f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune RSI->RegToChan = UpdatedRegToChan; 230f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune RSI->UndefReg = UpdatedUndef; 231f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune 232de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return NewMI; 233f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune} 234f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune 235f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeunevoid R600VectorRegMerger::RemoveMI(MachineInstr *MI) { 236f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune for (InstructionSetMap::iterator It = PreviousRegSeqByReg.begin(), 237f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune E = PreviousRegSeqByReg.end(); It != E; ++It) { 238f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune std::vector<MachineInstr *> &MIs = (*It).second; 239f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune MIs.erase(std::find(MIs.begin(), MIs.end(), MI), MIs.end()); 240f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune } 241f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune for (InstructionSetMap::iterator It = PreviousRegSeqByUndefCount.begin(), 242f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune E = PreviousRegSeqByUndefCount.end(); It != E; ++It) { 243f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune std::vector<MachineInstr *> &MIs = (*It).second; 244f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune MIs.erase(std::find(MIs.begin(), MIs.end(), MI), MIs.end()); 245f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune } 246f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune} 247f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune 248f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeunevoid R600VectorRegMerger::SwizzleInput(MachineInstr &MI, 249f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune const std::vector<std::pair<unsigned, unsigned> > &RemapChan) const { 250f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune unsigned Offset; 251f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune if (TII->get(MI.getOpcode()).TSFlags & R600_InstFlag::TEX_INST) 252f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune Offset = 2; 253f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune else 254f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune Offset = 3; 255f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune for (unsigned i = 0; i < 4; i++) { 256f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune unsigned Swizzle = MI.getOperand(i + Offset).getImm() + 1; 257f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune for (unsigned j = 0, e = RemapChan.size(); j < e; j++) { 258f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune if (RemapChan[j].first == Swizzle) { 259f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune MI.getOperand(i + Offset).setImm(RemapChan[j].second - 1); 260f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune break; 261f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune } 262f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune } 263f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune } 264f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune} 265f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune 266f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeunebool R600VectorRegMerger::areAllUsesSwizzeable(unsigned Reg) const { 26736b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines for (MachineRegisterInfo::use_instr_iterator It = MRI->use_instr_begin(Reg), 26836b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines E = MRI->use_instr_end(); It != E; ++It) { 269f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune if (!canSwizzle(*It)) 270f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune return false; 271f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune } 272f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune return true; 273f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune} 274f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune 275f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeunebool R600VectorRegMerger::tryMergeUsingCommonSlot(RegSeqInfo &RSI, 276f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune RegSeqInfo &CompatibleRSI, 277f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune std::vector<std::pair<unsigned, unsigned> > &RemapChan) { 278f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune for (MachineInstr::mop_iterator MOp = RSI.Instr->operands_begin(), 279f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune MOE = RSI.Instr->operands_end(); MOp != MOE; ++MOp) { 280f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune if (!MOp->isReg()) 281f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune continue; 282f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune if (PreviousRegSeqByReg[MOp->getReg()].empty()) 283f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune continue; 28437ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines for (MachineInstr *MI : PreviousRegSeqByReg[MOp->getReg()]) { 28537ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines CompatibleRSI = PreviousRegSeq[MI]; 286f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune if (RSI == CompatibleRSI) 287f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune continue; 288f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune if (tryMergeVector(&CompatibleRSI, &RSI, RemapChan)) 289f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune return true; 290f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune } 291f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune } 292f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune return false; 293f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune} 294f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune 295f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeunebool R600VectorRegMerger::tryMergeUsingFreeSlot(RegSeqInfo &RSI, 296f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune RegSeqInfo &CompatibleRSI, 297f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune std::vector<std::pair<unsigned, unsigned> > &RemapChan) { 298f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune unsigned NeededUndefs = 4 - RSI.UndefReg.size(); 299f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune if (PreviousRegSeqByUndefCount[NeededUndefs].empty()) 300f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune return false; 301f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune std::vector<MachineInstr *> &MIs = 302f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune PreviousRegSeqByUndefCount[NeededUndefs]; 303f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune CompatibleRSI = PreviousRegSeq[MIs.back()]; 304f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune tryMergeVector(&CompatibleRSI, &RSI, RemapChan); 305f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune return true; 306f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune} 307f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune 308f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeunevoid R600VectorRegMerger::trackRSI(const RegSeqInfo &RSI) { 309f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune for (DenseMap<unsigned, unsigned>::const_iterator 310f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune It = RSI.RegToChan.begin(), E = RSI.RegToChan.end(); It != E; ++It) { 311f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune PreviousRegSeqByReg[(*It).first].push_back(RSI.Instr); 312f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune } 313f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune PreviousRegSeqByUndefCount[RSI.UndefReg.size()].push_back(RSI.Instr); 314f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune PreviousRegSeq[RSI.Instr] = RSI; 315f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune} 316f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune 317f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeunebool R600VectorRegMerger::runOnMachineFunction(MachineFunction &Fn) { 318de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (skipFunction(*Fn.getFunction())) 319de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return false; 320de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 321de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar const R600Subtarget &ST = Fn.getSubtarget<R600Subtarget>(); 322de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar TII = ST.getInstrInfo(); 323de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MRI = &Fn.getRegInfo(); 324de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 325f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end(); 326f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune MBB != MBBe; ++MBB) { 327f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar MachineBasicBlock *MB = &*MBB; 328f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune PreviousRegSeq.clear(); 329f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune PreviousRegSeqByReg.clear(); 330f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune PreviousRegSeqByUndefCount.clear(); 331f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune 332f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune for (MachineBasicBlock::iterator MII = MB->begin(), MIIE = MB->end(); 333f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune MII != MIIE; ++MII) { 334de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MachineInstr &MI = *MII; 335de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (MI.getOpcode() != AMDGPU::REG_SEQUENCE) { 336de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (TII->get(MI.getOpcode()).TSFlags & R600_InstFlag::TEX_INST) { 337de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar unsigned Reg = MI.getOperand(1).getReg(); 33836b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines for (MachineRegisterInfo::def_instr_iterator 33936b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines It = MRI->def_instr_begin(Reg), E = MRI->def_instr_end(); 34036b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines It != E; ++It) { 34126db9ecfac98b2edbb5d45e13547e882bc2c3c03Vincent Lejeune RemoveMI(&(*It)); 34226db9ecfac98b2edbb5d45e13547e882bc2c3c03Vincent Lejeune } 34326db9ecfac98b2edbb5d45e13547e882bc2c3c03Vincent Lejeune } 344f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune continue; 34526db9ecfac98b2edbb5d45e13547e882bc2c3c03Vincent Lejeune } 34626db9ecfac98b2edbb5d45e13547e882bc2c3c03Vincent Lejeune 347de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar RegSeqInfo RSI(*MRI, &MI); 348f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune 349f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune // All uses of MI are swizzeable ? 350de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar unsigned Reg = MI.getOperand(0).getReg(); 351f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune if (!areAllUsesSwizzeable(Reg)) 352f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune continue; 353f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune 354de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar DEBUG({ 355de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar dbgs() << "Trying to optimize "; 356de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MI.dump(); 357de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar }); 358f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune 359f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune RegSeqInfo CandidateRSI; 360f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune std::vector<std::pair<unsigned, unsigned> > RemapChan; 361f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune DEBUG(dbgs() << "Using common slots...\n";); 362f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune if (tryMergeUsingCommonSlot(RSI, CandidateRSI, RemapChan)) { 363f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune // Remove CandidateRSI mapping 364f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune RemoveMI(CandidateRSI.Instr); 365f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune MII = RebuildVector(&RSI, &CandidateRSI, RemapChan); 366f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune trackRSI(RSI); 367f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune continue; 368f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune } 369f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune DEBUG(dbgs() << "Using free slots...\n";); 370f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune RemapChan.clear(); 371f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune if (tryMergeUsingFreeSlot(RSI, CandidateRSI, RemapChan)) { 372f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune RemoveMI(CandidateRSI.Instr); 373f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune MII = RebuildVector(&RSI, &CandidateRSI, RemapChan); 374f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune trackRSI(RSI); 375f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune continue; 376f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune } 377f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune //Failed to merge 378f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune trackRSI(RSI); 379f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune } 380f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune } 381f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune return false; 382f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune} 383f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune 384f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune} 385f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune 386f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeunellvm::FunctionPass *llvm::createR600VectorRegMerger(TargetMachine &tm) { 387f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune return new R600VectorRegMerger(tm); 388f3d6e32c09ac73b49628f5ec7066af5eca2737b5Vincent Lejeune} 389