ARMISelLowering.h revision 55d42003368c57d3a41c5f464d39b8440050d558
1//===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that ARM uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#ifndef ARMISELLOWERING_H 16#define ARMISELLOWERING_H 17 18#include "ARMSubtarget.h" 19#include "llvm/Target/TargetLowering.h" 20#include "llvm/Target/TargetRegisterInfo.h" 21#include "llvm/CodeGen/FastISel.h" 22#include "llvm/CodeGen/SelectionDAG.h" 23#include "llvm/CodeGen/CallingConvLower.h" 24#include <vector> 25 26namespace llvm { 27 class ARMConstantPoolValue; 28 29 namespace ARMISD { 30 // ARM Specific DAG Nodes 31 enum NodeType { 32 // Start the numbering where the builtin ops and target ops leave off. 33 FIRST_NUMBER = ISD::BUILTIN_OP_END, 34 35 Wrapper, // Wrapper - A wrapper node for TargetConstantPool, 36 // TargetExternalSymbol, and TargetGlobalAddress. 37 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable 38 39 CALL, // Function call. 40 CALL_PRED, // Function call that's predicable. 41 CALL_NOLINK, // Function call with branch not branch-and-link. 42 tCALL, // Thumb function call. 43 BRCOND, // Conditional branch. 44 BR_JT, // Jumptable branch. 45 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump). 46 RET_FLAG, // Return with a flag operand. 47 48 PIC_ADD, // Add with a PC operand and a PIC label. 49 50 CMP, // ARM compare instructions. 51 CMPZ, // ARM compare that sets only Z flag. 52 CMPFP, // ARM VFP compare instruction, sets FPSCR. 53 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR. 54 FMSTAT, // ARM fmstat instruction. 55 CMOV, // ARM conditional move instructions. 56 CNEG, // ARM conditional negate instructions. 57 58 BCC_i64, 59 60 RBIT, // ARM bitreverse instruction 61 62 FTOSI, // FP to sint within a FP register. 63 FTOUI, // FP to uint within a FP register. 64 SITOF, // sint to FP within a FP register. 65 UITOF, // uint to FP within a FP register. 66 67 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out. 68 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out. 69 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag. 70 71 VMOVRRD, // double to two gprs. 72 VMOVDRR, // Two gprs to double. 73 74 EH_SJLJ_SETJMP, // SjLj exception handling setjmp. 75 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp. 76 EH_SJLJ_DISPATCHSETUP, // SjLj exception handling dispatch setup. 77 78 TC_RETURN, // Tail call return pseudo. 79 80 THREAD_POINTER, 81 82 DYN_ALLOC, // Dynamic allocation on the stack. 83 84 MEMBARRIER, // Memory barrier (DMB) 85 MEMBARRIER_MCR, // Memory barrier (MCR) 86 87 PRELOAD, // Preload 88 89 VCEQ, // Vector compare equal. 90 VCEQZ, // Vector compare equal to zero. 91 VCGE, // Vector compare greater than or equal. 92 VCGEZ, // Vector compare greater than or equal to zero. 93 VCLEZ, // Vector compare less than or equal to zero. 94 VCGEU, // Vector compare unsigned greater than or equal. 95 VCGT, // Vector compare greater than. 96 VCGTZ, // Vector compare greater than zero. 97 VCLTZ, // Vector compare less than zero. 98 VCGTU, // Vector compare unsigned greater than. 99 VTST, // Vector test bits. 100 101 // Vector shift by immediate: 102 VSHL, // ...left 103 VSHRs, // ...right (signed) 104 VSHRu, // ...right (unsigned) 105 VSHLLs, // ...left long (signed) 106 VSHLLu, // ...left long (unsigned) 107 VSHLLi, // ...left long (with maximum shift count) 108 VSHRN, // ...right narrow 109 110 // Vector rounding shift by immediate: 111 VRSHRs, // ...right (signed) 112 VRSHRu, // ...right (unsigned) 113 VRSHRN, // ...right narrow 114 115 // Vector saturating shift by immediate: 116 VQSHLs, // ...left (signed) 117 VQSHLu, // ...left (unsigned) 118 VQSHLsu, // ...left (signed to unsigned) 119 VQSHRNs, // ...right narrow (signed) 120 VQSHRNu, // ...right narrow (unsigned) 121 VQSHRNsu, // ...right narrow (signed to unsigned) 122 123 // Vector saturating rounding shift by immediate: 124 VQRSHRNs, // ...right narrow (signed) 125 VQRSHRNu, // ...right narrow (unsigned) 126 VQRSHRNsu, // ...right narrow (signed to unsigned) 127 128 // Vector shift and insert: 129 VSLI, // ...left 130 VSRI, // ...right 131 132 // Vector get lane (VMOV scalar to ARM core register) 133 // (These are used for 8- and 16-bit element types only.) 134 VGETLANEu, // zero-extend vector extract element 135 VGETLANEs, // sign-extend vector extract element 136 137 // Vector move immediate and move negated immediate: 138 VMOVIMM, 139 VMVNIMM, 140 141 // Vector duplicate: 142 VDUP, 143 VDUPLANE, 144 145 // Vector shuffles: 146 VEXT, // extract 147 VREV64, // reverse elements within 64-bit doublewords 148 VREV32, // reverse elements within 32-bit words 149 VREV16, // reverse elements within 16-bit halfwords 150 VZIP, // zip (interleave) 151 VUZP, // unzip (deinterleave) 152 VTRN, // transpose 153 154 // Vector multiply long: 155 VMULLs, // ...signed 156 VMULLu, // ...unsigned 157 158 // Operands of the standard BUILD_VECTOR node are not legalized, which 159 // is fine if BUILD_VECTORs are always lowered to shuffles or other 160 // operations, but for ARM some BUILD_VECTORs are legal as-is and their 161 // operands need to be legalized. Define an ARM-specific version of 162 // BUILD_VECTOR for this purpose. 163 BUILD_VECTOR, 164 165 // Floating-point max and min: 166 FMAX, 167 FMIN, 168 169 // Bit-field insert 170 BFI, 171 172 // Vector OR with immediate 173 VORRIMM, 174 // Vector AND with NOT of immediate 175 VBICIMM, 176 177 // Vector load N-element structure to all lanes: 178 VLD2DUP = ISD::FIRST_TARGET_MEMORY_OPCODE, 179 VLD3DUP, 180 VLD4DUP 181 }; 182 } 183 184 /// Define some predicates that are used for node matching. 185 namespace ARM { 186 /// getVFPf32Imm / getVFPf64Imm - If the given fp immediate can be 187 /// materialized with a VMOV.f32 / VMOV.f64 (i.e. fconsts / fconstd) 188 /// instruction, returns its 8-bit integer representation. Otherwise, 189 /// returns -1. 190 int getVFPf32Imm(const APFloat &FPImm); 191 int getVFPf64Imm(const APFloat &FPImm); 192 bool isBitFieldInvertedMask(unsigned v); 193 } 194 195 //===--------------------------------------------------------------------===// 196 // ARMTargetLowering - ARM Implementation of the TargetLowering interface 197 198 class ARMTargetLowering : public TargetLowering { 199 public: 200 explicit ARMTargetLowering(TargetMachine &TM); 201 202 virtual unsigned getJumpTableEncoding(void) const; 203 204 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 205 206 /// ReplaceNodeResults - Replace the results of node with an illegal result 207 /// type with new values built out of custom code. 208 /// 209 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 210 SelectionDAG &DAG) const; 211 212 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 213 214 virtual const char *getTargetNodeName(unsigned Opcode) const; 215 216 virtual MachineBasicBlock * 217 EmitInstrWithCustomInserter(MachineInstr *MI, 218 MachineBasicBlock *MBB) const; 219 220 /// allowsUnalignedMemoryAccesses - Returns true if the target allows 221 /// unaligned memory accesses. of the specified type. 222 /// FIXME: Add getOptimalMemOpType to implement memcpy with NEON? 223 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const; 224 225 /// isLegalAddressingMode - Return true if the addressing mode represented 226 /// by AM is legal for this target, for a load/store of the specified type. 227 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const; 228 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const; 229 230 /// isLegalICmpImmediate - Return true if the specified immediate is legal 231 /// icmp immediate, that is the target has icmp instructions which can 232 /// compare a register against the immediate without having to materialize 233 /// the immediate into a register. 234 virtual bool isLegalICmpImmediate(int64_t Imm) const; 235 236 /// getPreIndexedAddressParts - returns true by value, base pointer and 237 /// offset pointer and addressing mode by reference if the node's address 238 /// can be legally represented as pre-indexed load / store address. 239 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, 240 SDValue &Offset, 241 ISD::MemIndexedMode &AM, 242 SelectionDAG &DAG) const; 243 244 /// getPostIndexedAddressParts - returns true by value, base pointer and 245 /// offset pointer and addressing mode by reference if this node can be 246 /// combined with a load / store to form a post-indexed load / store. 247 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, 248 SDValue &Base, SDValue &Offset, 249 ISD::MemIndexedMode &AM, 250 SelectionDAG &DAG) const; 251 252 virtual void computeMaskedBitsForTargetNode(const SDValue Op, 253 const APInt &Mask, 254 APInt &KnownZero, 255 APInt &KnownOne, 256 const SelectionDAG &DAG, 257 unsigned Depth) const; 258 259 260 virtual bool ExpandInlineAsm(CallInst *CI) const; 261 262 ConstraintType getConstraintType(const std::string &Constraint) const; 263 264 /// Examine constraint string and operand type and determine a weight value. 265 /// The operand object must already have been set up with the operand type. 266 ConstraintWeight getSingleConstraintMatchWeight( 267 AsmOperandInfo &info, const char *constraint) const; 268 269 std::pair<unsigned, const TargetRegisterClass*> 270 getRegForInlineAsmConstraint(const std::string &Constraint, 271 EVT VT) const; 272 std::vector<unsigned> 273 getRegClassForInlineAsmConstraint(const std::string &Constraint, 274 EVT VT) const; 275 276 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 277 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is 278 /// true it means one of the asm constraint of the inline asm instruction 279 /// being processed is 'm'. 280 virtual void LowerAsmOperandForConstraint(SDValue Op, 281 char ConstraintLetter, 282 std::vector<SDValue> &Ops, 283 SelectionDAG &DAG) const; 284 285 const ARMSubtarget* getSubtarget() const { 286 return Subtarget; 287 } 288 289 /// getRegClassFor - Return the register class that should be used for the 290 /// specified value type. 291 virtual TargetRegisterClass *getRegClassFor(EVT VT) const; 292 293 /// getFunctionAlignment - Return the Log2 alignment of this function. 294 virtual unsigned getFunctionAlignment(const Function *F) const; 295 296 /// getMaximalGlobalOffset - Returns the maximal possible offset which can 297 /// be used for loads / stores from the global. 298 virtual unsigned getMaximalGlobalOffset() const; 299 300 /// createFastISel - This method returns a target specific FastISel object, 301 /// or null if the target does not support "fast" ISel. 302 virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo) const; 303 304 Sched::Preference getSchedulingPreference(SDNode *N) const; 305 306 unsigned getRegPressureLimit(const TargetRegisterClass *RC, 307 MachineFunction &MF) const; 308 309 bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const; 310 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; 311 312 /// isFPImmLegal - Returns true if the target can instruction select the 313 /// specified FP immediate natively. If false, the legalizer will 314 /// materialize the FP immediate as a load from a constant pool. 315 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const; 316 317 virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info, 318 const CallInst &I, 319 unsigned Intrinsic) const; 320 protected: 321 std::pair<const TargetRegisterClass*, uint8_t> 322 findRepresentativeClass(EVT VT) const; 323 324 private: 325 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can 326 /// make the right decision when generating code for different targets. 327 const ARMSubtarget *Subtarget; 328 329 const TargetRegisterInfo *RegInfo; 330 331 const InstrItineraryData *Itins; 332 333 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created. 334 /// 335 unsigned ARMPCLabelIndex; 336 337 void addTypeForNEON(EVT VT, EVT PromotedLdStVT, EVT PromotedBitwiseVT); 338 void addDRTypeForNEON(EVT VT); 339 void addQRTypeForNEON(EVT VT); 340 341 typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector; 342 void PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG, 343 SDValue Chain, SDValue &Arg, 344 RegsToPassVector &RegsToPass, 345 CCValAssign &VA, CCValAssign &NextVA, 346 SDValue &StackPtr, 347 SmallVector<SDValue, 8> &MemOpChains, 348 ISD::ArgFlagsTy Flags) const; 349 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA, 350 SDValue &Root, SelectionDAG &DAG, 351 DebugLoc dl) const; 352 353 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return, 354 bool isVarArg) const; 355 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg, 356 DebugLoc dl, SelectionDAG &DAG, 357 const CCValAssign &VA, 358 ISD::ArgFlagsTy Flags) const; 359 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const; 360 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const; 361 SDValue LowerEH_SJLJ_DISPATCHSETUP(SDValue Op, SelectionDAG &DAG) const; 362 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG, 363 const ARMSubtarget *Subtarget) const; 364 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 365 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const; 366 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const; 367 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 368 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, 369 SelectionDAG &DAG) const; 370 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA, 371 SelectionDAG &DAG) const; 372 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const; 373 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const; 374 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; 375 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 376 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const; 377 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const; 378 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 379 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 380 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const; 381 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const; 382 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const; 383 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG, 384 const ARMSubtarget *ST) const; 385 386 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const; 387 388 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 389 CallingConv::ID CallConv, bool isVarArg, 390 const SmallVectorImpl<ISD::InputArg> &Ins, 391 DebugLoc dl, SelectionDAG &DAG, 392 SmallVectorImpl<SDValue> &InVals) const; 393 394 virtual SDValue 395 LowerFormalArguments(SDValue Chain, 396 CallingConv::ID CallConv, bool isVarArg, 397 const SmallVectorImpl<ISD::InputArg> &Ins, 398 DebugLoc dl, SelectionDAG &DAG, 399 SmallVectorImpl<SDValue> &InVals) const; 400 401 virtual SDValue 402 LowerCall(SDValue Chain, SDValue Callee, 403 CallingConv::ID CallConv, bool isVarArg, 404 bool &isTailCall, 405 const SmallVectorImpl<ISD::OutputArg> &Outs, 406 const SmallVectorImpl<SDValue> &OutVals, 407 const SmallVectorImpl<ISD::InputArg> &Ins, 408 DebugLoc dl, SelectionDAG &DAG, 409 SmallVectorImpl<SDValue> &InVals) const; 410 411 /// IsEligibleForTailCallOptimization - Check whether the call is eligible 412 /// for tail call optimization. Targets which want to do tail call 413 /// optimization should implement this function. 414 bool IsEligibleForTailCallOptimization(SDValue Callee, 415 CallingConv::ID CalleeCC, 416 bool isVarArg, 417 bool isCalleeStructRet, 418 bool isCallerStructRet, 419 const SmallVectorImpl<ISD::OutputArg> &Outs, 420 const SmallVectorImpl<SDValue> &OutVals, 421 const SmallVectorImpl<ISD::InputArg> &Ins, 422 SelectionDAG& DAG) const; 423 virtual SDValue 424 LowerReturn(SDValue Chain, 425 CallingConv::ID CallConv, bool isVarArg, 426 const SmallVectorImpl<ISD::OutputArg> &Outs, 427 const SmallVectorImpl<SDValue> &OutVals, 428 DebugLoc dl, SelectionDAG &DAG) const; 429 430 virtual bool isUsedByReturnOnly(SDNode *N) const; 431 432 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, 433 SDValue &ARMcc, SelectionDAG &DAG, DebugLoc dl) const; 434 SDValue getVFPCmp(SDValue LHS, SDValue RHS, 435 SelectionDAG &DAG, DebugLoc dl) const; 436 437 SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const; 438 439 MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI, 440 MachineBasicBlock *BB, 441 unsigned Size) const; 442 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI, 443 MachineBasicBlock *BB, 444 unsigned Size, 445 unsigned BinOpcode) const; 446 447 }; 448 449 enum NEONModImmType { 450 VMOVModImm, 451 VMVNModImm, 452 OtherModImm 453 }; 454 455 456 namespace ARM { 457 FastISel *createFastISel(FunctionLoweringInfo &funcInfo); 458 } 459} 460 461#endif // ARMISELLOWERING_H 462