ARMISelLowering.h revision 61f4dfe3693bf68b20748d82ac4dd9bf2f356699
1//===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that ARM uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef ARMISELLOWERING_H
16#define ARMISELLOWERING_H
17
18#include "ARM.h"
19#include "ARMSubtarget.h"
20#include "llvm/CodeGen/CallingConvLower.h"
21#include "llvm/CodeGen/FastISel.h"
22#include "llvm/CodeGen/SelectionDAG.h"
23#include "llvm/Target/TargetLowering.h"
24#include "llvm/Target/TargetRegisterInfo.h"
25#include "llvm/Target/TargetTransformImpl.h"
26#include <vector>
27
28namespace llvm {
29  class ARMConstantPoolValue;
30
31  namespace ARMISD {
32    // ARM Specific DAG Nodes
33    enum NodeType {
34      // Start the numbering where the builtin ops and target ops leave off.
35      FIRST_NUMBER = ISD::BUILTIN_OP_END,
36
37      Wrapper,      // Wrapper - A wrapper node for TargetConstantPool,
38                    // TargetExternalSymbol, and TargetGlobalAddress.
39      WrapperDYN,   // WrapperDYN - A wrapper node for TargetGlobalAddress in
40                    // DYN mode.
41      WrapperPIC,   // WrapperPIC - A wrapper node for TargetGlobalAddress in
42                    // PIC mode.
43      WrapperJT,    // WrapperJT - A wrapper node for TargetJumpTable
44
45      // Add pseudo op to model memcpy for struct byval.
46      COPY_STRUCT_BYVAL,
47
48      CALL,         // Function call.
49      CALL_PRED,    // Function call that's predicable.
50      CALL_NOLINK,  // Function call with branch not branch-and-link.
51      tCALL,        // Thumb function call.
52      BRCOND,       // Conditional branch.
53      BR_JT,        // Jumptable branch.
54      BR2_JT,       // Jumptable branch (2 level - jumptable entry is a jump).
55      RET_FLAG,     // Return with a flag operand.
56
57      PIC_ADD,      // Add with a PC operand and a PIC label.
58
59      CMP,          // ARM compare instructions.
60      CMN,          // ARM CMN instructions.
61      CMPZ,         // ARM compare that sets only Z flag.
62      CMPFP,        // ARM VFP compare instruction, sets FPSCR.
63      CMPFPw0,      // ARM VFP compare against zero instruction, sets FPSCR.
64      FMSTAT,       // ARM fmstat instruction.
65
66      CMOV,         // ARM conditional move instructions.
67
68      BCC_i64,
69
70      RBIT,         // ARM bitreverse instruction
71
72      FTOSI,        // FP to sint within a FP register.
73      FTOUI,        // FP to uint within a FP register.
74      SITOF,        // sint to FP within a FP register.
75      UITOF,        // uint to FP within a FP register.
76
77      SRL_FLAG,     // V,Flag = srl_flag X -> srl X, 1 + save carry out.
78      SRA_FLAG,     // V,Flag = sra_flag X -> sra X, 1 + save carry out.
79      RRX,          // V = RRX X, Flag     -> srl X, 1 + shift in carry flag.
80
81      ADDC,         // Add with carry
82      ADDE,         // Add using carry
83      SUBC,         // Sub with carry
84      SUBE,         // Sub using carry
85
86      VMOVRRD,      // double to two gprs.
87      VMOVDRR,      // Two gprs to double.
88
89      EH_SJLJ_SETJMP,         // SjLj exception handling setjmp.
90      EH_SJLJ_LONGJMP,        // SjLj exception handling longjmp.
91
92      TC_RETURN,    // Tail call return pseudo.
93
94      THREAD_POINTER,
95
96      DYN_ALLOC,    // Dynamic allocation on the stack.
97
98      MEMBARRIER,   // Memory barrier (DMB)
99      MEMBARRIER_MCR, // Memory barrier (MCR)
100
101      PRELOAD,      // Preload
102
103      VCEQ,         // Vector compare equal.
104      VCEQZ,        // Vector compare equal to zero.
105      VCGE,         // Vector compare greater than or equal.
106      VCGEZ,        // Vector compare greater than or equal to zero.
107      VCLEZ,        // Vector compare less than or equal to zero.
108      VCGEU,        // Vector compare unsigned greater than or equal.
109      VCGT,         // Vector compare greater than.
110      VCGTZ,        // Vector compare greater than zero.
111      VCLTZ,        // Vector compare less than zero.
112      VCGTU,        // Vector compare unsigned greater than.
113      VTST,         // Vector test bits.
114
115      // Vector shift by immediate:
116      VSHL,         // ...left
117      VSHRs,        // ...right (signed)
118      VSHRu,        // ...right (unsigned)
119      VSHLLs,       // ...left long (signed)
120      VSHLLu,       // ...left long (unsigned)
121      VSHLLi,       // ...left long (with maximum shift count)
122      VSHRN,        // ...right narrow
123
124      // Vector rounding shift by immediate:
125      VRSHRs,       // ...right (signed)
126      VRSHRu,       // ...right (unsigned)
127      VRSHRN,       // ...right narrow
128
129      // Vector saturating shift by immediate:
130      VQSHLs,       // ...left (signed)
131      VQSHLu,       // ...left (unsigned)
132      VQSHLsu,      // ...left (signed to unsigned)
133      VQSHRNs,      // ...right narrow (signed)
134      VQSHRNu,      // ...right narrow (unsigned)
135      VQSHRNsu,     // ...right narrow (signed to unsigned)
136
137      // Vector saturating rounding shift by immediate:
138      VQRSHRNs,     // ...right narrow (signed)
139      VQRSHRNu,     // ...right narrow (unsigned)
140      VQRSHRNsu,    // ...right narrow (signed to unsigned)
141
142      // Vector shift and insert:
143      VSLI,         // ...left
144      VSRI,         // ...right
145
146      // Vector get lane (VMOV scalar to ARM core register)
147      // (These are used for 8- and 16-bit element types only.)
148      VGETLANEu,    // zero-extend vector extract element
149      VGETLANEs,    // sign-extend vector extract element
150
151      // Vector move immediate and move negated immediate:
152      VMOVIMM,
153      VMVNIMM,
154
155      // Vector move f32 immediate:
156      VMOVFPIMM,
157
158      // Vector duplicate:
159      VDUP,
160      VDUPLANE,
161
162      // Vector shuffles:
163      VEXT,         // extract
164      VREV64,       // reverse elements within 64-bit doublewords
165      VREV32,       // reverse elements within 32-bit words
166      VREV16,       // reverse elements within 16-bit halfwords
167      VZIP,         // zip (interleave)
168      VUZP,         // unzip (deinterleave)
169      VTRN,         // transpose
170      VTBL1,        // 1-register shuffle with mask
171      VTBL2,        // 2-register shuffle with mask
172
173      // Vector multiply long:
174      VMULLs,       // ...signed
175      VMULLu,       // ...unsigned
176
177      UMLAL,        // 64bit Unsigned Accumulate Multiply
178      SMLAL,        // 64bit Signed Accumulate Multiply
179
180      // Operands of the standard BUILD_VECTOR node are not legalized, which
181      // is fine if BUILD_VECTORs are always lowered to shuffles or other
182      // operations, but for ARM some BUILD_VECTORs are legal as-is and their
183      // operands need to be legalized.  Define an ARM-specific version of
184      // BUILD_VECTOR for this purpose.
185      BUILD_VECTOR,
186
187      // Floating-point max and min:
188      FMAX,
189      FMIN,
190
191      // Bit-field insert
192      BFI,
193
194      // Vector OR with immediate
195      VORRIMM,
196      // Vector AND with NOT of immediate
197      VBICIMM,
198
199      // Vector bitwise select
200      VBSL,
201
202      // Vector load N-element structure to all lanes:
203      VLD2DUP = ISD::FIRST_TARGET_MEMORY_OPCODE,
204      VLD3DUP,
205      VLD4DUP,
206
207      // NEON loads with post-increment base updates:
208      VLD1_UPD,
209      VLD2_UPD,
210      VLD3_UPD,
211      VLD4_UPD,
212      VLD2LN_UPD,
213      VLD3LN_UPD,
214      VLD4LN_UPD,
215      VLD2DUP_UPD,
216      VLD3DUP_UPD,
217      VLD4DUP_UPD,
218
219      // NEON stores with post-increment base updates:
220      VST1_UPD,
221      VST2_UPD,
222      VST3_UPD,
223      VST4_UPD,
224      VST2LN_UPD,
225      VST3LN_UPD,
226      VST4LN_UPD,
227
228      // 64-bit atomic ops (value split into two registers)
229      ATOMADD64_DAG,
230      ATOMSUB64_DAG,
231      ATOMOR64_DAG,
232      ATOMXOR64_DAG,
233      ATOMAND64_DAG,
234      ATOMNAND64_DAG,
235      ATOMSWAP64_DAG,
236      ATOMCMPXCHG64_DAG,
237      ATOMMIN64_DAG,
238      ATOMUMIN64_DAG,
239      ATOMMAX64_DAG,
240      ATOMUMAX64_DAG
241    };
242  }
243
244  /// Define some predicates that are used for node matching.
245  namespace ARM {
246    bool isBitFieldInvertedMask(unsigned v);
247  }
248
249  //===--------------------------------------------------------------------===//
250  //  ARMTargetLowering - ARM Implementation of the TargetLowering interface
251
252  class ARMTargetLowering : public TargetLowering {
253  public:
254    explicit ARMTargetLowering(TargetMachine &TM);
255
256    virtual unsigned getJumpTableEncoding() const;
257
258    virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
259
260    /// ReplaceNodeResults - Replace the results of node with an illegal result
261    /// type with new values built out of custom code.
262    ///
263    virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
264                                    SelectionDAG &DAG) const;
265
266    virtual const char *getTargetNodeName(unsigned Opcode) const;
267
268    virtual bool isSelectSupported(SelectSupportKind Kind) const {
269      // ARM does not support scalar condition selects on vectors.
270      return (Kind != ScalarCondVectorVal);
271    }
272
273    /// getSetCCResultType - Return the value type to use for ISD::SETCC.
274    virtual EVT getSetCCResultType(EVT VT) const;
275
276    virtual MachineBasicBlock *
277      EmitInstrWithCustomInserter(MachineInstr *MI,
278                                  MachineBasicBlock *MBB) const;
279
280    virtual void
281    AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const;
282
283    SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
284    virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
285
286    bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const;
287
288    /// allowsUnalignedMemoryAccesses - Returns true if the target allows
289    /// unaligned memory accesses of the specified type. Returns whether it
290    /// is "fast" by reference in the second argument.
291    virtual bool allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const;
292
293    virtual EVT getOptimalMemOpType(uint64_t Size,
294                                    unsigned DstAlign, unsigned SrcAlign,
295                                    bool IsZeroVal,
296                                    bool MemcpyStrSrc,
297                                    MachineFunction &MF) const;
298
299    /// isLegalMemOpType - Returns true if it's legal to use load / store of the
300    /// specified type to expand memcpy / memset inline. This is mostly true
301    /// for legal types except for some special cases. For example, on X86
302    /// targets without SSE2 f64 load / store are done with fldl / fstpl which
303    /// also does type conversion.
304    virtual bool isLegalMemOpType(MVT VT) const;
305
306    using TargetLowering::isZExtFree;
307    virtual bool isZExtFree(SDValue Val, EVT VT2) const;
308
309    /// isLegalAddressingMode - Return true if the addressing mode represented
310    /// by AM is legal for this target, for a load/store of the specified type.
311    virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const;
312    bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
313
314    /// isLegalICmpImmediate - Return true if the specified immediate is legal
315    /// icmp immediate, that is the target has icmp instructions which can
316    /// compare a register against the immediate without having to materialize
317    /// the immediate into a register.
318    virtual bool isLegalICmpImmediate(int64_t Imm) const;
319
320    /// isLegalAddImmediate - Return true if the specified immediate is legal
321    /// add immediate, that is the target has add instructions which can
322    /// add a register and the immediate without having to materialize
323    /// the immediate into a register.
324    virtual bool isLegalAddImmediate(int64_t Imm) const;
325
326    /// getPreIndexedAddressParts - returns true by value, base pointer and
327    /// offset pointer and addressing mode by reference if the node's address
328    /// can be legally represented as pre-indexed load / store address.
329    virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
330                                           SDValue &Offset,
331                                           ISD::MemIndexedMode &AM,
332                                           SelectionDAG &DAG) const;
333
334    /// getPostIndexedAddressParts - returns true by value, base pointer and
335    /// offset pointer and addressing mode by reference if this node can be
336    /// combined with a load / store to form a post-indexed load / store.
337    virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
338                                            SDValue &Base, SDValue &Offset,
339                                            ISD::MemIndexedMode &AM,
340                                            SelectionDAG &DAG) const;
341
342    virtual void computeMaskedBitsForTargetNode(const SDValue Op,
343                                                APInt &KnownZero,
344                                                APInt &KnownOne,
345                                                const SelectionDAG &DAG,
346                                                unsigned Depth) const;
347
348
349    virtual bool ExpandInlineAsm(CallInst *CI) const;
350
351    ConstraintType getConstraintType(const std::string &Constraint) const;
352
353    /// Examine constraint string and operand type and determine a weight value.
354    /// The operand object must already have been set up with the operand type.
355    ConstraintWeight getSingleConstraintMatchWeight(
356      AsmOperandInfo &info, const char *constraint) const;
357
358    std::pair<unsigned, const TargetRegisterClass*>
359      getRegForInlineAsmConstraint(const std::string &Constraint,
360                                   EVT VT) const;
361
362    /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
363    /// vector.  If it is invalid, don't add anything to Ops. If hasMemory is
364    /// true it means one of the asm constraint of the inline asm instruction
365    /// being processed is 'm'.
366    virtual void LowerAsmOperandForConstraint(SDValue Op,
367                                              std::string &Constraint,
368                                              std::vector<SDValue> &Ops,
369                                              SelectionDAG &DAG) const;
370
371    const ARMSubtarget* getSubtarget() const {
372      return Subtarget;
373    }
374
375    /// getRegClassFor - Return the register class that should be used for the
376    /// specified value type.
377    virtual const TargetRegisterClass *getRegClassFor(EVT VT) const;
378
379    /// getMaximalGlobalOffset - Returns the maximal possible offset which can
380    /// be used for loads / stores from the global.
381    virtual unsigned getMaximalGlobalOffset() const;
382
383    /// createFastISel - This method returns a target specific FastISel object,
384    /// or null if the target does not support "fast" ISel.
385    virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
386                                     const TargetLibraryInfo *libInfo) const;
387
388    Sched::Preference getSchedulingPreference(SDNode *N) const;
389
390    bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const;
391    bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
392
393    /// isFPImmLegal - Returns true if the target can instruction select the
394    /// specified FP immediate natively. If false, the legalizer will
395    /// materialize the FP immediate as a load from a constant pool.
396    virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
397
398    virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info,
399                                    const CallInst &I,
400                                    unsigned Intrinsic) const;
401  protected:
402    std::pair<const TargetRegisterClass*, uint8_t>
403    findRepresentativeClass(EVT VT) const;
404
405  private:
406    /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
407    /// make the right decision when generating code for different targets.
408    const ARMSubtarget *Subtarget;
409
410    const TargetRegisterInfo *RegInfo;
411
412    const InstrItineraryData *Itins;
413
414    /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
415    ///
416    unsigned ARMPCLabelIndex;
417
418    void addTypeForNEON(MVT VT, MVT PromotedLdStVT, MVT PromotedBitwiseVT);
419    void addDRTypeForNEON(MVT VT);
420    void addQRTypeForNEON(MVT VT);
421
422    typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector;
423    void PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
424                          SDValue Chain, SDValue &Arg,
425                          RegsToPassVector &RegsToPass,
426                          CCValAssign &VA, CCValAssign &NextVA,
427                          SDValue &StackPtr,
428                          SmallVector<SDValue, 8> &MemOpChains,
429                          ISD::ArgFlagsTy Flags) const;
430    SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
431                                 SDValue &Root, SelectionDAG &DAG,
432                                 DebugLoc dl) const;
433
434    CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return,
435                                  bool isVarArg) const;
436    SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
437                             DebugLoc dl, SelectionDAG &DAG,
438                             const CCValAssign &VA,
439                             ISD::ArgFlagsTy Flags) const;
440    SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
441    SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
442    SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
443                                    const ARMSubtarget *Subtarget) const;
444    SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
445    SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
446    SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
447    SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
448    SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
449                                            SelectionDAG &DAG) const;
450    SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
451                                 SelectionDAG &DAG,
452                                 TLSModel::Model model) const;
453    SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
454    SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
455    SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
456    SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
457    SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
458    SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
459    SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
460    SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
461    SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
462    SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
463    SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
464    SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG,
465                            const ARMSubtarget *ST) const;
466    SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
467                              const ARMSubtarget *ST) const;
468
469    SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
470
471    SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
472                            CallingConv::ID CallConv, bool isVarArg,
473                            const SmallVectorImpl<ISD::InputArg> &Ins,
474                            DebugLoc dl, SelectionDAG &DAG,
475                            SmallVectorImpl<SDValue> &InVals) const;
476
477    virtual SDValue
478      LowerFormalArguments(SDValue Chain,
479                           CallingConv::ID CallConv, bool isVarArg,
480                           const SmallVectorImpl<ISD::InputArg> &Ins,
481                           DebugLoc dl, SelectionDAG &DAG,
482                           SmallVectorImpl<SDValue> &InVals) const;
483
484    void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
485                              DebugLoc dl, SDValue &Chain,
486                              const Value *OrigArg,
487                              unsigned OffsetFromOrigArg,
488                              unsigned ArgOffset,
489                              bool ForceMutable = false)
490      const;
491
492    void computeRegArea(CCState &CCInfo, MachineFunction &MF,
493                        unsigned &VARegSize, unsigned &VARegSaveSize) const;
494
495    virtual SDValue
496      LowerCall(TargetLowering::CallLoweringInfo &CLI,
497                SmallVectorImpl<SDValue> &InVals) const;
498
499    /// HandleByVal - Target-specific cleanup for ByVal support.
500    virtual void HandleByVal(CCState *, unsigned &, unsigned) const;
501
502    /// IsEligibleForTailCallOptimization - Check whether the call is eligible
503    /// for tail call optimization. Targets which want to do tail call
504    /// optimization should implement this function.
505    bool IsEligibleForTailCallOptimization(SDValue Callee,
506                                           CallingConv::ID CalleeCC,
507                                           bool isVarArg,
508                                           bool isCalleeStructRet,
509                                           bool isCallerStructRet,
510                                    const SmallVectorImpl<ISD::OutputArg> &Outs,
511                                    const SmallVectorImpl<SDValue> &OutVals,
512                                    const SmallVectorImpl<ISD::InputArg> &Ins,
513                                           SelectionDAG& DAG) const;
514
515    virtual bool CanLowerReturn(CallingConv::ID CallConv,
516                                MachineFunction &MF, bool isVarArg,
517                                const SmallVectorImpl<ISD::OutputArg> &Outs,
518                                LLVMContext &Context) const;
519
520    virtual SDValue
521      LowerReturn(SDValue Chain,
522                  CallingConv::ID CallConv, bool isVarArg,
523                  const SmallVectorImpl<ISD::OutputArg> &Outs,
524                  const SmallVectorImpl<SDValue> &OutVals,
525                  DebugLoc dl, SelectionDAG &DAG) const;
526
527    virtual bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const;
528
529    virtual bool mayBeEmittedAsTailCall(CallInst *CI) const;
530
531    SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
532                      SDValue &ARMcc, SelectionDAG &DAG, DebugLoc dl) const;
533    SDValue getVFPCmp(SDValue LHS, SDValue RHS,
534                      SelectionDAG &DAG, DebugLoc dl) const;
535    SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const;
536
537    SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;
538
539    MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI,
540                                         MachineBasicBlock *BB,
541                                         unsigned Size) const;
542    MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI,
543                                        MachineBasicBlock *BB,
544                                        unsigned Size,
545                                        unsigned BinOpcode) const;
546    MachineBasicBlock *EmitAtomicBinary64(MachineInstr *MI,
547                                          MachineBasicBlock *BB,
548                                          unsigned Op1,
549                                          unsigned Op2,
550                                          bool NeedsCarry = false,
551                                          bool IsCmpxchg = false,
552                                          bool IsMinMax = false,
553                                          ARMCC::CondCodes CC = ARMCC::AL) const;
554    MachineBasicBlock * EmitAtomicBinaryMinMax(MachineInstr *MI,
555                                               MachineBasicBlock *BB,
556                                               unsigned Size,
557                                               bool signExtend,
558                                               ARMCC::CondCodes Cond) const;
559
560    void SetupEntryBlockForSjLj(MachineInstr *MI,
561                                MachineBasicBlock *MBB,
562                                MachineBasicBlock *DispatchBB, int FI) const;
563
564    MachineBasicBlock *EmitSjLjDispatchBlock(MachineInstr *MI,
565                                             MachineBasicBlock *MBB) const;
566
567    bool RemapAddSubWithFlags(MachineInstr *MI, MachineBasicBlock *BB) const;
568
569    MachineBasicBlock *EmitStructByval(MachineInstr *MI,
570                                       MachineBasicBlock *MBB) const;
571  };
572
573  enum NEONModImmType {
574    VMOVModImm,
575    VMVNModImm,
576    OtherModImm
577  };
578
579
580  namespace ARM {
581    FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
582                             const TargetLibraryInfo *libInfo);
583  }
584
585  class ARMScalarTargetTransformImpl : public ScalarTargetTransformImpl {
586    const ARMSubtarget *Subtarget;
587  public:
588    explicit ARMScalarTargetTransformImpl(const TargetLowering *TL) :
589      ScalarTargetTransformImpl(TL),
590      Subtarget(&TL->getTargetMachine().getSubtarget<ARMSubtarget>()) {};
591
592    virtual unsigned getIntImmCost(const APInt &Imm, Type *Ty) const;
593  };
594}
595
596#endif  // ARMISELLOWERING_H
597