ARMISelLowering.h revision 98ca4f2a325f72374a477f9deba7d09e8999c29b 
1//===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that ARM uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef ARMISELLOWERING_H
16#define ARMISELLOWERING_H
17
18#include "ARMSubtarget.h"
19#include "llvm/Target/TargetLowering.h"
20#include "llvm/CodeGen/SelectionDAG.h"
21#include "llvm/CodeGen/CallingConvLower.h"
22#include <vector>
23
24namespace llvm {
25  class ARMConstantPoolValue;
26
27  namespace ARMISD {
28    // ARM Specific DAG Nodes
29    enum NodeType {
30      // Start the numbering where the builtin ops and target ops leave off.
31      FIRST_NUMBER = ISD::BUILTIN_OP_END,
32
33      Wrapper,      // Wrapper - A wrapper node for TargetConstantPool,
34                    // TargetExternalSymbol, and TargetGlobalAddress.
35      WrapperJT,    // WrapperJT - A wrapper node for TargetJumpTable
36
37      CALL,         // Function call.
38      CALL_PRED,    // Function call that's predicable.
39      CALL_NOLINK,  // Function call with branch not branch-and-link.
40      tCALL,        // Thumb function call.
41      BRCOND,       // Conditional branch.
42      BR_JT,        // Jumptable branch.
43      BR2_JT,       // Jumptable branch (2 level - jumptable entry is a jump).
44      RET_FLAG,     // Return with a flag operand.
45
46      PIC_ADD,      // Add with a PC operand and a PIC label.
47
48      CMP,          // ARM compare instructions.
49      CMPZ,         // ARM compare that sets only Z flag.
50      CMPFP,        // ARM VFP compare instruction, sets FPSCR.
51      CMPFPw0,      // ARM VFP compare against zero instruction, sets FPSCR.
52      FMSTAT,       // ARM fmstat instruction.
53      CMOV,         // ARM conditional move instructions.
54      CNEG,         // ARM conditional negate instructions.
55
56      FTOSI,        // FP to sint within a FP register.
57      FTOUI,        // FP to uint within a FP register.
58      SITOF,        // sint to FP within a FP register.
59      UITOF,        // uint to FP within a FP register.
60
61      SRL_FLAG,     // V,Flag = srl_flag X -> srl X, 1 + save carry out.
62      SRA_FLAG,     // V,Flag = sra_flag X -> sra X, 1 + save carry out.
63      RRX,          // V = RRX X, Flag     -> srl X, 1 + shift in carry flag.
64
65      FMRRD,        // double to two gprs.
66      FMDRR,        // Two gprs to double.
67
68      EH_SJLJ_SETJMP,    // SjLj exception handling setjmp
69      EH_SJLJ_LONGJMP,   // SjLj exception handling longjmp
70
71      THREAD_POINTER,
72
73      VCEQ,         // Vector compare equal.
74      VCGE,         // Vector compare greater than or equal.
75      VCGEU,        // Vector compare unsigned greater than or equal.
76      VCGT,         // Vector compare greater than.
77      VCGTU,        // Vector compare unsigned greater than.
78      VTST,         // Vector test bits.
79
80      // Vector shift by immediate:
81      VSHL,         // ...left
82      VSHRs,        // ...right (signed)
83      VSHRu,        // ...right (unsigned)
84      VSHLLs,       // ...left long (signed)
85      VSHLLu,       // ...left long (unsigned)
86      VSHLLi,       // ...left long (with maximum shift count)
87      VSHRN,        // ...right narrow
88
89      // Vector rounding shift by immediate:
90      VRSHRs,       // ...right (signed)
91      VRSHRu,       // ...right (unsigned)
92      VRSHRN,       // ...right narrow
93
94      // Vector saturating shift by immediate:
95      VQSHLs,       // ...left (signed)
96      VQSHLu,       // ...left (unsigned)
97      VQSHLsu,      // ...left (signed to unsigned)
98      VQSHRNs,      // ...right narrow (signed)
99      VQSHRNu,      // ...right narrow (unsigned)
100      VQSHRNsu,     // ...right narrow (signed to unsigned)
101
102      // Vector saturating rounding shift by immediate:
103      VQRSHRNs,     // ...right narrow (signed)
104      VQRSHRNu,     // ...right narrow (unsigned)
105      VQRSHRNsu,    // ...right narrow (signed to unsigned)
106
107      // Vector shift and insert:
108      VSLI,         // ...left
109      VSRI,         // ...right
110
111      // Vector get lane (VMOV scalar to ARM core register)
112      // (These are used for 8- and 16-bit element types only.)
113      VGETLANEu,    // zero-extend vector extract element
114      VGETLANEs,    // sign-extend vector extract element
115
116      // Vector duplicate lane (128-bit result only; 64-bit is a shuffle)
117      VDUPLANEQ,    // splat a lane from a 64-bit vector to a 128-bit vector
118
119      // Vector load/store with (de)interleaving
120      VLD2D,
121      VLD3D,
122      VLD4D
123    };
124  }
125
126  /// Define some predicates that are used for node matching.
127  namespace ARM {
128    /// getVMOVImm - If this is a build_vector of constants which can be
129    /// formed by using a VMOV instruction of the specified element size,
130    /// return the constant being splatted.  The ByteSize field indicates the
131    /// number of bytes of each element [1248].
132    SDValue getVMOVImm(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
133
134    /// isVREVMask - Check if a vector shuffle corresponds to a VREV
135    /// instruction with the specified blocksize.  (The order of the elements
136    /// within each block of the vector is reversed.)
137    bool isVREVMask(ShuffleVectorSDNode *N, unsigned blocksize);
138  }
139
140  //===--------------------------------------------------------------------===//
141  //  ARMTargetLowering - ARM Implementation of the TargetLowering interface
142
143  class ARMTargetLowering : public TargetLowering {
144    int VarArgsFrameIndex;            // FrameIndex for start of varargs area.
145  public:
146    explicit ARMTargetLowering(TargetMachine &TM);
147
148    virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
149
150    /// ReplaceNodeResults - Replace the results of node with an illegal result
151    /// type with new values built out of custom code.
152    ///
153    virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
154                                    SelectionDAG &DAG);
155
156    virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
157
158    virtual const char *getTargetNodeName(unsigned Opcode) const;
159
160    virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
161                                                  MachineBasicBlock *MBB) const;
162
163    /// isLegalAddressingMode - Return true if the addressing mode represented
164    /// by AM is legal for this target, for a load/store of the specified type.
165    virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const;
166
167    /// getPreIndexedAddressParts - returns true by value, base pointer and
168    /// offset pointer and addressing mode by reference if the node's address
169    /// can be legally represented as pre-indexed load / store address.
170    virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
171                                           SDValue &Offset,
172                                           ISD::MemIndexedMode &AM,
173                                           SelectionDAG &DAG) const;
174
175    /// getPostIndexedAddressParts - returns true by value, base pointer and
176    /// offset pointer and addressing mode by reference if this node can be
177    /// combined with a load / store to form a post-indexed load / store.
178    virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
179                                            SDValue &Base, SDValue &Offset,
180                                            ISD::MemIndexedMode &AM,
181                                            SelectionDAG &DAG) const;
182
183    virtual void computeMaskedBitsForTargetNode(const SDValue Op,
184                                                const APInt &Mask,
185                                                APInt &KnownZero,
186                                                APInt &KnownOne,
187                                                const SelectionDAG &DAG,
188                                                unsigned Depth) const;
189    ConstraintType getConstraintType(const std::string &Constraint) const;
190    std::pair<unsigned, const TargetRegisterClass*>
191      getRegForInlineAsmConstraint(const std::string &Constraint,
192                                   MVT VT) const;
193    std::vector<unsigned>
194    getRegClassForInlineAsmConstraint(const std::string &Constraint,
195                                      MVT VT) const;
196
197    /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
198    /// vector.  If it is invalid, don't add anything to Ops. If hasMemory is
199    /// true it means one of the asm constraint of the inline asm instruction
200    /// being processed is 'm'.
201    virtual void LowerAsmOperandForConstraint(SDValue Op,
202                                              char ConstraintLetter,
203                                              bool hasMemory,
204                                              std::vector<SDValue> &Ops,
205                                              SelectionDAG &DAG) const;
206
207    virtual const ARMSubtarget* getSubtarget() {
208      return Subtarget;
209    }
210
211    /// getFunctionAlignment - Return the Log2 alignment of this function.
212    virtual unsigned getFunctionAlignment(const Function *F) const;
213
214  private:
215    /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
216    /// make the right decision when generating code for different targets.
217    const ARMSubtarget *Subtarget;
218
219    /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
220    ///
221    unsigned ARMPCLabelIndex;
222
223    void addTypeForNEON(MVT VT, MVT PromotedLdStVT, MVT PromotedBitwiseVT);
224    void addDRTypeForNEON(MVT VT);
225    void addQRTypeForNEON(MVT VT);
226
227    typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector;
228    void PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
229                          SDValue Chain, SDValue &Arg,
230                          RegsToPassVector &RegsToPass,
231                          CCValAssign &VA, CCValAssign &NextVA,
232                          SDValue &StackPtr,
233                          SmallVector<SDValue, 8> &MemOpChains,
234                          ISD::ArgFlagsTy Flags);
235    SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
236                                 SDValue &Root, SelectionDAG &DAG, DebugLoc dl);
237
238    CCAssignFn *CCAssignFnForNode(unsigned CC, bool Return) const;
239    SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
240                             DebugLoc dl, SelectionDAG &DAG,
241                             const CCValAssign &VA,
242                             ISD::ArgFlagsTy Flags);
243    SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG);
244    SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG);
245    SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG);
246    SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG);
247    SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG);
248    SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
249                                            SelectionDAG &DAG);
250    SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
251                                   SelectionDAG &DAG);
252    SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG);
253    SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG);
254    SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG);
255
256    SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
257                                      SDValue Chain,
258                                      SDValue Dst, SDValue Src,
259                                      SDValue Size, unsigned Align,
260                                      bool AlwaysInline,
261                                      const Value *DstSV, uint64_t DstSVOff,
262                                      const Value *SrcSV, uint64_t SrcSVOff);
263    SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
264                            unsigned CallConv, bool isVarArg,
265                            const SmallVectorImpl<ISD::InputArg> &Ins,
266                            DebugLoc dl, SelectionDAG &DAG,
267                            SmallVectorImpl<SDValue> &InVals);
268
269    virtual SDValue
270      LowerFormalArguments(SDValue Chain,
271                           unsigned CallConv, bool isVarArg,
272                           const SmallVectorImpl<ISD::InputArg> &Ins,
273                           DebugLoc dl, SelectionDAG &DAG,
274                           SmallVectorImpl<SDValue> &InVals);
275
276    virtual SDValue
277      LowerCall(SDValue Chain, SDValue Callee,
278                unsigned CallConv, bool isVarArg,
279                bool isTailCall,
280                const SmallVectorImpl<ISD::OutputArg> &Outs,
281                const SmallVectorImpl<ISD::InputArg> &Ins,
282                DebugLoc dl, SelectionDAG &DAG,
283                SmallVectorImpl<SDValue> &InVals);
284
285    virtual SDValue
286      LowerReturn(SDValue Chain,
287                  unsigned CallConv, bool isVarArg,
288                  const SmallVectorImpl<ISD::OutputArg> &Outs,
289                  DebugLoc dl, SelectionDAG &DAG);
290  };
291}
292
293#endif  // ARMISELLOWERING_H
294