ARMISelLowering.h revision 9996663fc6d50128a4897ff3568d311496e9d944
1//===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Evan Cheng and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that ARM uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#ifndef ARMISELLOWERING_H 16#define ARMISELLOWERING_H 17 18#include "llvm/Target/TargetLowering.h" 19#include "llvm/CodeGen/SelectionDAG.h" 20#include <vector> 21 22namespace llvm { 23 class ARMConstantPoolValue; 24 class ARMSubtarget; 25 26 namespace ARMISD { 27 // ARM Specific DAG Nodes 28 enum NodeType { 29 // Start the numbering where the builting ops and target ops leave off. 30 FIRST_NUMBER = ISD::BUILTIN_OP_END+ARM::INSTRUCTION_LIST_END, 31 32 Wrapper, // Wrapper - A wrapper node for TargetConstantPool, 33 // TargetExternalSymbol, and TargetGlobalAddress. 34 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable 35 36 CALL, // Function call. 37 CALL_NOLINK, // Function call with branch not branch-and-link. 38 tCALL, // Thumb function call. 39 BRCOND, // Conditional branch. 40 BR_JT, // Jumptable branch. 41 RET_FLAG, // Return with a flag operand. 42 43 PIC_ADD, // Add with a PC operand and a PIC label. 44 45 CMP, // ARM compare instructions. 46 CMPNZ, // ARM compare that uses only N or Z flags. 47 CMPFP, // ARM VFP compare instruction, sets FPSCR. 48 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR. 49 FMSTAT, // ARM fmstat instruction. 50 CMOV, // ARM conditional move instructions. 51 CNEG, // ARM conditional negate instructions. 52 53 FTOSI, // FP to sint within a FP register. 54 FTOUI, // FP to uint within a FP register. 55 SITOF, // sint to FP within a FP register. 56 UITOF, // uint to FP within a FP register. 57 58 MULHILOU, // Lo,Hi = umul LHS, RHS. 59 MULHILOS, // Lo,Hi = smul LHS, RHS. 60 61 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out. 62 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out. 63 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag. 64 65 FMRRD, // double to two gprs. 66 FMDRR // Two gprs to double. 67 }; 68 } 69 70 //===----------------------------------------------------------------------===// 71 // ARMTargetLowering - ARM Implementation of the TargetLowering interface 72 73 class ARMTargetLowering : public TargetLowering { 74 int VarArgsFrameIndex; // FrameIndex for start of varargs area. 75 public: 76 ARMTargetLowering(TargetMachine &TM); 77 78 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG); 79 virtual const char *getTargetNodeName(unsigned Opcode) const; 80 81 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI, 82 MachineBasicBlock *MBB); 83 84 /// isLegalAddressingMode - Return true if the addressing mode represented 85 /// by AM is legal for this target, for a load/store of the specified type. 86 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const; 87 88 /// isLegalAddressImmediate - Return true if the integer value can be used 89 /// as the offset of the target addressing mode for load / store of the 90 /// given type. 91 virtual bool isLegalAddressImmediate(int64_t V, const Type *Ty) const; 92 93 /// isLegalAddressImmediate - Return true if the GlobalValue can be used as 94 /// the offset of the target addressing mode. 95 virtual bool isLegalAddressImmediate(GlobalValue *GV) const; 96 97 /// isLegalAddressScale - Return true if the integer value can be used as 98 /// the scale of the target addressing mode for load / store of the given 99 /// type. 100 virtual bool isLegalAddressScale(int64_t S, const Type *Ty) const; 101 102 /// isLegalAddressScaleAndImm - Return true if S works for 103 /// IsLegalAddressScale and V works for isLegalAddressImmediate _and_ 104 /// both can be applied simultaneously to the same instruction. 105 virtual bool isLegalAddressScaleAndImm(int64_t S, int64_t V, 106 const Type *Ty) const; 107 108 /// isLegalAddressScaleAndImm - Return true if S works for 109 /// IsLegalAddressScale and GV works for isLegalAddressImmediate _and_ 110 /// both can be applied simultaneously to the same instruction. 111 virtual bool isLegalAddressScaleAndImm(int64_t S, GlobalValue *GV, 112 const Type *Ty) const; 113 114 /// getPreIndexedAddressParts - returns true by value, base pointer and 115 /// offset pointer and addressing mode by reference if the node's address 116 /// can be legally represented as pre-indexed load / store address. 117 virtual bool getPreIndexedAddressParts(SDNode *N, SDOperand &Base, 118 SDOperand &Offset, 119 ISD::MemIndexedMode &AM, 120 SelectionDAG &DAG); 121 122 /// getPostIndexedAddressParts - returns true by value, base pointer and 123 /// offset pointer and addressing mode by reference if this node can be 124 /// combined with a load / store to form a post-indexed load / store. 125 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, 126 SDOperand &Base, SDOperand &Offset, 127 ISD::MemIndexedMode &AM, 128 SelectionDAG &DAG); 129 130 virtual void computeMaskedBitsForTargetNode(const SDOperand Op, 131 uint64_t Mask, 132 uint64_t &KnownZero, 133 uint64_t &KnownOne, 134 unsigned Depth) const; 135 ConstraintType getConstraintType(const std::string &Constraint) const; 136 std::pair<unsigned, const TargetRegisterClass*> 137 getRegForInlineAsmConstraint(const std::string &Constraint, 138 MVT::ValueType VT) const; 139 std::vector<unsigned> 140 getRegClassForInlineAsmConstraint(const std::string &Constraint, 141 MVT::ValueType VT) const; 142 private: 143 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can 144 /// make the right decision when generating code for different targets. 145 const ARMSubtarget *Subtarget; 146 147 /// ARMPCLabelIndex - Keep track the number of ARM PC labels created. 148 /// 149 unsigned ARMPCLabelIndex; 150 151 SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG); 152 SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG); 153 SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG); 154 SDOperand LowerBR_JT(SDOperand Op, SelectionDAG &DAG); 155 }; 156} 157 158#endif // ARMISELLOWERING_H 159