ARMISelLowering.h revision b01fad6d19ac83f9c97eee16af438507383f36d8 
1//===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by Evan Cheng and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that ARM uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef ARMISELLOWERING_H
16#define ARMISELLOWERING_H
17
18#include "llvm/Target/TargetLowering.h"
19#include "llvm/CodeGen/SelectionDAG.h"
20#include <vector>
21
22namespace llvm {
23  class ARMConstantPoolValue;
24  class ARMSubtarget;
25
26  namespace ARMISD {
27    // ARM Specific DAG Nodes
28    enum NodeType {
29      // Start the numbering where the builting ops and target ops leave off.
30      FIRST_NUMBER = ISD::BUILTIN_OP_END+ARM::INSTRUCTION_LIST_END,
31
32      Wrapper,      // Wrapper - A wrapper node for TargetConstantPool,
33                    // TargetExternalSymbol, and TargetGlobalAddress.
34      WrapperJT,    // WrapperJT - A wrapper node for TargetJumpTable
35
36      CALL,         // Function call.
37      CALL_NOLINK,  // Function call with branch not branch-and-link.
38      tCALL,        // Thumb function call.
39      BRCOND,       // Conditional branch.
40      BR_JT,        // Jumptable branch.
41      RET_FLAG,     // Return with a flag operand.
42
43      PIC_ADD,      // Add with a PC operand and a PIC label.
44
45      CMP,          // ARM compare instructions.
46      CMPFP,        // ARM VFP compare instruction, sets FPSCR.
47      CMPFPw0,      // ARM VFP compare against zero instruction, sets FPSCR.
48      FMSTAT,       // ARM fmstat instruction.
49      CMOV,         // ARM conditional move instructions.
50      CNEG,         // ARM conditional negate instructions.
51
52      FTOSI,        // FP to sint within a FP register.
53      FTOUI,        // FP to uint within a FP register.
54      SITOF,        // sint to FP within a FP register.
55      UITOF,        // uint to FP within a FP register.
56
57      MULHILOU,     // Lo,Hi = umul LHS, RHS.
58      MULHILOS,     // Lo,Hi = smul LHS, RHS.
59
60      SRL_FLAG,     // V,Flag = srl_flag X -> srl X, 1 + save carry out.
61      SRA_FLAG,     // V,Flag = sra_flag X -> sra X, 1 + save carry out.
62      RRX,          // V = RRX X, Flag     -> srl X, 1 + shift in carry flag.
63
64      FMRRD,        // double to two gprs.
65      FMDRR         // Two gprs to double.
66    };
67  }
68
69  //===----------------------------------------------------------------------===//
70  //  ARMTargetLowering - X86 Implementation of the TargetLowering interface
71
72  class ARMTargetLowering : public TargetLowering {
73    int VarArgsFrameIndex;            // FrameIndex for start of varargs area.
74  public:
75    ARMTargetLowering(TargetMachine &TM);
76
77    virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
78    virtual const char *getTargetNodeName(unsigned Opcode) const;
79
80    virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
81                                                       MachineBasicBlock *MBB);
82
83    /// isLegalAddressImmediate - Return true if the integer value can be used
84    /// as the offset of the target addressing mode for load / store of the
85    /// given type.
86    virtual bool isLegalAddressImmediate(int64_t V, const Type *Ty) const;
87
88    /// isLegalAddressImmediate - Return true if the GlobalValue can be used as
89    /// the offset of the target addressing mode.
90    virtual bool isLegalAddressImmediate(GlobalValue *GV) const;
91
92    /// isLegalAddressScale - Return true if the integer value can be used as
93    /// the scale of the target addressing mode for load / store of the given
94    /// type.
95    virtual bool isLegalAddressScale(int64_t S, const Type *Ty) const;
96
97    /// getPreIndexedAddressParts - returns true by value, base pointer and
98    /// offset pointer and addressing mode by reference if the node's address
99    /// can be legally represented as pre-indexed load / store address.
100    virtual bool getPreIndexedAddressParts(SDNode *N, SDOperand &Base,
101                                           SDOperand &Offset,
102                                           ISD::MemIndexedMode &AM,
103                                           SelectionDAG &DAG);
104
105    /// getPostIndexedAddressParts - returns true by value, base pointer and
106    /// offset pointer and addressing mode by reference if this node can be
107    /// combined with a load / store to form a post-indexed load / store.
108    virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
109                                            SDOperand &Base, SDOperand &Offset,
110                                            ISD::MemIndexedMode &AM,
111                                            SelectionDAG &DAG);
112
113    virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
114                                                uint64_t Mask,
115                                                uint64_t &KnownZero,
116                                                uint64_t &KnownOne,
117                                                unsigned Depth) const;
118    ConstraintType getConstraintType(char ConstraintLetter) const;
119    std::pair<unsigned, const TargetRegisterClass*>
120      getRegForInlineAsmConstraint(const std::string &Constraint,
121                                   MVT::ValueType VT) const;
122    std::vector<unsigned>
123    getRegClassForInlineAsmConstraint(const std::string &Constraint,
124                                      MVT::ValueType VT) const;
125  private:
126    /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
127    /// make the right decision when generating code for different targets.
128    const ARMSubtarget *Subtarget;
129
130    /// ARMPCLabelIndex - Keep track the number of ARM PC labels created.
131    ///
132    unsigned ARMPCLabelIndex;
133
134    SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG);
135    SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG);
136    SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG);
137    SDOperand LowerBR_JT(SDOperand Op, SelectionDAG &DAG);
138  };
139}
140
141#endif  // ARMISELLOWERING_H
142