ARMISelLowering.h revision e50ed30282bb5b4a9ed952580523f2dda16215ac 
1//===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that ARM uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef ARMISELLOWERING_H
16#define ARMISELLOWERING_H
17
18#include "ARMSubtarget.h"
19#include "llvm/Target/TargetLowering.h"
20#include "llvm/CodeGen/SelectionDAG.h"
21#include "llvm/CodeGen/CallingConvLower.h"
22#include <vector>
23
24namespace llvm {
25  class ARMConstantPoolValue;
26
27  namespace ARMISD {
28    // ARM Specific DAG Nodes
29    enum NodeType {
30      // Start the numbering where the builtin ops and target ops leave off.
31      FIRST_NUMBER = ISD::BUILTIN_OP_END,
32
33      Wrapper,      // Wrapper - A wrapper node for TargetConstantPool,
34                    // TargetExternalSymbol, and TargetGlobalAddress.
35      WrapperJT,    // WrapperJT - A wrapper node for TargetJumpTable
36
37      CALL,         // Function call.
38      CALL_PRED,    // Function call that's predicable.
39      CALL_NOLINK,  // Function call with branch not branch-and-link.
40      tCALL,        // Thumb function call.
41      BRCOND,       // Conditional branch.
42      BR_JT,        // Jumptable branch.
43      BR2_JT,       // Jumptable branch (2 level - jumptable entry is a jump).
44      RET_FLAG,     // Return with a flag operand.
45
46      PIC_ADD,      // Add with a PC operand and a PIC label.
47
48      CMP,          // ARM compare instructions.
49      CMPZ,         // ARM compare that sets only Z flag.
50      CMPFP,        // ARM VFP compare instruction, sets FPSCR.
51      CMPFPw0,      // ARM VFP compare against zero instruction, sets FPSCR.
52      FMSTAT,       // ARM fmstat instruction.
53      CMOV,         // ARM conditional move instructions.
54      CNEG,         // ARM conditional negate instructions.
55
56      FTOSI,        // FP to sint within a FP register.
57      FTOUI,        // FP to uint within a FP register.
58      SITOF,        // sint to FP within a FP register.
59      UITOF,        // uint to FP within a FP register.
60
61      SRL_FLAG,     // V,Flag = srl_flag X -> srl X, 1 + save carry out.
62      SRA_FLAG,     // V,Flag = sra_flag X -> sra X, 1 + save carry out.
63      RRX,          // V = RRX X, Flag     -> srl X, 1 + shift in carry flag.
64
65      FMRRD,        // double to two gprs.
66      FMDRR,        // Two gprs to double.
67
68      EH_SJLJ_SETJMP,    // SjLj exception handling setjmp.
69      EH_SJLJ_LONGJMP,   // SjLj exception handling longjmp.
70
71      THREAD_POINTER,
72
73      DYN_ALLOC,    // Dynamic allocation on the stack.
74
75      VCEQ,         // Vector compare equal.
76      VCGE,         // Vector compare greater than or equal.
77      VCGEU,        // Vector compare unsigned greater than or equal.
78      VCGT,         // Vector compare greater than.
79      VCGTU,        // Vector compare unsigned greater than.
80      VTST,         // Vector test bits.
81
82      // Vector shift by immediate:
83      VSHL,         // ...left
84      VSHRs,        // ...right (signed)
85      VSHRu,        // ...right (unsigned)
86      VSHLLs,       // ...left long (signed)
87      VSHLLu,       // ...left long (unsigned)
88      VSHLLi,       // ...left long (with maximum shift count)
89      VSHRN,        // ...right narrow
90
91      // Vector rounding shift by immediate:
92      VRSHRs,       // ...right (signed)
93      VRSHRu,       // ...right (unsigned)
94      VRSHRN,       // ...right narrow
95
96      // Vector saturating shift by immediate:
97      VQSHLs,       // ...left (signed)
98      VQSHLu,       // ...left (unsigned)
99      VQSHLsu,      // ...left (signed to unsigned)
100      VQSHRNs,      // ...right narrow (signed)
101      VQSHRNu,      // ...right narrow (unsigned)
102      VQSHRNsu,     // ...right narrow (signed to unsigned)
103
104      // Vector saturating rounding shift by immediate:
105      VQRSHRNs,     // ...right narrow (signed)
106      VQRSHRNu,     // ...right narrow (unsigned)
107      VQRSHRNsu,    // ...right narrow (signed to unsigned)
108
109      // Vector shift and insert:
110      VSLI,         // ...left
111      VSRI,         // ...right
112
113      // Vector get lane (VMOV scalar to ARM core register)
114      // (These are used for 8- and 16-bit element types only.)
115      VGETLANEu,    // zero-extend vector extract element
116      VGETLANEs,    // sign-extend vector extract element
117
118      // Vector duplicate lane (128-bit result only; 64-bit is a shuffle)
119      VDUPLANEQ,    // splat a lane from a 64-bit vector to a 128-bit vector
120
121      // Vector load/store with (de)interleaving
122      VLD2D,
123      VLD3D,
124      VLD4D,
125      VST2D,
126      VST3D,
127      VST4D
128    };
129  }
130
131  /// Define some predicates that are used for node matching.
132  namespace ARM {
133    /// getVMOVImm - If this is a build_vector of constants which can be
134    /// formed by using a VMOV instruction of the specified element size,
135    /// return the constant being splatted.  The ByteSize field indicates the
136    /// number of bytes of each element [1248].
137    SDValue getVMOVImm(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
138
139    /// isVREVMask - Check if a vector shuffle corresponds to a VREV
140    /// instruction with the specified blocksize.  (The order of the elements
141    /// within each block of the vector is reversed.)
142    bool isVREVMask(ShuffleVectorSDNode *N, unsigned blocksize);
143  }
144
145  //===--------------------------------------------------------------------===//
146  //  ARMTargetLowering - ARM Implementation of the TargetLowering interface
147
148  class ARMTargetLowering : public TargetLowering {
149    int VarArgsFrameIndex;            // FrameIndex for start of varargs area.
150  public:
151    explicit ARMTargetLowering(TargetMachine &TM);
152
153    virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
154
155    /// ReplaceNodeResults - Replace the results of node with an illegal result
156    /// type with new values built out of custom code.
157    ///
158    virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
159                                    SelectionDAG &DAG);
160
161    virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
162
163    virtual const char *getTargetNodeName(unsigned Opcode) const;
164
165    virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
166                                                  MachineBasicBlock *MBB) const;
167
168    /// isLegalAddressingMode - Return true if the addressing mode represented
169    /// by AM is legal for this target, for a load/store of the specified type.
170    virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const;
171
172    /// getPreIndexedAddressParts - returns true by value, base pointer and
173    /// offset pointer and addressing mode by reference if the node's address
174    /// can be legally represented as pre-indexed load / store address.
175    virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
176                                           SDValue &Offset,
177                                           ISD::MemIndexedMode &AM,
178                                           SelectionDAG &DAG) const;
179
180    /// getPostIndexedAddressParts - returns true by value, base pointer and
181    /// offset pointer and addressing mode by reference if this node can be
182    /// combined with a load / store to form a post-indexed load / store.
183    virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
184                                            SDValue &Base, SDValue &Offset,
185                                            ISD::MemIndexedMode &AM,
186                                            SelectionDAG &DAG) const;
187
188    virtual void computeMaskedBitsForTargetNode(const SDValue Op,
189                                                const APInt &Mask,
190                                                APInt &KnownZero,
191                                                APInt &KnownOne,
192                                                const SelectionDAG &DAG,
193                                                unsigned Depth) const;
194    ConstraintType getConstraintType(const std::string &Constraint) const;
195    std::pair<unsigned, const TargetRegisterClass*>
196      getRegForInlineAsmConstraint(const std::string &Constraint,
197                                   EVT VT) const;
198    std::vector<unsigned>
199    getRegClassForInlineAsmConstraint(const std::string &Constraint,
200                                      EVT VT) const;
201
202    /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
203    /// vector.  If it is invalid, don't add anything to Ops. If hasMemory is
204    /// true it means one of the asm constraint of the inline asm instruction
205    /// being processed is 'm'.
206    virtual void LowerAsmOperandForConstraint(SDValue Op,
207                                              char ConstraintLetter,
208                                              bool hasMemory,
209                                              std::vector<SDValue> &Ops,
210                                              SelectionDAG &DAG) const;
211
212    virtual const ARMSubtarget* getSubtarget() {
213      return Subtarget;
214    }
215
216    /// getFunctionAlignment - Return the Log2 alignment of this function.
217    virtual unsigned getFunctionAlignment(const Function *F) const;
218
219  private:
220    /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
221    /// make the right decision when generating code for different targets.
222    const ARMSubtarget *Subtarget;
223
224    /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
225    ///
226    unsigned ARMPCLabelIndex;
227
228    void addTypeForNEON(EVT VT, EVT PromotedLdStVT, EVT PromotedBitwiseVT);
229    void addDRTypeForNEON(EVT VT);
230    void addQRTypeForNEON(EVT VT);
231
232    typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector;
233    void PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
234                          SDValue Chain, SDValue &Arg,
235                          RegsToPassVector &RegsToPass,
236                          CCValAssign &VA, CCValAssign &NextVA,
237                          SDValue &StackPtr,
238                          SmallVector<SDValue, 8> &MemOpChains,
239                          ISD::ArgFlagsTy Flags);
240    SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
241                                 SDValue &Root, SelectionDAG &DAG, DebugLoc dl);
242
243    CCAssignFn *CCAssignFnForNode(unsigned CC, bool Return, bool isVarArg) const;
244    SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
245                             DebugLoc dl, SelectionDAG &DAG,
246                             const CCValAssign &VA,
247                             ISD::ArgFlagsTy Flags);
248    SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG);
249    SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG);
250    SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG);
251    SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG);
252    SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG);
253    SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
254                                            SelectionDAG &DAG);
255    SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
256                                   SelectionDAG &DAG);
257    SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG);
258    SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG);
259    SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG);
260    SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG);
261
262    SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
263                                      SDValue Chain,
264                                      SDValue Dst, SDValue Src,
265                                      SDValue Size, unsigned Align,
266                                      bool AlwaysInline,
267                                      const Value *DstSV, uint64_t DstSVOff,
268                                      const Value *SrcSV, uint64_t SrcSVOff);
269    SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
270                            unsigned CallConv, bool isVarArg,
271                            const SmallVectorImpl<ISD::InputArg> &Ins,
272                            DebugLoc dl, SelectionDAG &DAG,
273                            SmallVectorImpl<SDValue> &InVals);
274
275    virtual SDValue
276      LowerFormalArguments(SDValue Chain,
277                           unsigned CallConv, bool isVarArg,
278                           const SmallVectorImpl<ISD::InputArg> &Ins,
279                           DebugLoc dl, SelectionDAG &DAG,
280                           SmallVectorImpl<SDValue> &InVals);
281
282    virtual SDValue
283      LowerCall(SDValue Chain, SDValue Callee,
284                unsigned CallConv, bool isVarArg,
285                bool isTailCall,
286                const SmallVectorImpl<ISD::OutputArg> &Outs,
287                const SmallVectorImpl<ISD::InputArg> &Ins,
288                DebugLoc dl, SelectionDAG &DAG,
289                SmallVectorImpl<SDValue> &InVals);
290
291    virtual SDValue
292      LowerReturn(SDValue Chain,
293                  unsigned CallConv, bool isVarArg,
294                  const SmallVectorImpl<ISD::OutputArg> &Outs,
295                  DebugLoc dl, SelectionDAG &DAG);
296  };
297}
298
299#endif  // ARMISELLOWERING_H
300