ARMISelLowering.h revision f1ba1cad387dc52f3c2c5afc665edf9caad00992 
1//===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by Evan Cheng and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that ARM uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef ARMISELLOWERING_H
16#define ARMISELLOWERING_H
17
18#include "ARMSubtarget.h"
19#include "llvm/Target/TargetLowering.h"
20#include "llvm/CodeGen/SelectionDAG.h"
21#include <vector>
22
23namespace llvm {
24  class ARMConstantPoolValue;
25
26  namespace ARMISD {
27    // ARM Specific DAG Nodes
28    enum NodeType {
29      // Start the numbering where the builting ops and target ops leave off.
30      FIRST_NUMBER = ISD::BUILTIN_OP_END+ARM::INSTRUCTION_LIST_END,
31
32      Wrapper,      // Wrapper - A wrapper node for TargetConstantPool,
33                    // TargetExternalSymbol, and TargetGlobalAddress.
34      WrapperJT,    // WrapperJT - A wrapper node for TargetJumpTable
35
36      CALL,         // Function call.
37      CALL_PRED,    // Function call that's predicable.
38      CALL_NOLINK,  // Function call with branch not branch-and-link.
39      tCALL,        // Thumb function call.
40      BRCOND,       // Conditional branch.
41      BR_JT,        // Jumptable branch.
42      RET_FLAG,     // Return with a flag operand.
43
44      PIC_ADD,      // Add with a PC operand and a PIC label.
45
46      CMP,          // ARM compare instructions.
47      CMPNZ,        // ARM compare that uses only N or Z flags.
48      CMPFP,        // ARM VFP compare instruction, sets FPSCR.
49      CMPFPw0,      // ARM VFP compare against zero instruction, sets FPSCR.
50      FMSTAT,       // ARM fmstat instruction.
51      CMOV,         // ARM conditional move instructions.
52      CNEG,         // ARM conditional negate instructions.
53
54      FTOSI,        // FP to sint within a FP register.
55      FTOUI,        // FP to uint within a FP register.
56      SITOF,        // sint to FP within a FP register.
57      UITOF,        // uint to FP within a FP register.
58
59      SRL_FLAG,     // V,Flag = srl_flag X -> srl X, 1 + save carry out.
60      SRA_FLAG,     // V,Flag = sra_flag X -> sra X, 1 + save carry out.
61      RRX,          // V = RRX X, Flag     -> srl X, 1 + shift in carry flag.
62
63      FMRRD,        // double to two gprs.
64      FMDRR,         // Two gprs to double.
65
66      THREAD_POINTER
67    };
68  }
69
70  //===----------------------------------------------------------------------===//
71  //  ARMTargetLowering - ARM Implementation of the TargetLowering interface
72
73  class ARMTargetLowering : public TargetLowering {
74    int VarArgsFrameIndex;            // FrameIndex for start of varargs area.
75  public:
76    explicit ARMTargetLowering(TargetMachine &TM);
77
78    virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
79    virtual const char *getTargetNodeName(unsigned Opcode) const;
80
81    virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
82                                                       MachineBasicBlock *MBB);
83
84    /// isLegalAddressingMode - Return true if the addressing mode represented
85    /// by AM is legal for this target, for a load/store of the specified type.
86    virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const;
87
88    /// getPreIndexedAddressParts - returns true by value, base pointer and
89    /// offset pointer and addressing mode by reference if the node's address
90    /// can be legally represented as pre-indexed load / store address.
91    virtual bool getPreIndexedAddressParts(SDNode *N, SDOperand &Base,
92                                           SDOperand &Offset,
93                                           ISD::MemIndexedMode &AM,
94                                           SelectionDAG &DAG);
95
96    /// getPostIndexedAddressParts - returns true by value, base pointer and
97    /// offset pointer and addressing mode by reference if this node can be
98    /// combined with a load / store to form a post-indexed load / store.
99    virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
100                                            SDOperand &Base, SDOperand &Offset,
101                                            ISD::MemIndexedMode &AM,
102                                            SelectionDAG &DAG);
103
104    virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
105                                                uint64_t Mask,
106                                                uint64_t &KnownZero,
107                                                uint64_t &KnownOne,
108                                                const SelectionDAG &DAG,
109                                                unsigned Depth) const;
110    ConstraintType getConstraintType(const std::string &Constraint) const;
111    std::pair<unsigned, const TargetRegisterClass*>
112      getRegForInlineAsmConstraint(const std::string &Constraint,
113                                   MVT::ValueType VT) const;
114    std::vector<unsigned>
115    getRegClassForInlineAsmConstraint(const std::string &Constraint,
116                                      MVT::ValueType VT) const;
117
118    virtual const TargetSubtarget* getSubtarget() {
119      return static_cast<const TargetSubtarget*>(Subtarget);
120    }
121
122  private:
123    /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
124    /// make the right decision when generating code for different targets.
125    const ARMSubtarget *Subtarget;
126
127    /// ARMPCLabelIndex - Keep track the number of ARM PC labels created.
128    ///
129    unsigned ARMPCLabelIndex;
130
131    SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG);
132    SDOperand LowerGlobalAddressDarwin(SDOperand Op, SelectionDAG &DAG);
133    SDOperand LowerGlobalAddressELF(SDOperand Op, SelectionDAG &DAG);
134    SDOperand LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG);
135    SDOperand LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
136                                            SelectionDAG &DAG);
137    SDOperand LowerToTLSExecModels(GlobalAddressSDNode *GA,
138                                   SelectionDAG &DAG);
139    SDOperand LowerGLOBAL_OFFSET_TABLE(SDOperand Op, SelectionDAG &DAG);
140    SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG);
141    SDOperand LowerBR_JT(SDOperand Op, SelectionDAG &DAG);
142    SDOperand LowerMEMCPYInline(SDOperand Chain, SDOperand Dest,
143                                SDOperand Source, unsigned Size,
144                                unsigned Align, SelectionDAG &DAG);
145
146
147  };
148}
149
150#endif  // ARMISELLOWERING_H
151