HexagonBaseInfo.h revision 6948897e478cbd66626159776a8017b3c18579b9 
1//===-- HexagonBaseInfo.h - Top level definitions for Hexagon --*- C++ -*--===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains small standalone helper functions and enum definitions for
11// the Hexagon target useful for the compiler back-end and the MC libraries.
12// As such, it deliberately does not include references to LLVM core
13// code gen types, passes, etc..
14//
15//===----------------------------------------------------------------------===//
16
17#ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONBASEINFO_H
18#define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONBASEINFO_H
19
20#include "HexagonMCTargetDesc.h"
21#include "llvm/Support/ErrorHandling.h"
22#include <stdint.h>
23
24namespace llvm {
25
26/// HexagonII - This namespace holds all of the target specific flags that
27/// instruction info tracks.
28///
29namespace HexagonII {
30  // *** The code below must match HexagonInstrFormat*.td *** //
31
32  // Insn types.
33  // *** Must match HexagonInstrFormat*.td ***
34  enum Type {
35    TypePSEUDO  = 0,
36    TypeALU32   = 1,
37    TypeCR      = 2,
38    TypeJR      = 3,
39    TypeJ       = 4,
40    TypeLD      = 5,
41    TypeST      = 6,
42    TypeSYSTEM  = 7,
43    TypeXTYPE   = 8,
44    TypeMEMOP   = 9,
45    TypeNV      = 10,
46    TypeDUPLEX  = 11,
47    TypePREFIX  = 30, // Such as extenders.
48    TypeENDLOOP = 31  // Such as end of a HW loop.
49  };
50
51  enum SubTarget {
52    HasV2SubT     = 0xf,
53    HasV2SubTOnly = 0x1,
54    NoV2SubT      = 0x0,
55    HasV3SubT     = 0xe,
56    HasV3SubTOnly = 0x2,
57    NoV3SubT      = 0x1,
58    HasV4SubT     = 0xc,
59    NoV4SubT      = 0x3,
60    HasV5SubT     = 0x8,
61    NoV5SubT      = 0x7
62  };
63
64  enum AddrMode {
65    NoAddrMode     = 0,  // No addressing mode
66    Absolute       = 1,  // Absolute addressing mode
67    AbsoluteSet    = 2,  // Absolute set addressing mode
68    BaseImmOffset  = 3,  // Indirect with offset
69    BaseLongOffset = 4,  // Indirect with long offset
70    BaseRegOffset  = 5,  // Indirect with register offset
71    PostInc        = 6   // Post increment addressing mode
72  };
73
74  enum class MemAccessSize {
75    NoMemAccess = 0,            // Not a memory acces instruction.
76    ByteAccess = 1,             // Byte access instruction (memb).
77    HalfWordAccess = 2,         // Half word access instruction (memh).
78    WordAccess = 3,             // Word access instruction (memw).
79    DoubleWordAccess = 4        // Double word access instruction (memd)
80  };
81
82  // MCInstrDesc TSFlags
83  // *** Must match HexagonInstrFormat*.td ***
84  enum {
85    // This 5-bit field describes the insn type.
86    TypePos  = 0,
87    TypeMask = 0x1f,
88
89    // Solo instructions.
90    SoloPos  = 5,
91    SoloMask = 0x1,
92    // Packed only with A or X-type instructions.
93    SoloAXPos  = 6,
94    SoloAXMask = 0x1,
95    // Only A-type instruction in first slot or nothing.
96    SoloAin1Pos  = 7,
97    SoloAin1Mask = 0x1,
98
99    // Predicated instructions.
100    PredicatedPos  = 8,
101    PredicatedMask = 0x1,
102    PredicatedFalsePos  = 9,
103    PredicatedFalseMask = 0x1,
104    PredicatedNewPos  = 10,
105    PredicatedNewMask = 0x1,
106    PredicateLatePos  = 11,
107    PredicateLateMask = 0x1,
108
109    // New-Value consumer instructions.
110    NewValuePos  = 12,
111    NewValueMask = 0x1,
112    // New-Value producer instructions.
113    hasNewValuePos  = 13,
114    hasNewValueMask = 0x1,
115    // Which operand consumes or produces a new value.
116    NewValueOpPos  = 14,
117    NewValueOpMask = 0x7,
118    // Stores that can become new-value stores.
119    mayNVStorePos  = 17,
120    mayNVStoreMask = 0x1,
121    // New-value store instructions.
122    NVStorePos  = 18,
123    NVStoreMask = 0x1,
124    // Loads that can become current-value loads.
125    mayCVLoadPos  = 19,
126    mayCVLoadMask = 0x1,
127    // Current-value load instructions.
128    CVLoadPos  = 20,
129    CVLoadMask = 0x1,
130
131    // Extendable insns.
132    ExtendablePos  = 21,
133    ExtendableMask = 0x1,
134    // Insns must be extended.
135    ExtendedPos  = 22,
136    ExtendedMask = 0x1,
137    // Which operand may be extended.
138    ExtendableOpPos  = 23,
139    ExtendableOpMask = 0x7,
140    // Signed or unsigned range.
141    ExtentSignedPos  = 26,
142    ExtentSignedMask = 0x1,
143    // Number of bits of range before extending operand.
144    ExtentBitsPos  = 27,
145    ExtentBitsMask = 0x1f,
146    // Alignment power-of-two before extending operand.
147    ExtentAlignPos  = 32,
148    ExtentAlignMask = 0x3,
149
150    // Valid subtargets
151    validSubTargetPos  = 34,
152    validSubTargetMask = 0xf,
153
154    // Addressing mode for load/store instructions.
155    AddrModePos  = 40,
156    AddrModeMask = 0x7,
157    // Access size for load/store instructions.
158    MemAccessSizePos = 43,
159    MemAccesSizeMask = 0x7,
160
161    // Branch predicted taken.
162    TakenPos = 47,
163    TakenMask = 0x1,
164
165    // Floating-point instructions.
166    FPPos  = 48,
167    FPMask = 0x1
168  };
169
170  // *** The code above must match HexagonInstrFormat*.td *** //
171
172  // Hexagon specific MO operand flag mask.
173  enum HexagonMOTargetFlagVal {
174    //===------------------------------------------------------------------===//
175    // Hexagon Specific MachineOperand flags.
176    MO_NO_FLAG,
177
178    HMOTF_ConstExtended = 1,
179
180    /// MO_PCREL - On a symbol operand, indicates a PC-relative relocation
181    /// Used for computing a global address for PIC compilations
182    MO_PCREL,
183
184    /// MO_GOT - Indicates a GOT-relative relocation
185    MO_GOT,
186
187    // Low or high part of a symbol.
188    MO_LO16, MO_HI16,
189
190    // Offset from the base of the SDA.
191    MO_GPREL
192  };
193
194  // Hexagon Sub-instruction classes.
195  enum SubInstructionGroup {
196    HSIG_None = 0,
197    HSIG_L1,
198    HSIG_L2,
199    HSIG_S1,
200    HSIG_S2,
201    HSIG_A,
202    HSIG_Compound
203  };
204
205  // Hexagon Compound classes.
206  enum CompoundGroup {
207    HCG_None = 0,
208    HCG_A,
209    HCG_B,
210    HCG_C
211  };
212
213  enum InstParseBits {
214    INST_PARSE_MASK       = 0x0000c000,
215    INST_PARSE_PACKET_END = 0x0000c000,
216    INST_PARSE_LOOP_END   = 0x00008000,
217    INST_PARSE_NOT_END    = 0x00004000,
218    INST_PARSE_DUPLEX     = 0x00000000,
219    INST_PARSE_EXTENDER   = 0x00000000
220  };
221
222} // End namespace HexagonII.
223
224} // End namespace llvm.
225
226#endif
227