MipsSEISelDAGToDAG.cpp revision 36b56886974eae4f9c5ebc96befd3e7bfe5de338
1//===-- MipsSEISelDAGToDAG.cpp - A Dag to Dag Inst Selector for MipsSE ----===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// Subclass of MipsDAGToDAGISel specialized for mips32/64. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "mips-isel" 15#include "MipsSEISelDAGToDAG.h" 16#include "MCTargetDesc/MipsBaseInfo.h" 17#include "Mips.h" 18#include "MipsAnalyzeImmediate.h" 19#include "MipsMachineFunction.h" 20#include "MipsRegisterInfo.h" 21#include "llvm/CodeGen/MachineConstantPool.h" 22#include "llvm/CodeGen/MachineFrameInfo.h" 23#include "llvm/CodeGen/MachineFunction.h" 24#include "llvm/CodeGen/MachineInstrBuilder.h" 25#include "llvm/CodeGen/MachineRegisterInfo.h" 26#include "llvm/CodeGen/SelectionDAGNodes.h" 27#include "llvm/IR/CFG.h" 28#include "llvm/IR/GlobalValue.h" 29#include "llvm/IR/Instructions.h" 30#include "llvm/IR/Intrinsics.h" 31#include "llvm/IR/Type.h" 32#include "llvm/Support/Debug.h" 33#include "llvm/Support/ErrorHandling.h" 34#include "llvm/Support/raw_ostream.h" 35#include "llvm/Target/TargetMachine.h" 36using namespace llvm; 37 38bool MipsSEDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) { 39 if (Subtarget.inMips16Mode()) 40 return false; 41 return MipsDAGToDAGISel::runOnMachineFunction(MF); 42} 43 44void MipsSEDAGToDAGISel::addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI, 45 MachineFunction &MF) { 46 MachineInstrBuilder MIB(MF, &MI); 47 unsigned Mask = MI.getOperand(1).getImm(); 48 unsigned Flag = IsDef ? RegState::ImplicitDefine : RegState::Implicit; 49 50 if (Mask & 1) 51 MIB.addReg(Mips::DSPPos, Flag); 52 53 if (Mask & 2) 54 MIB.addReg(Mips::DSPSCount, Flag); 55 56 if (Mask & 4) 57 MIB.addReg(Mips::DSPCarry, Flag); 58 59 if (Mask & 8) 60 MIB.addReg(Mips::DSPOutFlag, Flag); 61 62 if (Mask & 16) 63 MIB.addReg(Mips::DSPCCond, Flag); 64 65 if (Mask & 32) 66 MIB.addReg(Mips::DSPEFI, Flag); 67} 68 69unsigned MipsSEDAGToDAGISel::getMSACtrlReg(const SDValue RegIdx) const { 70 switch (cast<ConstantSDNode>(RegIdx)->getZExtValue()) { 71 default: 72 llvm_unreachable("Could not map int to register"); 73 case 0: return Mips::MSAIR; 74 case 1: return Mips::MSACSR; 75 case 2: return Mips::MSAAccess; 76 case 3: return Mips::MSASave; 77 case 4: return Mips::MSAModify; 78 case 5: return Mips::MSARequest; 79 case 6: return Mips::MSAMap; 80 case 7: return Mips::MSAUnmap; 81 } 82} 83 84bool MipsSEDAGToDAGISel::replaceUsesWithZeroReg(MachineRegisterInfo *MRI, 85 const MachineInstr& MI) { 86 unsigned DstReg = 0, ZeroReg = 0; 87 88 // Check if MI is "addiu $dst, $zero, 0" or "daddiu $dst, $zero, 0". 89 if ((MI.getOpcode() == Mips::ADDiu) && 90 (MI.getOperand(1).getReg() == Mips::ZERO) && 91 (MI.getOperand(2).getImm() == 0)) { 92 DstReg = MI.getOperand(0).getReg(); 93 ZeroReg = Mips::ZERO; 94 } else if ((MI.getOpcode() == Mips::DADDiu) && 95 (MI.getOperand(1).getReg() == Mips::ZERO_64) && 96 (MI.getOperand(2).getImm() == 0)) { 97 DstReg = MI.getOperand(0).getReg(); 98 ZeroReg = Mips::ZERO_64; 99 } 100 101 if (!DstReg) 102 return false; 103 104 // Replace uses with ZeroReg. 105 for (MachineRegisterInfo::use_iterator U = MRI->use_begin(DstReg), 106 E = MRI->use_end(); U != E;) { 107 MachineOperand &MO = *U; 108 unsigned OpNo = U.getOperandNo(); 109 MachineInstr *MI = MO.getParent(); 110 ++U; 111 112 // Do not replace if it is a phi's operand or is tied to def operand. 113 if (MI->isPHI() || MI->isRegTiedToDefOperand(OpNo) || MI->isPseudo()) 114 continue; 115 116 MO.setReg(ZeroReg); 117 } 118 119 return true; 120} 121 122void MipsSEDAGToDAGISel::initGlobalBaseReg(MachineFunction &MF) { 123 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 124 125 if (!MipsFI->globalBaseRegSet()) 126 return; 127 128 MachineBasicBlock &MBB = MF.front(); 129 MachineBasicBlock::iterator I = MBB.begin(); 130 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 131 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); 132 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc(); 133 unsigned V0, V1, GlobalBaseReg = MipsFI->getGlobalBaseReg(); 134 const TargetRegisterClass *RC; 135 136 if (Subtarget.isABI_N64()) 137 RC = (const TargetRegisterClass*)&Mips::GPR64RegClass; 138 else 139 RC = (const TargetRegisterClass*)&Mips::GPR32RegClass; 140 141 V0 = RegInfo.createVirtualRegister(RC); 142 V1 = RegInfo.createVirtualRegister(RC); 143 144 if (Subtarget.isABI_N64()) { 145 MF.getRegInfo().addLiveIn(Mips::T9_64); 146 MBB.addLiveIn(Mips::T9_64); 147 148 // lui $v0, %hi(%neg(%gp_rel(fname))) 149 // daddu $v1, $v0, $t9 150 // daddiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname))) 151 const GlobalValue *FName = MF.getFunction(); 152 BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0) 153 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI); 154 BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0) 155 .addReg(Mips::T9_64); 156 BuildMI(MBB, I, DL, TII.get(Mips::DADDiu), GlobalBaseReg).addReg(V1) 157 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO); 158 return; 159 } 160 161 if (MF.getTarget().getRelocationModel() == Reloc::Static) { 162 // Set global register to __gnu_local_gp. 163 // 164 // lui $v0, %hi(__gnu_local_gp) 165 // addiu $globalbasereg, $v0, %lo(__gnu_local_gp) 166 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0) 167 .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_HI); 168 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0) 169 .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_LO); 170 return; 171 } 172 173 MF.getRegInfo().addLiveIn(Mips::T9); 174 MBB.addLiveIn(Mips::T9); 175 176 if (Subtarget.isABI_N32()) { 177 // lui $v0, %hi(%neg(%gp_rel(fname))) 178 // addu $v1, $v0, $t9 179 // addiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname))) 180 const GlobalValue *FName = MF.getFunction(); 181 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0) 182 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI); 183 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9); 184 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1) 185 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO); 186 return; 187 } 188 189 assert(Subtarget.isABI_O32()); 190 191 // For O32 ABI, the following instruction sequence is emitted to initialize 192 // the global base register: 193 // 194 // 0. lui $2, %hi(_gp_disp) 195 // 1. addiu $2, $2, %lo(_gp_disp) 196 // 2. addu $globalbasereg, $2, $t9 197 // 198 // We emit only the last instruction here. 199 // 200 // GNU linker requires that the first two instructions appear at the beginning 201 // of a function and no instructions be inserted before or between them. 202 // The two instructions are emitted during lowering to MC layer in order to 203 // avoid any reordering. 204 // 205 // Register $2 (Mips::V0) is added to the list of live-in registers to ensure 206 // the value instruction 1 (addiu) defines is valid when instruction 2 (addu) 207 // reads it. 208 MF.getRegInfo().addLiveIn(Mips::V0); 209 MBB.addLiveIn(Mips::V0); 210 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), GlobalBaseReg) 211 .addReg(Mips::V0).addReg(Mips::T9); 212} 213 214void MipsSEDAGToDAGISel::processFunctionAfterISel(MachineFunction &MF) { 215 initGlobalBaseReg(MF); 216 217 MachineRegisterInfo *MRI = &MF.getRegInfo(); 218 219 for (MachineFunction::iterator MFI = MF.begin(), MFE = MF.end(); MFI != MFE; 220 ++MFI) 221 for (MachineBasicBlock::iterator I = MFI->begin(); I != MFI->end(); ++I) { 222 if (I->getOpcode() == Mips::RDDSP) 223 addDSPCtrlRegOperands(false, *I, MF); 224 else if (I->getOpcode() == Mips::WRDSP) 225 addDSPCtrlRegOperands(true, *I, MF); 226 else 227 replaceUsesWithZeroReg(MRI, *I); 228 } 229} 230 231SDNode *MipsSEDAGToDAGISel::selectAddESubE(unsigned MOp, SDValue InFlag, 232 SDValue CmpLHS, SDLoc DL, 233 SDNode *Node) const { 234 unsigned Opc = InFlag.getOpcode(); (void)Opc; 235 236 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) || 237 (Opc == ISD::SUBC || Opc == ISD::SUBE)) && 238 "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn"); 239 240 SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) }; 241 SDValue LHS = Node->getOperand(0), RHS = Node->getOperand(1); 242 EVT VT = LHS.getValueType(); 243 244 SDNode *Carry = CurDAG->getMachineNode(Mips::SLTu, DL, VT, Ops); 245 SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, DL, VT, 246 SDValue(Carry, 0), RHS); 247 return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue, LHS, 248 SDValue(AddCarry, 0)); 249} 250 251/// Match frameindex 252bool MipsSEDAGToDAGISel::selectAddrFrameIndex(SDValue Addr, SDValue &Base, 253 SDValue &Offset) const { 254 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) { 255 EVT ValTy = Addr.getValueType(); 256 257 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy); 258 Offset = CurDAG->getTargetConstant(0, ValTy); 259 return true; 260 } 261 return false; 262} 263 264/// Match frameindex+offset and frameindex|offset 265bool MipsSEDAGToDAGISel::selectAddrFrameIndexOffset(SDValue Addr, SDValue &Base, 266 SDValue &Offset, 267 unsigned OffsetBits) const { 268 if (CurDAG->isBaseWithConstantOffset(Addr)) { 269 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)); 270 if (isIntN(OffsetBits, CN->getSExtValue())) { 271 EVT ValTy = Addr.getValueType(); 272 273 // If the first operand is a FI, get the TargetFI Node 274 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode> 275 (Addr.getOperand(0))) 276 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy); 277 else 278 Base = Addr.getOperand(0); 279 280 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), ValTy); 281 return true; 282 } 283 } 284 return false; 285} 286 287/// ComplexPattern used on MipsInstrInfo 288/// Used on Mips Load/Store instructions 289bool MipsSEDAGToDAGISel::selectAddrRegImm(SDValue Addr, SDValue &Base, 290 SDValue &Offset) const { 291 // if Address is FI, get the TargetFrameIndex. 292 if (selectAddrFrameIndex(Addr, Base, Offset)) 293 return true; 294 295 // on PIC code Load GA 296 if (Addr.getOpcode() == MipsISD::Wrapper) { 297 Base = Addr.getOperand(0); 298 Offset = Addr.getOperand(1); 299 return true; 300 } 301 302 if (TM.getRelocationModel() != Reloc::PIC_) { 303 if ((Addr.getOpcode() == ISD::TargetExternalSymbol || 304 Addr.getOpcode() == ISD::TargetGlobalAddress)) 305 return false; 306 } 307 308 // Addresses of the form FI+const or FI|const 309 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 16)) 310 return true; 311 312 // Operand is a result from an ADD. 313 if (Addr.getOpcode() == ISD::ADD) { 314 // When loading from constant pools, load the lower address part in 315 // the instruction itself. Example, instead of: 316 // lui $2, %hi($CPI1_0) 317 // addiu $2, $2, %lo($CPI1_0) 318 // lwc1 $f0, 0($2) 319 // Generate: 320 // lui $2, %hi($CPI1_0) 321 // lwc1 $f0, %lo($CPI1_0)($2) 322 if (Addr.getOperand(1).getOpcode() == MipsISD::Lo || 323 Addr.getOperand(1).getOpcode() == MipsISD::GPRel) { 324 SDValue Opnd0 = Addr.getOperand(1).getOperand(0); 325 if (isa<ConstantPoolSDNode>(Opnd0) || isa<GlobalAddressSDNode>(Opnd0) || 326 isa<JumpTableSDNode>(Opnd0)) { 327 Base = Addr.getOperand(0); 328 Offset = Opnd0; 329 return true; 330 } 331 } 332 } 333 334 return false; 335} 336 337/// ComplexPattern used on MipsInstrInfo 338/// Used on Mips Load/Store instructions 339bool MipsSEDAGToDAGISel::selectAddrRegReg(SDValue Addr, SDValue &Base, 340 SDValue &Offset) const { 341 // Operand is a result from an ADD. 342 if (Addr.getOpcode() == ISD::ADD) { 343 Base = Addr.getOperand(0); 344 Offset = Addr.getOperand(1); 345 return true; 346 } 347 348 return false; 349} 350 351bool MipsSEDAGToDAGISel::selectAddrDefault(SDValue Addr, SDValue &Base, 352 SDValue &Offset) const { 353 Base = Addr; 354 Offset = CurDAG->getTargetConstant(0, Addr.getValueType()); 355 return true; 356} 357 358bool MipsSEDAGToDAGISel::selectIntAddr(SDValue Addr, SDValue &Base, 359 SDValue &Offset) const { 360 return selectAddrRegImm(Addr, Base, Offset) || 361 selectAddrDefault(Addr, Base, Offset); 362} 363 364bool MipsSEDAGToDAGISel::selectAddrRegImm10(SDValue Addr, SDValue &Base, 365 SDValue &Offset) const { 366 if (selectAddrFrameIndex(Addr, Base, Offset)) 367 return true; 368 369 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 10)) 370 return true; 371 372 return false; 373} 374 375/// Used on microMIPS Load/Store unaligned instructions (12-bit offset) 376bool MipsSEDAGToDAGISel::selectAddrRegImm12(SDValue Addr, SDValue &Base, 377 SDValue &Offset) const { 378 if (selectAddrFrameIndex(Addr, Base, Offset)) 379 return true; 380 381 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 12)) 382 return true; 383 384 return false; 385} 386 387bool MipsSEDAGToDAGISel::selectIntAddrMM(SDValue Addr, SDValue &Base, 388 SDValue &Offset) const { 389 return selectAddrRegImm12(Addr, Base, Offset) || 390 selectAddrDefault(Addr, Base, Offset); 391} 392 393bool MipsSEDAGToDAGISel::selectIntAddrMSA(SDValue Addr, SDValue &Base, 394 SDValue &Offset) const { 395 if (selectAddrRegImm10(Addr, Base, Offset)) 396 return true; 397 398 if (selectAddrDefault(Addr, Base, Offset)) 399 return true; 400 401 return false; 402} 403 404// Select constant vector splats. 405// 406// Returns true and sets Imm if: 407// * MSA is enabled 408// * N is a ISD::BUILD_VECTOR representing a constant splat 409bool MipsSEDAGToDAGISel::selectVSplat(SDNode *N, APInt &Imm) const { 410 if (!Subtarget.hasMSA()) 411 return false; 412 413 BuildVectorSDNode *Node = dyn_cast<BuildVectorSDNode>(N); 414 415 if (Node == NULL) 416 return false; 417 418 APInt SplatValue, SplatUndef; 419 unsigned SplatBitSize; 420 bool HasAnyUndefs; 421 422 if (!Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, 423 HasAnyUndefs, 8, 424 !Subtarget.isLittle())) 425 return false; 426 427 Imm = SplatValue; 428 429 return true; 430} 431 432// Select constant vector splats. 433// 434// In addition to the requirements of selectVSplat(), this function returns 435// true and sets Imm if: 436// * The splat value is the same width as the elements of the vector 437// * The splat value fits in an integer with the specified signed-ness and 438// width. 439// 440// This function looks through ISD::BITCAST nodes. 441// TODO: This might not be appropriate for big-endian MSA since BITCAST is 442// sometimes a shuffle in big-endian mode. 443// 444// It's worth noting that this function is not used as part of the selection 445// of ldi.[bhwd] since it does not permit using the wrong-typed ldi.[bhwd] 446// instruction to achieve the desired bit pattern. ldi.[bhwd] is selected in 447// MipsSEDAGToDAGISel::selectNode. 448bool MipsSEDAGToDAGISel:: 449selectVSplatCommon(SDValue N, SDValue &Imm, bool Signed, 450 unsigned ImmBitSize) const { 451 APInt ImmValue; 452 EVT EltTy = N->getValueType(0).getVectorElementType(); 453 454 if (N->getOpcode() == ISD::BITCAST) 455 N = N->getOperand(0); 456 457 if (selectVSplat (N.getNode(), ImmValue) && 458 ImmValue.getBitWidth() == EltTy.getSizeInBits()) { 459 if (( Signed && ImmValue.isSignedIntN(ImmBitSize)) || 460 (!Signed && ImmValue.isIntN(ImmBitSize))) { 461 Imm = CurDAG->getTargetConstant(ImmValue, EltTy); 462 return true; 463 } 464 } 465 466 return false; 467} 468 469// Select constant vector splats. 470bool MipsSEDAGToDAGISel:: 471selectVSplatUimm1(SDValue N, SDValue &Imm) const { 472 return selectVSplatCommon(N, Imm, false, 1); 473} 474 475bool MipsSEDAGToDAGISel:: 476selectVSplatUimm2(SDValue N, SDValue &Imm) const { 477 return selectVSplatCommon(N, Imm, false, 2); 478} 479 480bool MipsSEDAGToDAGISel:: 481selectVSplatUimm3(SDValue N, SDValue &Imm) const { 482 return selectVSplatCommon(N, Imm, false, 3); 483} 484 485// Select constant vector splats. 486bool MipsSEDAGToDAGISel:: 487selectVSplatUimm4(SDValue N, SDValue &Imm) const { 488 return selectVSplatCommon(N, Imm, false, 4); 489} 490 491// Select constant vector splats. 492bool MipsSEDAGToDAGISel:: 493selectVSplatUimm5(SDValue N, SDValue &Imm) const { 494 return selectVSplatCommon(N, Imm, false, 5); 495} 496 497// Select constant vector splats. 498bool MipsSEDAGToDAGISel:: 499selectVSplatUimm6(SDValue N, SDValue &Imm) const { 500 return selectVSplatCommon(N, Imm, false, 6); 501} 502 503// Select constant vector splats. 504bool MipsSEDAGToDAGISel:: 505selectVSplatUimm8(SDValue N, SDValue &Imm) const { 506 return selectVSplatCommon(N, Imm, false, 8); 507} 508 509// Select constant vector splats. 510bool MipsSEDAGToDAGISel:: 511selectVSplatSimm5(SDValue N, SDValue &Imm) const { 512 return selectVSplatCommon(N, Imm, true, 5); 513} 514 515// Select constant vector splats whose value is a power of 2. 516// 517// In addition to the requirements of selectVSplat(), this function returns 518// true and sets Imm if: 519// * The splat value is the same width as the elements of the vector 520// * The splat value is a power of two. 521// 522// This function looks through ISD::BITCAST nodes. 523// TODO: This might not be appropriate for big-endian MSA since BITCAST is 524// sometimes a shuffle in big-endian mode. 525bool MipsSEDAGToDAGISel::selectVSplatUimmPow2(SDValue N, SDValue &Imm) const { 526 APInt ImmValue; 527 EVT EltTy = N->getValueType(0).getVectorElementType(); 528 529 if (N->getOpcode() == ISD::BITCAST) 530 N = N->getOperand(0); 531 532 if (selectVSplat (N.getNode(), ImmValue) && 533 ImmValue.getBitWidth() == EltTy.getSizeInBits()) { 534 int32_t Log2 = ImmValue.exactLogBase2(); 535 536 if (Log2 != -1) { 537 Imm = CurDAG->getTargetConstant(Log2, EltTy); 538 return true; 539 } 540 } 541 542 return false; 543} 544 545// Select constant vector splats whose value only has a consecutive sequence 546// of left-most bits set (e.g. 0b11...1100...00). 547// 548// In addition to the requirements of selectVSplat(), this function returns 549// true and sets Imm if: 550// * The splat value is the same width as the elements of the vector 551// * The splat value is a consecutive sequence of left-most bits. 552// 553// This function looks through ISD::BITCAST nodes. 554// TODO: This might not be appropriate for big-endian MSA since BITCAST is 555// sometimes a shuffle in big-endian mode. 556bool MipsSEDAGToDAGISel::selectVSplatMaskL(SDValue N, SDValue &Imm) const { 557 APInt ImmValue; 558 EVT EltTy = N->getValueType(0).getVectorElementType(); 559 560 if (N->getOpcode() == ISD::BITCAST) 561 N = N->getOperand(0); 562 563 if (selectVSplat(N.getNode(), ImmValue) && 564 ImmValue.getBitWidth() == EltTy.getSizeInBits()) { 565 // Extract the run of set bits starting with bit zero from the bitwise 566 // inverse of ImmValue, and test that the inverse of this is the same 567 // as the original value. 568 if (ImmValue == ~(~ImmValue & ~(~ImmValue + 1))) { 569 570 Imm = CurDAG->getTargetConstant(ImmValue.countPopulation(), EltTy); 571 return true; 572 } 573 } 574 575 return false; 576} 577 578// Select constant vector splats whose value only has a consecutive sequence 579// of right-most bits set (e.g. 0b00...0011...11). 580// 581// In addition to the requirements of selectVSplat(), this function returns 582// true and sets Imm if: 583// * The splat value is the same width as the elements of the vector 584// * The splat value is a consecutive sequence of right-most bits. 585// 586// This function looks through ISD::BITCAST nodes. 587// TODO: This might not be appropriate for big-endian MSA since BITCAST is 588// sometimes a shuffle in big-endian mode. 589bool MipsSEDAGToDAGISel::selectVSplatMaskR(SDValue N, SDValue &Imm) const { 590 APInt ImmValue; 591 EVT EltTy = N->getValueType(0).getVectorElementType(); 592 593 if (N->getOpcode() == ISD::BITCAST) 594 N = N->getOperand(0); 595 596 if (selectVSplat(N.getNode(), ImmValue) && 597 ImmValue.getBitWidth() == EltTy.getSizeInBits()) { 598 // Extract the run of set bits starting with bit zero, and test that the 599 // result is the same as the original value 600 if (ImmValue == (ImmValue & ~(ImmValue + 1))) { 601 Imm = CurDAG->getTargetConstant(ImmValue.countPopulation(), EltTy); 602 return true; 603 } 604 } 605 606 return false; 607} 608 609bool MipsSEDAGToDAGISel::selectVSplatUimmInvPow2(SDValue N, 610 SDValue &Imm) const { 611 APInt ImmValue; 612 EVT EltTy = N->getValueType(0).getVectorElementType(); 613 614 if (N->getOpcode() == ISD::BITCAST) 615 N = N->getOperand(0); 616 617 if (selectVSplat(N.getNode(), ImmValue) && 618 ImmValue.getBitWidth() == EltTy.getSizeInBits()) { 619 int32_t Log2 = (~ImmValue).exactLogBase2(); 620 621 if (Log2 != -1) { 622 Imm = CurDAG->getTargetConstant(Log2, EltTy); 623 return true; 624 } 625 } 626 627 return false; 628} 629 630std::pair<bool, SDNode*> MipsSEDAGToDAGISel::selectNode(SDNode *Node) { 631 unsigned Opcode = Node->getOpcode(); 632 SDLoc DL(Node); 633 634 /// 635 // Instruction Selection not handled by the auto-generated 636 // tablegen selection should be handled here. 637 /// 638 SDNode *Result; 639 640 switch(Opcode) { 641 default: break; 642 643 case ISD::SUBE: { 644 SDValue InFlag = Node->getOperand(2); 645 Result = selectAddESubE(Mips::SUBu, InFlag, InFlag.getOperand(0), DL, Node); 646 return std::make_pair(true, Result); 647 } 648 649 case ISD::ADDE: { 650 if (Subtarget.hasDSP()) // Select DSP instructions, ADDSC and ADDWC. 651 break; 652 SDValue InFlag = Node->getOperand(2); 653 Result = selectAddESubE(Mips::ADDu, InFlag, InFlag.getValue(0), DL, Node); 654 return std::make_pair(true, Result); 655 } 656 657 case ISD::ConstantFP: { 658 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node); 659 if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) { 660 if (Subtarget.isGP64bit()) { 661 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL, 662 Mips::ZERO_64, MVT::i64); 663 Result = CurDAG->getMachineNode(Mips::DMTC1, DL, MVT::f64, Zero); 664 } else if (Subtarget.isFP64bit()) { 665 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL, 666 Mips::ZERO, MVT::i32); 667 Result = CurDAG->getMachineNode(Mips::BuildPairF64_64, DL, MVT::f64, 668 Zero, Zero); 669 } else { 670 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL, 671 Mips::ZERO, MVT::i32); 672 Result = CurDAG->getMachineNode(Mips::BuildPairF64, DL, MVT::f64, Zero, 673 Zero); 674 } 675 676 return std::make_pair(true, Result); 677 } 678 break; 679 } 680 681 case ISD::Constant: { 682 const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node); 683 unsigned Size = CN->getValueSizeInBits(0); 684 685 if (Size == 32) 686 break; 687 688 MipsAnalyzeImmediate AnalyzeImm; 689 int64_t Imm = CN->getSExtValue(); 690 691 const MipsAnalyzeImmediate::InstSeq &Seq = 692 AnalyzeImm.Analyze(Imm, Size, false); 693 694 MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin(); 695 SDLoc DL(CN); 696 SDNode *RegOpnd; 697 SDValue ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd), 698 MVT::i64); 699 700 // The first instruction can be a LUi which is different from other 701 // instructions (ADDiu, ORI and SLL) in that it does not have a register 702 // operand. 703 if (Inst->Opc == Mips::LUi64) 704 RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, ImmOpnd); 705 else 706 RegOpnd = 707 CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, 708 CurDAG->getRegister(Mips::ZERO_64, MVT::i64), 709 ImmOpnd); 710 711 // The remaining instructions in the sequence are handled here. 712 for (++Inst; Inst != Seq.end(); ++Inst) { 713 ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd), 714 MVT::i64); 715 RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, 716 SDValue(RegOpnd, 0), ImmOpnd); 717 } 718 719 return std::make_pair(true, RegOpnd); 720 } 721 722 case ISD::INTRINSIC_W_CHAIN: { 723 switch (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) { 724 default: 725 break; 726 727 case Intrinsic::mips_cfcmsa: { 728 SDValue ChainIn = Node->getOperand(0); 729 SDValue RegIdx = Node->getOperand(2); 730 SDValue Reg = CurDAG->getCopyFromReg(ChainIn, DL, 731 getMSACtrlReg(RegIdx), MVT::i32); 732 return std::make_pair(true, Reg.getNode()); 733 } 734 } 735 break; 736 } 737 738 case ISD::INTRINSIC_WO_CHAIN: { 739 switch (cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue()) { 740 default: 741 break; 742 743 case Intrinsic::mips_move_v: 744 // Like an assignment but will always produce a move.v even if 745 // unnecessary. 746 return std::make_pair(true, 747 CurDAG->getMachineNode(Mips::MOVE_V, DL, 748 Node->getValueType(0), 749 Node->getOperand(1))); 750 } 751 break; 752 } 753 754 case ISD::INTRINSIC_VOID: { 755 switch (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) { 756 default: 757 break; 758 759 case Intrinsic::mips_ctcmsa: { 760 SDValue ChainIn = Node->getOperand(0); 761 SDValue RegIdx = Node->getOperand(2); 762 SDValue Value = Node->getOperand(3); 763 SDValue ChainOut = CurDAG->getCopyToReg(ChainIn, DL, 764 getMSACtrlReg(RegIdx), Value); 765 return std::make_pair(true, ChainOut.getNode()); 766 } 767 } 768 break; 769 } 770 771 case MipsISD::ThreadPointer: { 772 EVT PtrVT = getTargetLowering()->getPointerTy(); 773 unsigned RdhwrOpc, DestReg; 774 775 if (PtrVT == MVT::i32) { 776 RdhwrOpc = Mips::RDHWR; 777 DestReg = Mips::V1; 778 } else { 779 RdhwrOpc = Mips::RDHWR64; 780 DestReg = Mips::V1_64; 781 } 782 783 SDNode *Rdhwr = 784 CurDAG->getMachineNode(RdhwrOpc, SDLoc(Node), 785 Node->getValueType(0), 786 CurDAG->getRegister(Mips::HWR29, MVT::i32)); 787 SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), DL, DestReg, 788 SDValue(Rdhwr, 0)); 789 SDValue ResNode = CurDAG->getCopyFromReg(Chain, DL, DestReg, PtrVT); 790 ReplaceUses(SDValue(Node, 0), ResNode); 791 return std::make_pair(true, ResNode.getNode()); 792 } 793 794 case ISD::BUILD_VECTOR: { 795 // Select appropriate ldi.[bhwd] instructions for constant splats of 796 // 128-bit when MSA is enabled. Fixup any register class mismatches that 797 // occur as a result. 798 // 799 // This allows the compiler to use a wider range of immediates than would 800 // otherwise be allowed. If, for example, v4i32 could only use ldi.h then 801 // it would not be possible to load { 0x01010101, 0x01010101, 0x01010101, 802 // 0x01010101 } without using a constant pool. This would be sub-optimal 803 // when // 'ldi.b wd, 1' is capable of producing that bit-pattern in the 804 // same set/ of registers. Similarly, ldi.h isn't capable of producing { 805 // 0x00000000, 0x00000001, 0x00000000, 0x00000001 } but 'ldi.d wd, 1' can. 806 807 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Node); 808 APInt SplatValue, SplatUndef; 809 unsigned SplatBitSize; 810 bool HasAnyUndefs; 811 unsigned LdiOp; 812 EVT ResVecTy = BVN->getValueType(0); 813 EVT ViaVecTy; 814 815 if (!Subtarget.hasMSA() || !BVN->getValueType(0).is128BitVector()) 816 return std::make_pair(false, (SDNode*)NULL); 817 818 if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, 819 HasAnyUndefs, 8, 820 !Subtarget.isLittle())) 821 return std::make_pair(false, (SDNode*)NULL); 822 823 switch (SplatBitSize) { 824 default: 825 return std::make_pair(false, (SDNode*)NULL); 826 case 8: 827 LdiOp = Mips::LDI_B; 828 ViaVecTy = MVT::v16i8; 829 break; 830 case 16: 831 LdiOp = Mips::LDI_H; 832 ViaVecTy = MVT::v8i16; 833 break; 834 case 32: 835 LdiOp = Mips::LDI_W; 836 ViaVecTy = MVT::v4i32; 837 break; 838 case 64: 839 LdiOp = Mips::LDI_D; 840 ViaVecTy = MVT::v2i64; 841 break; 842 } 843 844 if (!SplatValue.isSignedIntN(10)) 845 return std::make_pair(false, (SDNode*)NULL); 846 847 SDValue Imm = CurDAG->getTargetConstant(SplatValue, 848 ViaVecTy.getVectorElementType()); 849 850 SDNode *Res = CurDAG->getMachineNode(LdiOp, SDLoc(Node), ViaVecTy, Imm); 851 852 if (ResVecTy != ViaVecTy) { 853 // If LdiOp is writing to a different register class to ResVecTy, then 854 // fix it up here. This COPY_TO_REGCLASS should never cause a move.v 855 // since the source and destination register sets contain the same 856 // registers. 857 const TargetLowering *TLI = getTargetLowering(); 858 MVT ResVecTySimple = ResVecTy.getSimpleVT(); 859 const TargetRegisterClass *RC = TLI->getRegClassFor(ResVecTySimple); 860 Res = CurDAG->getMachineNode(Mips::COPY_TO_REGCLASS, SDLoc(Node), 861 ResVecTy, SDValue(Res, 0), 862 CurDAG->getTargetConstant(RC->getID(), 863 MVT::i32)); 864 } 865 866 return std::make_pair(true, Res); 867 } 868 869 } 870 871 return std::make_pair(false, (SDNode*)NULL); 872} 873 874FunctionPass *llvm::createMipsSEISelDag(MipsTargetMachine &TM) { 875 return new MipsSEDAGToDAGISel(TM); 876} 877