MipsSEISelDAGToDAG.cpp revision f283512d72757aac5bedcb270f9199194e6a12c0 
1//===-- MipsSEISelDAGToDAG.cpp - A Dag to Dag Inst Selector for MipsSE ----===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Subclass of MipsDAGToDAGISel specialized for mips32/64.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "mips-isel"
15#include "MipsSEISelDAGToDAG.h"
16#include "Mips.h"
17#include "MCTargetDesc/MipsBaseInfo.h"
18#include "MipsAnalyzeImmediate.h"
19#include "MipsMachineFunction.h"
20#include "MipsRegisterInfo.h"
21#include "llvm/CodeGen/MachineConstantPool.h"
22#include "llvm/CodeGen/MachineFrameInfo.h"
23#include "llvm/CodeGen/MachineFunction.h"
24#include "llvm/CodeGen/MachineInstrBuilder.h"
25#include "llvm/CodeGen/MachineRegisterInfo.h"
26#include "llvm/CodeGen/SelectionDAGNodes.h"
27#include "llvm/IR/GlobalValue.h"
28#include "llvm/IR/Instructions.h"
29#include "llvm/IR/Intrinsics.h"
30#include "llvm/IR/Type.h"
31#include "llvm/Support/CFG.h"
32#include "llvm/Support/Debug.h"
33#include "llvm/Support/ErrorHandling.h"
34#include "llvm/Support/raw_ostream.h"
35#include "llvm/Target/TargetMachine.h"
36using namespace llvm;
37
38
39bool MipsSEDAGToDAGISel::replaceUsesWithZeroReg(MachineRegisterInfo *MRI,
40                                                const MachineInstr& MI) {
41  unsigned DstReg = 0, ZeroReg = 0;
42
43  // Check if MI is "addiu $dst, $zero, 0" or "daddiu $dst, $zero, 0".
44  if ((MI.getOpcode() == Mips::ADDiu) &&
45      (MI.getOperand(1).getReg() == Mips::ZERO) &&
46      (MI.getOperand(2).getImm() == 0)) {
47    DstReg = MI.getOperand(0).getReg();
48    ZeroReg = Mips::ZERO;
49  } else if ((MI.getOpcode() == Mips::DADDiu) &&
50             (MI.getOperand(1).getReg() == Mips::ZERO_64) &&
51             (MI.getOperand(2).getImm() == 0)) {
52    DstReg = MI.getOperand(0).getReg();
53    ZeroReg = Mips::ZERO_64;
54  }
55
56  if (!DstReg)
57    return false;
58
59  // Replace uses with ZeroReg.
60  for (MachineRegisterInfo::use_iterator U = MRI->use_begin(DstReg),
61       E = MRI->use_end(); U != E;) {
62    MachineOperand &MO = U.getOperand();
63    unsigned OpNo = U.getOperandNo();
64    MachineInstr *MI = MO.getParent();
65    ++U;
66
67    // Do not replace if it is a phi's operand or is tied to def operand.
68    if (MI->isPHI() || MI->isRegTiedToDefOperand(OpNo) || MI->isPseudo())
69      continue;
70
71    MO.setReg(ZeroReg);
72  }
73
74  return true;
75}
76
77void MipsSEDAGToDAGISel::initGlobalBaseReg(MachineFunction &MF) {
78  MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
79
80  if (!MipsFI->globalBaseRegSet())
81    return;
82
83  MachineBasicBlock &MBB = MF.front();
84  MachineBasicBlock::iterator I = MBB.begin();
85  MachineRegisterInfo &RegInfo = MF.getRegInfo();
86  const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
87  DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
88  unsigned V0, V1, GlobalBaseReg = MipsFI->getGlobalBaseReg();
89  const TargetRegisterClass *RC;
90
91  if (Subtarget.isABI_N64())
92    RC = (const TargetRegisterClass*)&Mips::CPU64RegsRegClass;
93  else
94    RC = (const TargetRegisterClass*)&Mips::CPURegsRegClass;
95
96  V0 = RegInfo.createVirtualRegister(RC);
97  V1 = RegInfo.createVirtualRegister(RC);
98
99  if (Subtarget.isABI_N64()) {
100    MF.getRegInfo().addLiveIn(Mips::T9_64);
101    MBB.addLiveIn(Mips::T9_64);
102
103    // lui $v0, %hi(%neg(%gp_rel(fname)))
104    // daddu $v1, $v0, $t9
105    // daddiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
106    const GlobalValue *FName = MF.getFunction();
107    BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0)
108      .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
109    BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0)
110      .addReg(Mips::T9_64);
111    BuildMI(MBB, I, DL, TII.get(Mips::DADDiu), GlobalBaseReg).addReg(V1)
112      .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
113    return;
114  }
115
116  if (MF.getTarget().getRelocationModel() == Reloc::Static) {
117    // Set global register to __gnu_local_gp.
118    //
119    // lui   $v0, %hi(__gnu_local_gp)
120    // addiu $globalbasereg, $v0, %lo(__gnu_local_gp)
121    BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
122      .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_HI);
123    BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
124      .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_LO);
125    return;
126  }
127
128  MF.getRegInfo().addLiveIn(Mips::T9);
129  MBB.addLiveIn(Mips::T9);
130
131  if (Subtarget.isABI_N32()) {
132    // lui $v0, %hi(%neg(%gp_rel(fname)))
133    // addu $v1, $v0, $t9
134    // addiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
135    const GlobalValue *FName = MF.getFunction();
136    BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
137      .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
138    BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9);
139    BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1)
140      .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
141    return;
142  }
143
144  assert(Subtarget.isABI_O32());
145
146  // For O32 ABI, the following instruction sequence is emitted to initialize
147  // the global base register:
148  //
149  //  0. lui   $2, %hi(_gp_disp)
150  //  1. addiu $2, $2, %lo(_gp_disp)
151  //  2. addu  $globalbasereg, $2, $t9
152  //
153  // We emit only the last instruction here.
154  //
155  // GNU linker requires that the first two instructions appear at the beginning
156  // of a function and no instructions be inserted before or between them.
157  // The two instructions are emitted during lowering to MC layer in order to
158  // avoid any reordering.
159  //
160  // Register $2 (Mips::V0) is added to the list of live-in registers to ensure
161  // the value instruction 1 (addiu) defines is valid when instruction 2 (addu)
162  // reads it.
163  MF.getRegInfo().addLiveIn(Mips::V0);
164  MBB.addLiveIn(Mips::V0);
165  BuildMI(MBB, I, DL, TII.get(Mips::ADDu), GlobalBaseReg)
166    .addReg(Mips::V0).addReg(Mips::T9);
167}
168
169void MipsSEDAGToDAGISel::processFunctionAfterISel(MachineFunction &MF) {
170  initGlobalBaseReg(MF);
171
172  MachineRegisterInfo *MRI = &MF.getRegInfo();
173
174  for (MachineFunction::iterator MFI = MF.begin(), MFE = MF.end(); MFI != MFE;
175       ++MFI)
176    for (MachineBasicBlock::iterator I = MFI->begin(); I != MFI->end(); ++I)
177      replaceUsesWithZeroReg(MRI, *I);
178}
179
180/// Select multiply instructions.
181std::pair<SDNode*, SDNode*>
182MipsSEDAGToDAGISel::selectMULT(SDNode *N, unsigned Opc, DebugLoc DL, EVT Ty,
183                               bool HasLo, bool HasHi) {
184  SDNode *Lo = 0, *Hi = 0;
185  SDNode *Mul = CurDAG->getMachineNode(Opc, DL, MVT::Glue, N->getOperand(0),
186                                       N->getOperand(1));
187  SDValue InFlag = SDValue(Mul, 0);
188
189  if (HasLo) {
190    unsigned Opcode = (Ty == MVT::i32 ? Mips::MFLO : Mips::MFLO64);
191    Lo = CurDAG->getMachineNode(Opcode, DL, Ty, MVT::Glue, InFlag);
192    InFlag = SDValue(Lo, 1);
193  }
194  if (HasHi) {
195    unsigned Opcode = (Ty == MVT::i32 ? Mips::MFHI : Mips::MFHI64);
196    Hi = CurDAG->getMachineNode(Opcode, DL, Ty, InFlag);
197  }
198  return std::make_pair(Lo, Hi);
199}
200
201/// ComplexPattern used on MipsInstrInfo
202/// Used on Mips Load/Store instructions
203bool MipsSEDAGToDAGISel::selectAddrRegImm(SDValue Addr, SDValue &Base,
204                                          SDValue &Offset) const {
205  EVT ValTy = Addr.getValueType();
206
207  // if Address is FI, get the TargetFrameIndex.
208  if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
209    Base   = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
210    Offset = CurDAG->getTargetConstant(0, ValTy);
211    return true;
212  }
213
214  // on PIC code Load GA
215  if (Addr.getOpcode() == MipsISD::Wrapper) {
216    Base   = Addr.getOperand(0);
217    Offset = Addr.getOperand(1);
218    return true;
219  }
220
221  if (TM.getRelocationModel() != Reloc::PIC_) {
222    if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
223        Addr.getOpcode() == ISD::TargetGlobalAddress))
224      return false;
225  }
226
227  // Addresses of the form FI+const or FI|const
228  if (CurDAG->isBaseWithConstantOffset(Addr)) {
229    ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
230    if (isInt<16>(CN->getSExtValue())) {
231
232      // If the first operand is a FI, get the TargetFI Node
233      if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
234                                  (Addr.getOperand(0)))
235        Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
236      else
237        Base = Addr.getOperand(0);
238
239      Offset = CurDAG->getTargetConstant(CN->getZExtValue(), ValTy);
240      return true;
241    }
242  }
243
244  // Operand is a result from an ADD.
245  if (Addr.getOpcode() == ISD::ADD) {
246    // When loading from constant pools, load the lower address part in
247    // the instruction itself. Example, instead of:
248    //  lui $2, %hi($CPI1_0)
249    //  addiu $2, $2, %lo($CPI1_0)
250    //  lwc1 $f0, 0($2)
251    // Generate:
252    //  lui $2, %hi($CPI1_0)
253    //  lwc1 $f0, %lo($CPI1_0)($2)
254    if (Addr.getOperand(1).getOpcode() == MipsISD::Lo ||
255        Addr.getOperand(1).getOpcode() == MipsISD::GPRel) {
256      SDValue Opnd0 = Addr.getOperand(1).getOperand(0);
257      if (isa<ConstantPoolSDNode>(Opnd0) || isa<GlobalAddressSDNode>(Opnd0) ||
258          isa<JumpTableSDNode>(Opnd0)) {
259        Base = Addr.getOperand(0);
260        Offset = Opnd0;
261        return true;
262      }
263    }
264  }
265
266  return false;
267}
268
269bool MipsSEDAGToDAGISel::selectAddrDefault(SDValue Addr, SDValue &Base,
270                                           SDValue &Offset) const {
271  Base = Addr;
272  Offset = CurDAG->getTargetConstant(0, Addr.getValueType());
273  return true;
274}
275
276bool MipsSEDAGToDAGISel::selectIntAddr(SDValue Addr, SDValue &Base,
277                                       SDValue &Offset) const {
278  return selectAddrRegImm(Addr, Base, Offset) ||
279    selectAddrDefault(Addr, Base, Offset);
280}
281
282std::pair<bool, SDNode*> MipsSEDAGToDAGISel::selectNode(SDNode *Node) {
283  unsigned Opcode = Node->getOpcode();
284  DebugLoc DL = Node->getDebugLoc();
285
286  ///
287  // Instruction Selection not handled by the auto-generated
288  // tablegen selection should be handled here.
289  ///
290  EVT NodeTy = Node->getValueType(0);
291  SDNode *Result;
292  unsigned MultOpc;
293
294  switch(Opcode) {
295  default: break;
296
297  case ISD::SUBE:
298  case ISD::ADDE: {
299    SDValue InFlag = Node->getOperand(2), CmpLHS;
300    unsigned Opc = InFlag.getOpcode(); (void)Opc;
301    assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
302            (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
303           "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");
304
305    unsigned MOp;
306    if (Opcode == ISD::ADDE) {
307      CmpLHS = InFlag.getValue(0);
308      MOp = Mips::ADDu;
309    } else {
310      CmpLHS = InFlag.getOperand(0);
311      MOp = Mips::SUBu;
312    }
313
314    SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };
315
316    SDValue LHS = Node->getOperand(0);
317    SDValue RHS = Node->getOperand(1);
318
319    EVT VT = LHS.getValueType();
320
321    unsigned Sltu_op = Mips::SLTu;
322    SDNode *Carry = CurDAG->getMachineNode(Sltu_op, DL, VT, Ops, 2);
323    unsigned Addu_op = Mips::ADDu;
324    SDNode *AddCarry = CurDAG->getMachineNode(Addu_op, DL, VT,
325                                              SDValue(Carry,0), RHS);
326
327    Result = CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue, LHS,
328                                  SDValue(AddCarry,0));
329    return std::make_pair(true, Result);
330  }
331
332  /// Mul with two results
333  case ISD::SMUL_LOHI:
334  case ISD::UMUL_LOHI: {
335    if (NodeTy == MVT::i32)
336      MultOpc = (Opcode == ISD::UMUL_LOHI ? Mips::MULTu : Mips::MULT);
337    else
338      MultOpc = (Opcode == ISD::UMUL_LOHI ? Mips::DMULTu : Mips::DMULT);
339
340    std::pair<SDNode*, SDNode*> LoHi = selectMULT(Node, MultOpc, DL, NodeTy,
341                                                  true, true);
342
343    if (!SDValue(Node, 0).use_empty())
344      ReplaceUses(SDValue(Node, 0), SDValue(LoHi.first, 0));
345
346    if (!SDValue(Node, 1).use_empty())
347      ReplaceUses(SDValue(Node, 1), SDValue(LoHi.second, 0));
348
349    return std::make_pair(true, (SDNode*)NULL);
350  }
351
352  /// Special Muls
353  case ISD::MUL: {
354    // Mips32 has a 32-bit three operand mul instruction.
355    if (Subtarget.hasMips32() && NodeTy == MVT::i32)
356      break;
357    MultOpc = NodeTy == MVT::i32 ? Mips::MULT : Mips::DMULT;
358    Result = selectMULT(Node, MultOpc, DL, NodeTy, true, false).first;
359    return std::make_pair(true, Result);
360  }
361  case ISD::MULHS:
362  case ISD::MULHU: {
363    if (NodeTy == MVT::i32)
364      MultOpc = (Opcode == ISD::MULHU ? Mips::MULTu : Mips::MULT);
365    else
366      MultOpc = (Opcode == ISD::MULHU ? Mips::DMULTu : Mips::DMULT);
367
368    Result = selectMULT(Node, MultOpc, DL, NodeTy, false, true).second;
369    return std::make_pair(true, Result);
370  }
371
372  case ISD::ConstantFP: {
373    ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node);
374    if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
375      if (Subtarget.hasMips64()) {
376        SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
377                                              Mips::ZERO_64, MVT::i64);
378        Result = CurDAG->getMachineNode(Mips::DMTC1, DL, MVT::f64, Zero);
379      } else {
380        SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
381                                              Mips::ZERO, MVT::i32);
382        Result = CurDAG->getMachineNode(Mips::BuildPairF64, DL, MVT::f64, Zero,
383                                        Zero);
384      }
385
386      return std::make_pair(true, Result);
387    }
388    break;
389  }
390
391  case ISD::Constant: {
392    const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node);
393    unsigned Size = CN->getValueSizeInBits(0);
394
395    if (Size == 32)
396      break;
397
398    MipsAnalyzeImmediate AnalyzeImm;
399    int64_t Imm = CN->getSExtValue();
400
401    const MipsAnalyzeImmediate::InstSeq &Seq =
402      AnalyzeImm.Analyze(Imm, Size, false);
403
404    MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
405    DebugLoc DL = CN->getDebugLoc();
406    SDNode *RegOpnd;
407    SDValue ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
408                                                MVT::i64);
409
410    // The first instruction can be a LUi which is different from other
411    // instructions (ADDiu, ORI and SLL) in that it does not have a register
412    // operand.
413    if (Inst->Opc == Mips::LUi64)
414      RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, ImmOpnd);
415    else
416      RegOpnd =
417        CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
418                               CurDAG->getRegister(Mips::ZERO_64, MVT::i64),
419                               ImmOpnd);
420
421    // The remaining instructions in the sequence are handled here.
422    for (++Inst; Inst != Seq.end(); ++Inst) {
423      ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
424                                          MVT::i64);
425      RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
426                                       SDValue(RegOpnd, 0), ImmOpnd);
427    }
428
429    return std::make_pair(true, RegOpnd);
430  }
431
432  case MipsISD::ThreadPointer: {
433    EVT PtrVT = TLI.getPointerTy();
434    unsigned RdhwrOpc, SrcReg, DestReg;
435
436    if (PtrVT == MVT::i32) {
437      RdhwrOpc = Mips::RDHWR;
438      SrcReg = Mips::HWR29;
439      DestReg = Mips::V1;
440    } else {
441      RdhwrOpc = Mips::RDHWR64;
442      SrcReg = Mips::HWR29_64;
443      DestReg = Mips::V1_64;
444    }
445
446    SDNode *Rdhwr =
447      CurDAG->getMachineNode(RdhwrOpc, Node->getDebugLoc(),
448                             Node->getValueType(0),
449                             CurDAG->getRegister(SrcReg, PtrVT));
450    SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), DL, DestReg,
451                                         SDValue(Rdhwr, 0));
452    SDValue ResNode = CurDAG->getCopyFromReg(Chain, DL, DestReg, PtrVT);
453    ReplaceUses(SDValue(Node, 0), ResNode);
454    return std::make_pair(true, ResNode.getNode());
455  }
456  }
457
458  return std::make_pair(false, (SDNode*)NULL);
459}
460
461FunctionPass *llvm::createMipsSEISelDag(MipsTargetMachine &TM) {
462  return new MipsSEDAGToDAGISel(TM);
463}
464