PPCISelLowering.cpp revision 860e8862c1fbd3b261da4a64a8c0096f9f373681
1//===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Chris Lattner and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the PPCISelLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "PPCISelLowering.h" 15#include "PPCTargetMachine.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/CodeGen/MachineFunction.h" 18#include "llvm/CodeGen/MachineInstrBuilder.h" 19#include "llvm/CodeGen/SelectionDAG.h" 20#include "llvm/CodeGen/SSARegMap.h" 21#include "llvm/Constants.h" 22#include "llvm/Function.h" 23using namespace llvm; 24 25PPCTargetLowering::PPCTargetLowering(TargetMachine &TM) 26 : TargetLowering(TM) { 27 28 // Fold away setcc operations if possible. 29 setSetCCIsExpensive(); 30 setPow2DivIsCheap(); 31 32 // Use _setjmp/_longjmp instead of setjmp/longjmp. 33 setUseUnderscoreSetJmpLongJmp(true); 34 35 // Set up the register classes. 36 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass); 37 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass); 38 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass); 39 40 // PowerPC has no intrinsics for these particular operations 41 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand); 42 setOperationAction(ISD::MEMSET, MVT::Other, Expand); 43 setOperationAction(ISD::MEMCPY, MVT::Other, Expand); 44 45 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD 46 setOperationAction(ISD::SEXTLOAD, MVT::i1, Expand); 47 setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand); 48 49 // PowerPC has no SREM/UREM instructions 50 setOperationAction(ISD::SREM, MVT::i32, Expand); 51 setOperationAction(ISD::UREM, MVT::i32, Expand); 52 53 // We don't support sin/cos/sqrt/fmod 54 setOperationAction(ISD::FSIN , MVT::f64, Expand); 55 setOperationAction(ISD::FCOS , MVT::f64, Expand); 56 setOperationAction(ISD::FREM , MVT::f64, Expand); 57 setOperationAction(ISD::FSIN , MVT::f32, Expand); 58 setOperationAction(ISD::FCOS , MVT::f32, Expand); 59 setOperationAction(ISD::FREM , MVT::f32, Expand); 60 61 // If we're enabling GP optimizations, use hardware square root 62 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) { 63 setOperationAction(ISD::FSQRT, MVT::f64, Expand); 64 setOperationAction(ISD::FSQRT, MVT::f32, Expand); 65 } 66 67 // PowerPC does not have CTPOP or CTTZ 68 setOperationAction(ISD::CTPOP, MVT::i32 , Expand); 69 setOperationAction(ISD::CTTZ , MVT::i32 , Expand); 70 71 // PowerPC does not have Select 72 setOperationAction(ISD::SELECT, MVT::i32, Expand); 73 setOperationAction(ISD::SELECT, MVT::f32, Expand); 74 setOperationAction(ISD::SELECT, MVT::f64, Expand); 75 76 // PowerPC wants to turn select_cc of FP into fsel when possible. 77 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 78 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 79 80 // PowerPC does not have BRCOND* which requires SetCC 81 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 82 setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand); 83 84 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores. 85 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 86 87 // PowerPC does not have [U|S]INT_TO_FP 88 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); 89 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 90 91 // PowerPC does not have truncstore for i1. 92 setOperationAction(ISD::TRUNCSTORE, MVT::i1, Promote); 93 94 // We want to legalize GlobalAddress into the appropriate instructions to 95 // materialize the address. 96 //setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 97 98 if (TM.getSubtarget<PPCSubtarget>().is64Bit()) { 99 // They also have instructions for converting between i64 and fp. 100 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); 101 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); 102 // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT 103 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote); 104 } else { 105 // PowerPC does not have FP_TO_UINT on 32-bit implementations. 106 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 107 } 108 109 if (TM.getSubtarget<PPCSubtarget>().has64BitRegs()) { 110 // 64 bit PowerPC implementations can support i64 types directly 111 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass); 112 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or 113 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand); 114 } else { 115 // 32 bit PowerPC wants to expand i64 shifts itself. 116 setOperationAction(ISD::SHL, MVT::i64, Custom); 117 setOperationAction(ISD::SRL, MVT::i64, Custom); 118 setOperationAction(ISD::SRA, MVT::i64, Custom); 119 } 120 121 setSetCCResultContents(ZeroOrOneSetCCResult); 122 123 computeRegisterProperties(); 124} 125 126/// isFloatingPointZero - Return true if this is 0.0 or -0.0. 127static bool isFloatingPointZero(SDOperand Op) { 128 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) 129 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0); 130 else if (Op.getOpcode() == ISD::EXTLOAD || Op.getOpcode() == ISD::LOAD) { 131 // Maybe this has already been legalized into the constant pool? 132 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1))) 133 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->get())) 134 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0); 135 } 136 return false; 137} 138 139/// LowerOperation - Provide custom lowering hooks for some operations. 140/// 141SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { 142 switch (Op.getOpcode()) { 143 default: assert(0 && "Wasn't expecting to be able to lower this!"); 144 case ISD::FP_TO_SINT: { 145 assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType())); 146 SDOperand Src = Op.getOperand(0); 147 if (Src.getValueType() == MVT::f32) 148 Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src); 149 150 switch (Op.getValueType()) { 151 default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!"); 152 case MVT::i32: 153 Op = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src); 154 break; 155 case MVT::i64: 156 Op = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src); 157 break; 158 } 159 160 int FrameIdx = 161 DAG.getMachineFunction().getFrameInfo()->CreateStackObject(8, 8); 162 SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i32); 163 SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 164 Op, FI, DAG.getSrcValue(0)); 165 if (Op.getOpcode() == PPCISD::FCTIDZ) { 166 Op = DAG.getLoad(MVT::i64, ST, FI, DAG.getSrcValue(0)); 167 } else { 168 FI = DAG.getNode(ISD::ADD, MVT::i32, FI, DAG.getConstant(4, MVT::i32)); 169 Op = DAG.getLoad(MVT::i32, ST, FI, DAG.getSrcValue(0)); 170 } 171 return Op; 172 } 173 case ISD::SINT_TO_FP: { 174 assert(MVT::i64 == Op.getOperand(0).getValueType() && 175 "Unhandled SINT_TO_FP type in custom expander!"); 176 int FrameIdx = 177 DAG.getMachineFunction().getFrameInfo()->CreateStackObject(8, 8); 178 SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i32); 179 SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 180 Op.getOperand(0), FI, DAG.getSrcValue(0)); 181 SDOperand LD = DAG.getLoad(MVT::f64, ST, FI, DAG.getSrcValue(0)); 182 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, LD); 183 if (MVT::f32 == Op.getValueType()) 184 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP); 185 return FP; 186 } 187 case ISD::SELECT_CC: { 188 // Turn FP only select_cc's into fsel instructions. 189 if (!MVT::isFloatingPoint(Op.getOperand(0).getValueType()) || 190 !MVT::isFloatingPoint(Op.getOperand(2).getValueType())) 191 break; 192 193 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 194 195 // Cannot handle SETEQ/SETNE. 196 if (CC == ISD::SETEQ || CC == ISD::SETNE) break; 197 198 MVT::ValueType ResVT = Op.getValueType(); 199 MVT::ValueType CmpVT = Op.getOperand(0).getValueType(); 200 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); 201 SDOperand TV = Op.getOperand(2), FV = Op.getOperand(3); 202 203 // If the RHS of the comparison is a 0.0, we don't need to do the 204 // subtraction at all. 205 if (isFloatingPointZero(RHS)) 206 switch (CC) { 207 default: assert(0 && "Invalid FSEL condition"); abort(); 208 case ISD::SETULT: 209 case ISD::SETLT: 210 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 211 case ISD::SETUGE: 212 case ISD::SETGE: 213 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 214 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS); 215 return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV); 216 case ISD::SETUGT: 217 case ISD::SETGT: 218 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 219 case ISD::SETULE: 220 case ISD::SETLE: 221 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 222 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS); 223 return DAG.getNode(PPCISD::FSEL, ResVT, 224 DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV); 225 } 226 227 SDOperand Cmp; 228 switch (CC) { 229 default: assert(0 && "Invalid FSEL condition"); abort(); 230 case ISD::SETULT: 231 case ISD::SETLT: 232 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS); 233 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 234 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 235 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV); 236 case ISD::SETUGE: 237 case ISD::SETGE: 238 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS); 239 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 240 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 241 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV); 242 case ISD::SETUGT: 243 case ISD::SETGT: 244 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS); 245 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 246 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 247 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV); 248 case ISD::SETULE: 249 case ISD::SETLE: 250 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS); 251 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 252 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 253 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV); 254 } 255 break; 256 } 257 case ISD::SHL: { 258 assert(Op.getValueType() == MVT::i64 && 259 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!"); 260 // The generic code does a fine job expanding shift by a constant. 261 if (isa<ConstantSDNode>(Op.getOperand(1))) break; 262 263 // Otherwise, expand into a bunch of logical ops. Note that these ops 264 // depend on the PPC behavior for oversized shift amounts. 265 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), 266 DAG.getConstant(0, MVT::i32)); 267 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), 268 DAG.getConstant(1, MVT::i32)); 269 SDOperand Amt = Op.getOperand(1); 270 271 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32, 272 DAG.getConstant(32, MVT::i32), Amt); 273 SDOperand Tmp2 = DAG.getNode(ISD::SHL, MVT::i32, Hi, Amt); 274 SDOperand Tmp3 = DAG.getNode(ISD::SRL, MVT::i32, Lo, Tmp1); 275 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3); 276 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt, 277 DAG.getConstant(-32U, MVT::i32)); 278 SDOperand Tmp6 = DAG.getNode(ISD::SHL, MVT::i32, Lo, Tmp5); 279 SDOperand OutHi = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6); 280 SDOperand OutLo = DAG.getNode(ISD::SHL, MVT::i32, Lo, Amt); 281 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi); 282 } 283 case ISD::SRL: { 284 assert(Op.getValueType() == MVT::i64 && 285 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!"); 286 // The generic code does a fine job expanding shift by a constant. 287 if (isa<ConstantSDNode>(Op.getOperand(1))) break; 288 289 // Otherwise, expand into a bunch of logical ops. Note that these ops 290 // depend on the PPC behavior for oversized shift amounts. 291 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), 292 DAG.getConstant(0, MVT::i32)); 293 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), 294 DAG.getConstant(1, MVT::i32)); 295 SDOperand Amt = Op.getOperand(1); 296 297 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32, 298 DAG.getConstant(32, MVT::i32), Amt); 299 SDOperand Tmp2 = DAG.getNode(ISD::SRL, MVT::i32, Lo, Amt); 300 SDOperand Tmp3 = DAG.getNode(ISD::SHL, MVT::i32, Hi, Tmp1); 301 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3); 302 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt, 303 DAG.getConstant(-32U, MVT::i32)); 304 SDOperand Tmp6 = DAG.getNode(ISD::SRL, MVT::i32, Hi, Tmp5); 305 SDOperand OutLo = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6); 306 SDOperand OutHi = DAG.getNode(ISD::SRL, MVT::i32, Hi, Amt); 307 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi); 308 } 309 case ISD::SRA: { 310 assert(Op.getValueType() == MVT::i64 && 311 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRA!"); 312 // The generic code does a fine job expanding shift by a constant. 313 if (isa<ConstantSDNode>(Op.getOperand(1))) break; 314 315 // Otherwise, expand into a bunch of logical ops, followed by a select_cc. 316 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), 317 DAG.getConstant(0, MVT::i32)); 318 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), 319 DAG.getConstant(1, MVT::i32)); 320 SDOperand Amt = Op.getOperand(1); 321 322 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32, 323 DAG.getConstant(32, MVT::i32), Amt); 324 SDOperand Tmp2 = DAG.getNode(ISD::SRL, MVT::i32, Lo, Amt); 325 SDOperand Tmp3 = DAG.getNode(ISD::SHL, MVT::i32, Hi, Tmp1); 326 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3); 327 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt, 328 DAG.getConstant(-32U, MVT::i32)); 329 SDOperand Tmp6 = DAG.getNode(ISD::SRA, MVT::i32, Hi, Tmp5); 330 SDOperand OutHi = DAG.getNode(ISD::SRA, MVT::i32, Hi, Amt); 331 SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, MVT::i32), 332 Tmp4, Tmp6, ISD::SETLE); 333 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi); 334 } 335 case ISD::GlobalAddress: { 336 // Only lower GlobalAddress on Darwin. 337 if (!getTargetMachine().getSubtarget<PPCSubtarget>().isDarwin()) break; 338 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 339 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32); 340 SDOperand Zero = DAG.getConstant(0, MVT::i32); 341 342 SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, GA, Zero); 343 if (PICEnabled) { 344 // With PIC, the first instruction is actually "GR+hi(&G)". 345 Hi = DAG.getNode(ISD::ADD, MVT::i32, 346 DAG.getTargetNode(PPCISD::GlobalBaseReg, MVT::i32), Hi); 347 } 348 349 SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, GA, Zero); 350 Lo = DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo); 351 352 if (!GV->hasWeakLinkage() && !GV->isExternal()) 353 return Lo; 354 355 // If the global is weak or external, we have to go through the lazy 356 // resolution stub. 357 return DAG.getLoad(MVT::i32, DAG.getEntryNode(), Lo, DAG.getSrcValue(0)); 358 } 359 } 360 return SDOperand(); 361} 362 363std::vector<SDOperand> 364PPCTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { 365 // 366 // add beautiful description of PPC stack frame format, or at least some docs 367 // 368 MachineFunction &MF = DAG.getMachineFunction(); 369 MachineFrameInfo *MFI = MF.getFrameInfo(); 370 MachineBasicBlock& BB = MF.front(); 371 SSARegMap *RegMap = MF.getSSARegMap(); 372 std::vector<SDOperand> ArgValues; 373 374 unsigned ArgOffset = 24; 375 unsigned GPR_remaining = 8; 376 unsigned FPR_remaining = 13; 377 unsigned GPR_idx = 0, FPR_idx = 0; 378 static const unsigned GPR[] = { 379 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 380 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 381 }; 382 static const unsigned FPR[] = { 383 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 384 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13 385 }; 386 387 // Add DAG nodes to load the arguments... On entry to a function on PPC, 388 // the arguments start at offset 24, although they are likely to be passed 389 // in registers. 390 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { 391 SDOperand newroot, argt; 392 unsigned ObjSize; 393 bool needsLoad = false; 394 bool ArgLive = !I->use_empty(); 395 MVT::ValueType ObjectVT = getValueType(I->getType()); 396 397 switch (ObjectVT) { 398 default: assert(0 && "Unhandled argument type!"); 399 case MVT::i1: 400 case MVT::i8: 401 case MVT::i16: 402 case MVT::i32: 403 ObjSize = 4; 404 if (!ArgLive) break; 405 if (GPR_remaining > 0) { 406 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass); 407 MF.addLiveIn(GPR[GPR_idx], VReg); 408 argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32); 409 if (ObjectVT != MVT::i32) { 410 unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext 411 : ISD::AssertZext; 412 argt = DAG.getNode(AssertOp, MVT::i32, argt, 413 DAG.getValueType(ObjectVT)); 414 argt = DAG.getNode(ISD::TRUNCATE, ObjectVT, argt); 415 } 416 } else { 417 needsLoad = true; 418 } 419 break; 420 case MVT::i64: ObjSize = 8; 421 if (!ArgLive) break; 422 if (GPR_remaining > 0) { 423 SDOperand argHi, argLo; 424 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass); 425 MF.addLiveIn(GPR[GPR_idx], VReg); 426 argHi = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32); 427 // If we have two or more remaining argument registers, then both halves 428 // of the i64 can be sourced from there. Otherwise, the lower half will 429 // have to come off the stack. This can happen when an i64 is preceded 430 // by 28 bytes of arguments. 431 if (GPR_remaining > 1) { 432 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass); 433 MF.addLiveIn(GPR[GPR_idx+1], VReg); 434 argLo = DAG.getCopyFromReg(argHi, VReg, MVT::i32); 435 } else { 436 int FI = MFI->CreateFixedObject(4, ArgOffset+4); 437 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32); 438 argLo = DAG.getLoad(MVT::i32, DAG.getEntryNode(), FIN, 439 DAG.getSrcValue(NULL)); 440 } 441 // Build the outgoing arg thingy 442 argt = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, argLo, argHi); 443 newroot = argLo; 444 } else { 445 needsLoad = true; 446 } 447 break; 448 case MVT::f32: 449 case MVT::f64: 450 ObjSize = (ObjectVT == MVT::f64) ? 8 : 4; 451 if (!ArgLive) break; 452 if (FPR_remaining > 0) { 453 unsigned VReg; 454 if (ObjectVT == MVT::f32) 455 VReg = RegMap->createVirtualRegister(&PPC::F4RCRegClass); 456 else 457 VReg = RegMap->createVirtualRegister(&PPC::F8RCRegClass); 458 MF.addLiveIn(FPR[FPR_idx], VReg); 459 argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), VReg, ObjectVT); 460 --FPR_remaining; 461 ++FPR_idx; 462 } else { 463 needsLoad = true; 464 } 465 break; 466 } 467 468 // We need to load the argument to a virtual register if we determined above 469 // that we ran out of physical registers of the appropriate type 470 if (needsLoad) { 471 unsigned SubregOffset = 0; 472 if (ObjectVT == MVT::i8 || ObjectVT == MVT::i1) SubregOffset = 3; 473 if (ObjectVT == MVT::i16) SubregOffset = 2; 474 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset); 475 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32); 476 FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN, 477 DAG.getConstant(SubregOffset, MVT::i32)); 478 argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN, 479 DAG.getSrcValue(NULL)); 480 } 481 482 // Every 4 bytes of argument space consumes one of the GPRs available for 483 // argument passing. 484 if (GPR_remaining > 0) { 485 unsigned delta = (GPR_remaining > 1 && ObjSize == 8) ? 2 : 1; 486 GPR_remaining -= delta; 487 GPR_idx += delta; 488 } 489 ArgOffset += ObjSize; 490 if (newroot.Val) 491 DAG.setRoot(newroot.getValue(1)); 492 493 ArgValues.push_back(argt); 494 } 495 496 // If the function takes variable number of arguments, make a frame index for 497 // the start of the first vararg value... for expansion of llvm.va_start. 498 if (F.isVarArg()) { 499 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset); 500 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32); 501 // If this function is vararg, store any remaining integer argument regs 502 // to their spots on the stack so that they may be loaded by deferencing the 503 // result of va_next. 504 std::vector<SDOperand> MemOps; 505 for (; GPR_remaining > 0; --GPR_remaining, ++GPR_idx) { 506 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass); 507 MF.addLiveIn(GPR[GPR_idx], VReg); 508 SDOperand Val = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32); 509 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1), 510 Val, FIN, DAG.getSrcValue(NULL)); 511 MemOps.push_back(Store); 512 // Increment the address by four for the next argument to store 513 SDOperand PtrOff = DAG.getConstant(4, getPointerTy()); 514 FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN, PtrOff); 515 } 516 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps)); 517 } 518 519 // Finally, inform the code generator which regs we return values in. 520 switch (getValueType(F.getReturnType())) { 521 default: assert(0 && "Unknown type!"); 522 case MVT::isVoid: break; 523 case MVT::i1: 524 case MVT::i8: 525 case MVT::i16: 526 case MVT::i32: 527 MF.addLiveOut(PPC::R3); 528 break; 529 case MVT::i64: 530 MF.addLiveOut(PPC::R3); 531 MF.addLiveOut(PPC::R4); 532 break; 533 case MVT::f32: 534 case MVT::f64: 535 MF.addLiveOut(PPC::F1); 536 break; 537 } 538 539 return ArgValues; 540} 541 542std::pair<SDOperand, SDOperand> 543PPCTargetLowering::LowerCallTo(SDOperand Chain, 544 const Type *RetTy, bool isVarArg, 545 unsigned CallingConv, bool isTailCall, 546 SDOperand Callee, ArgListTy &Args, 547 SelectionDAG &DAG) { 548 // args_to_use will accumulate outgoing args for the ISD::CALL case in 549 // SelectExpr to use to put the arguments in the appropriate registers. 550 std::vector<SDOperand> args_to_use; 551 552 // Count how many bytes are to be pushed on the stack, including the linkage 553 // area, and parameter passing area. 554 unsigned NumBytes = 24; 555 556 if (Args.empty()) { 557 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain, 558 DAG.getConstant(NumBytes, getPointerTy())); 559 } else { 560 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 561 switch (getValueType(Args[i].second)) { 562 default: assert(0 && "Unknown value type!"); 563 case MVT::i1: 564 case MVT::i8: 565 case MVT::i16: 566 case MVT::i32: 567 case MVT::f32: 568 NumBytes += 4; 569 break; 570 case MVT::i64: 571 case MVT::f64: 572 NumBytes += 8; 573 break; 574 } 575 } 576 577 // Just to be safe, we'll always reserve the full 24 bytes of linkage area 578 // plus 32 bytes of argument space in case any called code gets funky on us. 579 // (Required by ABI to support var arg) 580 if (NumBytes < 56) NumBytes = 56; 581 582 // Adjust the stack pointer for the new arguments... 583 // These operations are automatically eliminated by the prolog/epilog pass 584 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain, 585 DAG.getConstant(NumBytes, getPointerTy())); 586 587 // Set up a copy of the stack pointer for use loading and storing any 588 // arguments that may not fit in the registers available for argument 589 // passing. 590 SDOperand StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(), 591 PPC::R1, MVT::i32); 592 593 // Figure out which arguments are going to go in registers, and which in 594 // memory. Also, if this is a vararg function, floating point operations 595 // must be stored to our stack, and loaded into integer regs as well, if 596 // any integer regs are available for argument passing. 597 unsigned ArgOffset = 24; 598 unsigned GPR_remaining = 8; 599 unsigned FPR_remaining = 13; 600 601 std::vector<SDOperand> MemOps; 602 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 603 // PtrOff will be used to store the current argument to the stack if a 604 // register cannot be found for it. 605 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); 606 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 607 MVT::ValueType ArgVT = getValueType(Args[i].second); 608 609 switch (ArgVT) { 610 default: assert(0 && "Unexpected ValueType for argument!"); 611 case MVT::i1: 612 case MVT::i8: 613 case MVT::i16: 614 // Promote the integer to 32 bits. If the input type is signed use a 615 // sign extend, otherwise use a zero extend. 616 if (Args[i].second->isSigned()) 617 Args[i].first =DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Args[i].first); 618 else 619 Args[i].first =DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Args[i].first); 620 // FALL THROUGH 621 case MVT::i32: 622 if (GPR_remaining > 0) { 623 args_to_use.push_back(Args[i].first); 624 --GPR_remaining; 625 } else { 626 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 627 Args[i].first, PtrOff, 628 DAG.getSrcValue(NULL))); 629 } 630 ArgOffset += 4; 631 break; 632 case MVT::i64: 633 // If we have one free GPR left, we can place the upper half of the i64 634 // in it, and store the other half to the stack. If we have two or more 635 // free GPRs, then we can pass both halves of the i64 in registers. 636 if (GPR_remaining > 0) { 637 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, 638 Args[i].first, DAG.getConstant(1, MVT::i32)); 639 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, 640 Args[i].first, DAG.getConstant(0, MVT::i32)); 641 args_to_use.push_back(Hi); 642 --GPR_remaining; 643 if (GPR_remaining > 0) { 644 args_to_use.push_back(Lo); 645 --GPR_remaining; 646 } else { 647 SDOperand ConstFour = DAG.getConstant(4, getPointerTy()); 648 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour); 649 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 650 Lo, PtrOff, DAG.getSrcValue(NULL))); 651 } 652 } else { 653 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 654 Args[i].first, PtrOff, 655 DAG.getSrcValue(NULL))); 656 } 657 ArgOffset += 8; 658 break; 659 case MVT::f32: 660 case MVT::f64: 661 if (FPR_remaining > 0) { 662 args_to_use.push_back(Args[i].first); 663 --FPR_remaining; 664 if (isVarArg) { 665 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain, 666 Args[i].first, PtrOff, 667 DAG.getSrcValue(NULL)); 668 MemOps.push_back(Store); 669 // Float varargs are always shadowed in available integer registers 670 if (GPR_remaining > 0) { 671 SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff, 672 DAG.getSrcValue(NULL)); 673 MemOps.push_back(Load); 674 args_to_use.push_back(Load); 675 --GPR_remaining; 676 } 677 if (GPR_remaining > 0 && MVT::f64 == ArgVT) { 678 SDOperand ConstFour = DAG.getConstant(4, getPointerTy()); 679 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour); 680 SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff, 681 DAG.getSrcValue(NULL)); 682 MemOps.push_back(Load); 683 args_to_use.push_back(Load); 684 --GPR_remaining; 685 } 686 } else { 687 // If we have any FPRs remaining, we may also have GPRs remaining. 688 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available 689 // GPRs. 690 if (GPR_remaining > 0) { 691 args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32)); 692 --GPR_remaining; 693 } 694 if (GPR_remaining > 0 && MVT::f64 == ArgVT) { 695 args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32)); 696 --GPR_remaining; 697 } 698 } 699 } else { 700 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 701 Args[i].first, PtrOff, 702 DAG.getSrcValue(NULL))); 703 } 704 ArgOffset += (ArgVT == MVT::f32) ? 4 : 8; 705 break; 706 } 707 } 708 if (!MemOps.empty()) 709 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps); 710 } 711 712 std::vector<MVT::ValueType> RetVals; 713 MVT::ValueType RetTyVT = getValueType(RetTy); 714 MVT::ValueType ActualRetTyVT = RetTyVT; 715 if (RetTyVT >= MVT::i1 && RetTyVT <= MVT::i16) 716 ActualRetTyVT = MVT::i32; // Promote result to i32. 717 718 if (RetTyVT != MVT::isVoid) 719 RetVals.push_back(ActualRetTyVT); 720 RetVals.push_back(MVT::Other); 721 722 // If the callee is a GlobalAddress node (quite common, every direct call is) 723 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 724 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 725 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32); 726 727 SDOperand TheCall = SDOperand(DAG.getCall(RetVals, 728 Chain, Callee, args_to_use), 0); 729 Chain = TheCall.getValue(RetTyVT != MVT::isVoid); 730 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain, 731 DAG.getConstant(NumBytes, getPointerTy())); 732 SDOperand RetVal = TheCall; 733 734 // If the result is a small value, add a note so that we keep track of the 735 // information about whether it is sign or zero extended. 736 if (RetTyVT != ActualRetTyVT) { 737 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext : ISD::AssertZext, 738 MVT::i32, RetVal, DAG.getValueType(RetTyVT)); 739 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal); 740 } 741 742 return std::make_pair(RetVal, Chain); 743} 744 745SDOperand PPCTargetLowering::LowerReturnTo(SDOperand Chain, SDOperand Op, 746 SelectionDAG &DAG) { 747 if (Op.getValueType() == MVT::i64) { 748 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op, 749 DAG.getConstant(1, MVT::i32)); 750 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op, 751 DAG.getConstant(0, MVT::i32)); 752 return DAG.getNode(ISD::RET, MVT::Other, Chain, Lo, Hi); 753 } else { 754 return DAG.getNode(ISD::RET, MVT::Other, Chain, Op); 755 } 756} 757 758SDOperand PPCTargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP, 759 Value *VAListV, SelectionDAG &DAG) { 760 // vastart just stores the address of the VarArgsFrameIndex slot into the 761 // memory location argument. 762 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32); 763 return DAG.getNode(ISD::STORE, MVT::Other, Chain, FR, VAListP, 764 DAG.getSrcValue(VAListV)); 765} 766 767std::pair<SDOperand,SDOperand> 768PPCTargetLowering::LowerVAArg(SDOperand Chain, 769 SDOperand VAListP, Value *VAListV, 770 const Type *ArgTy, SelectionDAG &DAG) { 771 MVT::ValueType ArgVT = getValueType(ArgTy); 772 773 SDOperand VAList = 774 DAG.getLoad(MVT::i32, Chain, VAListP, DAG.getSrcValue(VAListV)); 775 SDOperand Result = DAG.getLoad(ArgVT, Chain, VAList, DAG.getSrcValue(NULL)); 776 unsigned Amt; 777 if (ArgVT == MVT::i32 || ArgVT == MVT::f32) 778 Amt = 4; 779 else { 780 assert((ArgVT == MVT::i64 || ArgVT == MVT::f64) && 781 "Other types should have been promoted for varargs!"); 782 Amt = 8; 783 } 784 VAList = DAG.getNode(ISD::ADD, VAList.getValueType(), VAList, 785 DAG.getConstant(Amt, VAList.getValueType())); 786 Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain, 787 VAList, VAListP, DAG.getSrcValue(VAListV)); 788 return std::make_pair(Result, Chain); 789} 790 791 792std::pair<SDOperand, SDOperand> PPCTargetLowering:: 793LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth, 794 SelectionDAG &DAG) { 795 assert(0 && "LowerFrameReturnAddress unimplemented"); 796 abort(); 797} 798 799MachineBasicBlock * 800PPCTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, 801 MachineBasicBlock *BB) { 802 assert((MI->getOpcode() == PPC::SELECT_CC_Int || 803 MI->getOpcode() == PPC::SELECT_CC_F4 || 804 MI->getOpcode() == PPC::SELECT_CC_F8) && 805 "Unexpected instr type to insert"); 806 807 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond 808 // control-flow pattern. The incoming instruction knows the destination vreg 809 // to set, the condition code register to branch on, the true/false values to 810 // select between, and a branch opcode to use. 811 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 812 ilist<MachineBasicBlock>::iterator It = BB; 813 ++It; 814 815 // thisMBB: 816 // ... 817 // TrueVal = ... 818 // cmpTY ccX, r1, r2 819 // bCC copy1MBB 820 // fallthrough --> copy0MBB 821 MachineBasicBlock *thisMBB = BB; 822 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); 823 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); 824 BuildMI(BB, MI->getOperand(4).getImmedValue(), 2) 825 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB); 826 MachineFunction *F = BB->getParent(); 827 F->getBasicBlockList().insert(It, copy0MBB); 828 F->getBasicBlockList().insert(It, sinkMBB); 829 // Update machine-CFG edges 830 BB->addSuccessor(copy0MBB); 831 BB->addSuccessor(sinkMBB); 832 833 // copy0MBB: 834 // %FalseValue = ... 835 // # fallthrough to sinkMBB 836 BB = copy0MBB; 837 838 // Update machine-CFG edges 839 BB->addSuccessor(sinkMBB); 840 841 // sinkMBB: 842 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 843 // ... 844 BB = sinkMBB; 845 BuildMI(BB, PPC::PHI, 4, MI->getOperand(0).getReg()) 846 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB) 847 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 848 849 delete MI; // The pseudo instruction is gone now. 850 return BB; 851} 852 853