PPCISelLowering.cpp revision da6d20f0c15205923cb2c3ef4bf9b5d77de88881
1//===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Chris Lattner and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the PPCISelLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "PPCISelLowering.h" 15#include "PPCTargetMachine.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/CodeGen/MachineFunction.h" 18#include "llvm/CodeGen/MachineInstrBuilder.h" 19#include "llvm/CodeGen/SelectionDAG.h" 20#include "llvm/CodeGen/SSARegMap.h" 21#include "llvm/Constants.h" 22#include "llvm/Function.h" 23using namespace llvm; 24 25PPCTargetLowering::PPCTargetLowering(TargetMachine &TM) 26 : TargetLowering(TM) { 27 28 // Fold away setcc operations if possible. 29 setSetCCIsExpensive(); 30 setPow2DivIsCheap(); 31 32 // Use _setjmp/_longjmp instead of setjmp/longjmp. 33 setUseUnderscoreSetJmpLongJmp(true); 34 35 // Set up the register classes. 36 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass); 37 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass); 38 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass); 39 40 // PowerPC has no intrinsics for these particular operations 41 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand); 42 setOperationAction(ISD::MEMSET, MVT::Other, Expand); 43 setOperationAction(ISD::MEMCPY, MVT::Other, Expand); 44 45 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD 46 setOperationAction(ISD::SEXTLOAD, MVT::i1, Expand); 47 setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand); 48 49 // PowerPC has no SREM/UREM instructions 50 setOperationAction(ISD::SREM, MVT::i32, Expand); 51 setOperationAction(ISD::UREM, MVT::i32, Expand); 52 53 // We don't support sin/cos/sqrt/fmod 54 setOperationAction(ISD::FSIN , MVT::f64, Expand); 55 setOperationAction(ISD::FCOS , MVT::f64, Expand); 56 setOperationAction(ISD::FREM , MVT::f64, Expand); 57 setOperationAction(ISD::FSIN , MVT::f32, Expand); 58 setOperationAction(ISD::FCOS , MVT::f32, Expand); 59 setOperationAction(ISD::FREM , MVT::f32, Expand); 60 61 // If we're enabling GP optimizations, use hardware square root 62 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) { 63 setOperationAction(ISD::FSQRT, MVT::f64, Expand); 64 setOperationAction(ISD::FSQRT, MVT::f32, Expand); 65 } 66 67 // PowerPC does not have CTPOP or CTTZ 68 setOperationAction(ISD::CTPOP, MVT::i32 , Expand); 69 setOperationAction(ISD::CTTZ , MVT::i32 , Expand); 70 71 // PowerPC does not have Select 72 setOperationAction(ISD::SELECT, MVT::i32, Expand); 73 setOperationAction(ISD::SELECT, MVT::f32, Expand); 74 setOperationAction(ISD::SELECT, MVT::f64, Expand); 75 76 // PowerPC wants to turn select_cc of FP into fsel when possible. 77 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 78 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 79 80 // PowerPC does not have BRCOND* which requires SetCC 81 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 82 setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand); 83 84 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores. 85 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 86 87 // PowerPC does not have [U|S]INT_TO_FP 88 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); 89 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 90 91 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand); 92 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand); 93 94 // PowerPC does not have truncstore for i1. 95 setOperationAction(ISD::TRUNCSTORE, MVT::i1, Promote); 96 97 // Support label based line numbers. 98 setOperationAction(ISD::LOCATION, MVT::Other, Expand); 99 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 100 // FIXME - use subtarget debug flags 101 if (!TM.getSubtarget<PPCSubtarget>().isDarwin()) 102 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand); 103 104 // We want to legalize GlobalAddress and ConstantPool nodes into the 105 // appropriate instructions to materialize the address. 106 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 107 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 108 109 if (TM.getSubtarget<PPCSubtarget>().is64Bit()) { 110 // They also have instructions for converting between i64 and fp. 111 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); 112 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); 113 // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT 114 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote); 115 } else { 116 // PowerPC does not have FP_TO_UINT on 32-bit implementations. 117 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 118 } 119 120 if (TM.getSubtarget<PPCSubtarget>().has64BitRegs()) { 121 // 64 bit PowerPC implementations can support i64 types directly 122 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass); 123 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or 124 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand); 125 } else { 126 // 32 bit PowerPC wants to expand i64 shifts itself. 127 setOperationAction(ISD::SHL, MVT::i64, Custom); 128 setOperationAction(ISD::SRL, MVT::i64, Custom); 129 setOperationAction(ISD::SRA, MVT::i64, Custom); 130 } 131 132 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) { 133 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass); 134 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass); 135 } 136 137 setSetCCResultContents(ZeroOrOneSetCCResult); 138 139 computeRegisterProperties(); 140} 141 142const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const { 143 switch (Opcode) { 144 default: return 0; 145 case PPCISD::FSEL: return "PPCISD::FSEL"; 146 case PPCISD::FCFID: return "PPCISD::FCFID"; 147 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ"; 148 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ"; 149 case PPCISD::VMADDFP: return "PPCISD::VMADDFP"; 150 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP"; 151 case PPCISD::Hi: return "PPCISD::Hi"; 152 case PPCISD::Lo: return "PPCISD::Lo"; 153 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg"; 154 case PPCISD::SRL: return "PPCISD::SRL"; 155 case PPCISD::SRA: return "PPCISD::SRA"; 156 case PPCISD::SHL: return "PPCISD::SHL"; 157 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG"; 158 } 159} 160 161/// isFloatingPointZero - Return true if this is 0.0 or -0.0. 162static bool isFloatingPointZero(SDOperand Op) { 163 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) 164 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0); 165 else if (Op.getOpcode() == ISD::EXTLOAD || Op.getOpcode() == ISD::LOAD) { 166 // Maybe this has already been legalized into the constant pool? 167 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1))) 168 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->get())) 169 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0); 170 } 171 return false; 172} 173 174/// LowerOperation - Provide custom lowering hooks for some operations. 175/// 176SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { 177 switch (Op.getOpcode()) { 178 default: assert(0 && "Wasn't expecting to be able to lower this!"); 179 case ISD::FP_TO_SINT: { 180 assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType())); 181 SDOperand Src = Op.getOperand(0); 182 if (Src.getValueType() == MVT::f32) 183 Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src); 184 185 SDOperand Tmp; 186 switch (Op.getValueType()) { 187 default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!"); 188 case MVT::i32: 189 Tmp = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src); 190 break; 191 case MVT::i64: 192 Tmp = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src); 193 break; 194 } 195 196 // Convert the FP value to an int value through memory. 197 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Tmp); 198 if (Op.getValueType() == MVT::i32) 199 Bits = DAG.getNode(ISD::TRUNCATE, MVT::i32, Bits); 200 return Bits; 201 } 202 case ISD::SINT_TO_FP: { 203 assert(MVT::i64 == Op.getOperand(0).getValueType() && 204 "Unhandled SINT_TO_FP type in custom expander!"); 205 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0)); 206 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits); 207 if (MVT::f32 == Op.getValueType()) 208 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP); 209 return FP; 210 } 211 case ISD::SELECT_CC: { 212 // Turn FP only select_cc's into fsel instructions. 213 if (!MVT::isFloatingPoint(Op.getOperand(0).getValueType()) || 214 !MVT::isFloatingPoint(Op.getOperand(2).getValueType())) 215 break; 216 217 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 218 219 // Cannot handle SETEQ/SETNE. 220 if (CC == ISD::SETEQ || CC == ISD::SETNE) break; 221 222 MVT::ValueType ResVT = Op.getValueType(); 223 MVT::ValueType CmpVT = Op.getOperand(0).getValueType(); 224 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); 225 SDOperand TV = Op.getOperand(2), FV = Op.getOperand(3); 226 227 // If the RHS of the comparison is a 0.0, we don't need to do the 228 // subtraction at all. 229 if (isFloatingPointZero(RHS)) 230 switch (CC) { 231 default: assert(0 && "Invalid FSEL condition"); abort(); 232 case ISD::SETULT: 233 case ISD::SETLT: 234 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 235 case ISD::SETUGE: 236 case ISD::SETGE: 237 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 238 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS); 239 return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV); 240 case ISD::SETUGT: 241 case ISD::SETGT: 242 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 243 case ISD::SETULE: 244 case ISD::SETLE: 245 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 246 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS); 247 return DAG.getNode(PPCISD::FSEL, ResVT, 248 DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV); 249 } 250 251 SDOperand Cmp; 252 switch (CC) { 253 default: assert(0 && "Invalid FSEL condition"); abort(); 254 case ISD::SETULT: 255 case ISD::SETLT: 256 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS); 257 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 258 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 259 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV); 260 case ISD::SETUGE: 261 case ISD::SETGE: 262 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS); 263 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 264 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 265 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV); 266 case ISD::SETUGT: 267 case ISD::SETGT: 268 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS); 269 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 270 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 271 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV); 272 case ISD::SETULE: 273 case ISD::SETLE: 274 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS); 275 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 276 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 277 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV); 278 } 279 break; 280 } 281 case ISD::SHL: { 282 assert(Op.getValueType() == MVT::i64 && 283 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!"); 284 // The generic code does a fine job expanding shift by a constant. 285 if (isa<ConstantSDNode>(Op.getOperand(1))) break; 286 287 // Otherwise, expand into a bunch of logical ops. Note that these ops 288 // depend on the PPC behavior for oversized shift amounts. 289 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), 290 DAG.getConstant(0, MVT::i32)); 291 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), 292 DAG.getConstant(1, MVT::i32)); 293 SDOperand Amt = Op.getOperand(1); 294 295 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32, 296 DAG.getConstant(32, MVT::i32), Amt); 297 SDOperand Tmp2 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Amt); 298 SDOperand Tmp3 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Tmp1); 299 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3); 300 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt, 301 DAG.getConstant(-32U, MVT::i32)); 302 SDOperand Tmp6 = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Tmp5); 303 SDOperand OutHi = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6); 304 SDOperand OutLo = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Amt); 305 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi); 306 } 307 case ISD::SRL: { 308 assert(Op.getValueType() == MVT::i64 && 309 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!"); 310 // The generic code does a fine job expanding shift by a constant. 311 if (isa<ConstantSDNode>(Op.getOperand(1))) break; 312 313 // Otherwise, expand into a bunch of logical ops. Note that these ops 314 // depend on the PPC behavior for oversized shift amounts. 315 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), 316 DAG.getConstant(0, MVT::i32)); 317 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), 318 DAG.getConstant(1, MVT::i32)); 319 SDOperand Amt = Op.getOperand(1); 320 321 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32, 322 DAG.getConstant(32, MVT::i32), Amt); 323 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt); 324 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1); 325 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3); 326 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt, 327 DAG.getConstant(-32U, MVT::i32)); 328 SDOperand Tmp6 = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Tmp5); 329 SDOperand OutLo = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6); 330 SDOperand OutHi = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Amt); 331 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi); 332 } 333 case ISD::SRA: { 334 assert(Op.getValueType() == MVT::i64 && 335 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRA!"); 336 // The generic code does a fine job expanding shift by a constant. 337 if (isa<ConstantSDNode>(Op.getOperand(1))) break; 338 339 // Otherwise, expand into a bunch of logical ops, followed by a select_cc. 340 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), 341 DAG.getConstant(0, MVT::i32)); 342 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), 343 DAG.getConstant(1, MVT::i32)); 344 SDOperand Amt = Op.getOperand(1); 345 346 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32, 347 DAG.getConstant(32, MVT::i32), Amt); 348 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt); 349 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1); 350 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3); 351 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt, 352 DAG.getConstant(-32U, MVT::i32)); 353 SDOperand Tmp6 = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Tmp5); 354 SDOperand OutHi = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Amt); 355 SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, MVT::i32), 356 Tmp4, Tmp6, ISD::SETLE); 357 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi); 358 } 359 case ISD::ConstantPool: { 360 Constant *C = cast<ConstantPoolSDNode>(Op)->get(); 361 SDOperand CPI = DAG.getTargetConstantPool(C, MVT::i32); 362 SDOperand Zero = DAG.getConstant(0, MVT::i32); 363 364 if (PPCGenerateStaticCode) { 365 // Generate non-pic code that has direct accesses to the constant pool. 366 // The address of the global is just (hi(&g)+lo(&g)). 367 SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, CPI, Zero); 368 SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, CPI, Zero); 369 return DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo); 370 } 371 372 // Only lower ConstantPool on Darwin. 373 if (!getTargetMachine().getSubtarget<PPCSubtarget>().isDarwin()) break; 374 SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, CPI, Zero); 375 if (PICEnabled) { 376 // With PIC, the first instruction is actually "GR+hi(&G)". 377 Hi = DAG.getNode(ISD::ADD, MVT::i32, 378 DAG.getNode(PPCISD::GlobalBaseReg, MVT::i32), Hi); 379 } 380 381 SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, CPI, Zero); 382 Lo = DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo); 383 return Lo; 384 } 385 case ISD::GlobalAddress: { 386 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op); 387 GlobalValue *GV = GSDN->getGlobal(); 388 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32, GSDN->getOffset()); 389 SDOperand Zero = DAG.getConstant(0, MVT::i32); 390 391 if (PPCGenerateStaticCode) { 392 // Generate non-pic code that has direct accesses to globals. 393 // The address of the global is just (hi(&g)+lo(&g)). 394 SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, GA, Zero); 395 SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, GA, Zero); 396 return DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo); 397 } 398 399 // Only lower GlobalAddress on Darwin. 400 if (!getTargetMachine().getSubtarget<PPCSubtarget>().isDarwin()) break; 401 402 SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, GA, Zero); 403 if (PICEnabled) { 404 // With PIC, the first instruction is actually "GR+hi(&G)". 405 Hi = DAG.getNode(ISD::ADD, MVT::i32, 406 DAG.getNode(PPCISD::GlobalBaseReg, MVT::i32), Hi); 407 } 408 409 SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, GA, Zero); 410 Lo = DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo); 411 412 if (!GV->hasWeakLinkage() && !GV->hasLinkOnceLinkage() && !GV->isExternal()) 413 return Lo; 414 415 // If the global is weak or external, we have to go through the lazy 416 // resolution stub. 417 return DAG.getLoad(MVT::i32, DAG.getEntryNode(), Lo, DAG.getSrcValue(0)); 418 } 419 } 420 return SDOperand(); 421} 422 423std::vector<SDOperand> 424PPCTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { 425 // 426 // add beautiful description of PPC stack frame format, or at least some docs 427 // 428 MachineFunction &MF = DAG.getMachineFunction(); 429 MachineFrameInfo *MFI = MF.getFrameInfo(); 430 MachineBasicBlock& BB = MF.front(); 431 SSARegMap *RegMap = MF.getSSARegMap(); 432 std::vector<SDOperand> ArgValues; 433 434 unsigned ArgOffset = 24; 435 unsigned GPR_remaining = 8; 436 unsigned FPR_remaining = 13; 437 unsigned GPR_idx = 0, FPR_idx = 0; 438 static const unsigned GPR[] = { 439 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 440 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 441 }; 442 static const unsigned FPR[] = { 443 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 444 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13 445 }; 446 447 // Add DAG nodes to load the arguments... On entry to a function on PPC, 448 // the arguments start at offset 24, although they are likely to be passed 449 // in registers. 450 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { 451 SDOperand newroot, argt; 452 unsigned ObjSize; 453 bool needsLoad = false; 454 bool ArgLive = !I->use_empty(); 455 MVT::ValueType ObjectVT = getValueType(I->getType()); 456 457 switch (ObjectVT) { 458 default: assert(0 && "Unhandled argument type!"); 459 case MVT::i1: 460 case MVT::i8: 461 case MVT::i16: 462 case MVT::i32: 463 ObjSize = 4; 464 if (!ArgLive) break; 465 if (GPR_remaining > 0) { 466 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass); 467 MF.addLiveIn(GPR[GPR_idx], VReg); 468 argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32); 469 if (ObjectVT != MVT::i32) { 470 unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext 471 : ISD::AssertZext; 472 argt = DAG.getNode(AssertOp, MVT::i32, argt, 473 DAG.getValueType(ObjectVT)); 474 argt = DAG.getNode(ISD::TRUNCATE, ObjectVT, argt); 475 } 476 } else { 477 needsLoad = true; 478 } 479 break; 480 case MVT::i64: 481 ObjSize = 8; 482 if (!ArgLive) break; 483 if (GPR_remaining > 0) { 484 SDOperand argHi, argLo; 485 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass); 486 MF.addLiveIn(GPR[GPR_idx], VReg); 487 argHi = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32); 488 // If we have two or more remaining argument registers, then both halves 489 // of the i64 can be sourced from there. Otherwise, the lower half will 490 // have to come off the stack. This can happen when an i64 is preceded 491 // by 28 bytes of arguments. 492 if (GPR_remaining > 1) { 493 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass); 494 MF.addLiveIn(GPR[GPR_idx+1], VReg); 495 argLo = DAG.getCopyFromReg(argHi, VReg, MVT::i32); 496 } else { 497 int FI = MFI->CreateFixedObject(4, ArgOffset+4); 498 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32); 499 argLo = DAG.getLoad(MVT::i32, DAG.getEntryNode(), FIN, 500 DAG.getSrcValue(NULL)); 501 } 502 // Build the outgoing arg thingy 503 argt = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, argLo, argHi); 504 newroot = argLo; 505 } else { 506 needsLoad = true; 507 } 508 break; 509 case MVT::f32: 510 case MVT::f64: 511 ObjSize = (ObjectVT == MVT::f64) ? 8 : 4; 512 if (!ArgLive) break; 513 if (FPR_remaining > 0) { 514 unsigned VReg; 515 if (ObjectVT == MVT::f32) 516 VReg = RegMap->createVirtualRegister(&PPC::F4RCRegClass); 517 else 518 VReg = RegMap->createVirtualRegister(&PPC::F8RCRegClass); 519 MF.addLiveIn(FPR[FPR_idx], VReg); 520 argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), VReg, ObjectVT); 521 --FPR_remaining; 522 ++FPR_idx; 523 } else { 524 needsLoad = true; 525 } 526 break; 527 } 528 529 // We need to load the argument to a virtual register if we determined above 530 // that we ran out of physical registers of the appropriate type 531 if (needsLoad) { 532 unsigned SubregOffset = 0; 533 if (ObjectVT == MVT::i8 || ObjectVT == MVT::i1) SubregOffset = 3; 534 if (ObjectVT == MVT::i16) SubregOffset = 2; 535 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset); 536 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32); 537 FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN, 538 DAG.getConstant(SubregOffset, MVT::i32)); 539 argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN, 540 DAG.getSrcValue(NULL)); 541 } 542 543 // Every 4 bytes of argument space consumes one of the GPRs available for 544 // argument passing. 545 if (GPR_remaining > 0) { 546 unsigned delta = (GPR_remaining > 1 && ObjSize == 8) ? 2 : 1; 547 GPR_remaining -= delta; 548 GPR_idx += delta; 549 } 550 ArgOffset += ObjSize; 551 if (newroot.Val) 552 DAG.setRoot(newroot.getValue(1)); 553 554 ArgValues.push_back(argt); 555 } 556 557 // If the function takes variable number of arguments, make a frame index for 558 // the start of the first vararg value... for expansion of llvm.va_start. 559 if (F.isVarArg()) { 560 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset); 561 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32); 562 // If this function is vararg, store any remaining integer argument regs 563 // to their spots on the stack so that they may be loaded by deferencing the 564 // result of va_next. 565 std::vector<SDOperand> MemOps; 566 for (; GPR_remaining > 0; --GPR_remaining, ++GPR_idx) { 567 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass); 568 MF.addLiveIn(GPR[GPR_idx], VReg); 569 SDOperand Val = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32); 570 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1), 571 Val, FIN, DAG.getSrcValue(NULL)); 572 MemOps.push_back(Store); 573 // Increment the address by four for the next argument to store 574 SDOperand PtrOff = DAG.getConstant(4, getPointerTy()); 575 FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN, PtrOff); 576 } 577 if (!MemOps.empty()) { 578 MemOps.push_back(DAG.getRoot()); 579 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps)); 580 } 581 } 582 583 // Finally, inform the code generator which regs we return values in. 584 switch (getValueType(F.getReturnType())) { 585 default: assert(0 && "Unknown type!"); 586 case MVT::isVoid: break; 587 case MVT::i1: 588 case MVT::i8: 589 case MVT::i16: 590 case MVT::i32: 591 MF.addLiveOut(PPC::R3); 592 break; 593 case MVT::i64: 594 MF.addLiveOut(PPC::R3); 595 MF.addLiveOut(PPC::R4); 596 break; 597 case MVT::f32: 598 case MVT::f64: 599 MF.addLiveOut(PPC::F1); 600 break; 601 } 602 603 return ArgValues; 604} 605 606std::pair<SDOperand, SDOperand> 607PPCTargetLowering::LowerCallTo(SDOperand Chain, 608 const Type *RetTy, bool isVarArg, 609 unsigned CallingConv, bool isTailCall, 610 SDOperand Callee, ArgListTy &Args, 611 SelectionDAG &DAG) { 612 // args_to_use will accumulate outgoing args for the ISD::CALL case in 613 // SelectExpr to use to put the arguments in the appropriate registers. 614 std::vector<SDOperand> args_to_use; 615 616 // Count how many bytes are to be pushed on the stack, including the linkage 617 // area, and parameter passing area. 618 unsigned NumBytes = 24; 619 620 if (Args.empty()) { 621 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain, 622 DAG.getConstant(NumBytes, getPointerTy())); 623 } else { 624 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 625 switch (getValueType(Args[i].second)) { 626 default: assert(0 && "Unknown value type!"); 627 case MVT::i1: 628 case MVT::i8: 629 case MVT::i16: 630 case MVT::i32: 631 case MVT::f32: 632 NumBytes += 4; 633 break; 634 case MVT::i64: 635 case MVT::f64: 636 NumBytes += 8; 637 break; 638 } 639 } 640 641 // Just to be safe, we'll always reserve the full 24 bytes of linkage area 642 // plus 32 bytes of argument space in case any called code gets funky on us. 643 // (Required by ABI to support var arg) 644 if (NumBytes < 56) NumBytes = 56; 645 646 // Adjust the stack pointer for the new arguments... 647 // These operations are automatically eliminated by the prolog/epilog pass 648 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain, 649 DAG.getConstant(NumBytes, getPointerTy())); 650 651 // Set up a copy of the stack pointer for use loading and storing any 652 // arguments that may not fit in the registers available for argument 653 // passing. 654 SDOperand StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(), 655 PPC::R1, MVT::i32); 656 657 // Figure out which arguments are going to go in registers, and which in 658 // memory. Also, if this is a vararg function, floating point operations 659 // must be stored to our stack, and loaded into integer regs as well, if 660 // any integer regs are available for argument passing. 661 unsigned ArgOffset = 24; 662 unsigned GPR_remaining = 8; 663 unsigned FPR_remaining = 13; 664 665 std::vector<SDOperand> MemOps; 666 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 667 // PtrOff will be used to store the current argument to the stack if a 668 // register cannot be found for it. 669 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); 670 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 671 MVT::ValueType ArgVT = getValueType(Args[i].second); 672 673 switch (ArgVT) { 674 default: assert(0 && "Unexpected ValueType for argument!"); 675 case MVT::i1: 676 case MVT::i8: 677 case MVT::i16: 678 // Promote the integer to 32 bits. If the input type is signed use a 679 // sign extend, otherwise use a zero extend. 680 if (Args[i].second->isSigned()) 681 Args[i].first =DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Args[i].first); 682 else 683 Args[i].first =DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Args[i].first); 684 // FALL THROUGH 685 case MVT::i32: 686 if (GPR_remaining > 0) { 687 args_to_use.push_back(Args[i].first); 688 --GPR_remaining; 689 } else { 690 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 691 Args[i].first, PtrOff, 692 DAG.getSrcValue(NULL))); 693 } 694 ArgOffset += 4; 695 break; 696 case MVT::i64: 697 // If we have one free GPR left, we can place the upper half of the i64 698 // in it, and store the other half to the stack. If we have two or more 699 // free GPRs, then we can pass both halves of the i64 in registers. 700 if (GPR_remaining > 0) { 701 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, 702 Args[i].first, DAG.getConstant(1, MVT::i32)); 703 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, 704 Args[i].first, DAG.getConstant(0, MVT::i32)); 705 args_to_use.push_back(Hi); 706 --GPR_remaining; 707 if (GPR_remaining > 0) { 708 args_to_use.push_back(Lo); 709 --GPR_remaining; 710 } else { 711 SDOperand ConstFour = DAG.getConstant(4, getPointerTy()); 712 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour); 713 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 714 Lo, PtrOff, DAG.getSrcValue(NULL))); 715 } 716 } else { 717 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 718 Args[i].first, PtrOff, 719 DAG.getSrcValue(NULL))); 720 } 721 ArgOffset += 8; 722 break; 723 case MVT::f32: 724 case MVT::f64: 725 if (FPR_remaining > 0) { 726 args_to_use.push_back(Args[i].first); 727 --FPR_remaining; 728 if (isVarArg) { 729 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain, 730 Args[i].first, PtrOff, 731 DAG.getSrcValue(NULL)); 732 MemOps.push_back(Store); 733 // Float varargs are always shadowed in available integer registers 734 if (GPR_remaining > 0) { 735 SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff, 736 DAG.getSrcValue(NULL)); 737 MemOps.push_back(Load.getValue(1)); 738 args_to_use.push_back(Load); 739 --GPR_remaining; 740 } 741 if (GPR_remaining > 0 && MVT::f64 == ArgVT) { 742 SDOperand ConstFour = DAG.getConstant(4, getPointerTy()); 743 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour); 744 SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff, 745 DAG.getSrcValue(NULL)); 746 MemOps.push_back(Load.getValue(1)); 747 args_to_use.push_back(Load); 748 --GPR_remaining; 749 } 750 } else { 751 // If we have any FPRs remaining, we may also have GPRs remaining. 752 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available 753 // GPRs. 754 if (GPR_remaining > 0) { 755 args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32)); 756 --GPR_remaining; 757 } 758 if (GPR_remaining > 0 && MVT::f64 == ArgVT) { 759 args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32)); 760 --GPR_remaining; 761 } 762 } 763 } else { 764 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 765 Args[i].first, PtrOff, 766 DAG.getSrcValue(NULL))); 767 } 768 ArgOffset += (ArgVT == MVT::f32) ? 4 : 8; 769 break; 770 } 771 } 772 if (!MemOps.empty()) 773 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps); 774 } 775 776 std::vector<MVT::ValueType> RetVals; 777 MVT::ValueType RetTyVT = getValueType(RetTy); 778 MVT::ValueType ActualRetTyVT = RetTyVT; 779 if (RetTyVT >= MVT::i1 && RetTyVT <= MVT::i16) 780 ActualRetTyVT = MVT::i32; // Promote result to i32. 781 782 if (RetTyVT != MVT::isVoid) 783 RetVals.push_back(ActualRetTyVT); 784 RetVals.push_back(MVT::Other); 785 786 // If the callee is a GlobalAddress node (quite common, every direct call is) 787 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 788 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 789 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32); 790 791 SDOperand TheCall = SDOperand(DAG.getCall(RetVals, 792 Chain, Callee, args_to_use), 0); 793 Chain = TheCall.getValue(RetTyVT != MVT::isVoid); 794 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain, 795 DAG.getConstant(NumBytes, getPointerTy())); 796 SDOperand RetVal = TheCall; 797 798 // If the result is a small value, add a note so that we keep track of the 799 // information about whether it is sign or zero extended. 800 if (RetTyVT != ActualRetTyVT) { 801 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext : ISD::AssertZext, 802 MVT::i32, RetVal, DAG.getValueType(RetTyVT)); 803 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal); 804 } 805 806 return std::make_pair(RetVal, Chain); 807} 808 809SDOperand PPCTargetLowering::LowerReturnTo(SDOperand Chain, SDOperand Op, 810 SelectionDAG &DAG) { 811 SDOperand Copy; 812 switch (Op.getValueType()) { 813 default: assert(0 && "Unknown type to return!"); 814 case MVT::i32: 815 Copy = DAG.getCopyToReg(Chain, PPC::R3, Op, SDOperand()); 816 break; 817 case MVT::f32: 818 case MVT::f64: 819 Copy = DAG.getCopyToReg(Chain, PPC::F1, Op, SDOperand()); 820 break; 821 case MVT::i64: 822 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op, 823 DAG.getConstant(1, MVT::i32)); 824 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op, 825 DAG.getConstant(0, MVT::i32)); 826 Copy = DAG.getCopyToReg(Chain, PPC::R3, Hi, SDOperand()); 827 Copy = DAG.getCopyToReg(Copy, PPC::R4, Lo, Copy.getValue(1)); 828 break; 829 } 830 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1)); 831} 832 833SDOperand PPCTargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP, 834 Value *VAListV, SelectionDAG &DAG) { 835 // vastart just stores the address of the VarArgsFrameIndex slot into the 836 // memory location argument. 837 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32); 838 return DAG.getNode(ISD::STORE, MVT::Other, Chain, FR, VAListP, 839 DAG.getSrcValue(VAListV)); 840} 841 842std::pair<SDOperand,SDOperand> 843PPCTargetLowering::LowerVAArg(SDOperand Chain, 844 SDOperand VAListP, Value *VAListV, 845 const Type *ArgTy, SelectionDAG &DAG) { 846 MVT::ValueType ArgVT = getValueType(ArgTy); 847 848 SDOperand VAList = 849 DAG.getLoad(MVT::i32, Chain, VAListP, DAG.getSrcValue(VAListV)); 850 SDOperand Result = DAG.getLoad(ArgVT, Chain, VAList, DAG.getSrcValue(NULL)); 851 unsigned Amt; 852 if (ArgVT == MVT::i32 || ArgVT == MVT::f32) 853 Amt = 4; 854 else { 855 assert((ArgVT == MVT::i64 || ArgVT == MVT::f64) && 856 "Other types should have been promoted for varargs!"); 857 Amt = 8; 858 } 859 VAList = DAG.getNode(ISD::ADD, VAList.getValueType(), VAList, 860 DAG.getConstant(Amt, VAList.getValueType())); 861 Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain, 862 VAList, VAListP, DAG.getSrcValue(VAListV)); 863 return std::make_pair(Result, Chain); 864} 865 866 867std::pair<SDOperand, SDOperand> PPCTargetLowering:: 868LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth, 869 SelectionDAG &DAG) { 870 assert(0 && "LowerFrameReturnAddress unimplemented"); 871 abort(); 872} 873 874MachineBasicBlock * 875PPCTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, 876 MachineBasicBlock *BB) { 877 assert((MI->getOpcode() == PPC::SELECT_CC_Int || 878 MI->getOpcode() == PPC::SELECT_CC_F4 || 879 MI->getOpcode() == PPC::SELECT_CC_F8) && 880 "Unexpected instr type to insert"); 881 882 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond 883 // control-flow pattern. The incoming instruction knows the destination vreg 884 // to set, the condition code register to branch on, the true/false values to 885 // select between, and a branch opcode to use. 886 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 887 ilist<MachineBasicBlock>::iterator It = BB; 888 ++It; 889 890 // thisMBB: 891 // ... 892 // TrueVal = ... 893 // cmpTY ccX, r1, r2 894 // bCC copy1MBB 895 // fallthrough --> copy0MBB 896 MachineBasicBlock *thisMBB = BB; 897 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); 898 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); 899 BuildMI(BB, MI->getOperand(4).getImmedValue(), 2) 900 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB); 901 MachineFunction *F = BB->getParent(); 902 F->getBasicBlockList().insert(It, copy0MBB); 903 F->getBasicBlockList().insert(It, sinkMBB); 904 // Update machine-CFG edges 905 BB->addSuccessor(copy0MBB); 906 BB->addSuccessor(sinkMBB); 907 908 // copy0MBB: 909 // %FalseValue = ... 910 // # fallthrough to sinkMBB 911 BB = copy0MBB; 912 913 // Update machine-CFG edges 914 BB->addSuccessor(sinkMBB); 915 916 // sinkMBB: 917 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 918 // ... 919 BB = sinkMBB; 920 BuildMI(BB, PPC::PHI, 4, MI->getOperand(0).getReg()) 921 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB) 922 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 923 924 delete MI; // The pseudo instruction is gone now. 925 return BB; 926} 927 928