X86AsmPrinter.cpp revision 0285a33761b7d6432cc0031fd32a230d48c5a2a3 
1//===-- X86/Printer.cpp - Convert X86 code to human readable rep. ---------===//
2//
3// This file contains a printer that converts from our internal representation
4// of LLVM code to a nice human readable form that is suitable for debuggging.
5//
6//===----------------------------------------------------------------------===//
7
8#include "X86.h"
9#include "X86InstrInfo.h"
10#include "llvm/Function.h"
11#include "llvm/Target/TargetMachine.h"
12#include "llvm/CodeGen/MachineFunctionPass.h"
13#include "llvm/CodeGen/MachineInstr.h"
14#include "Support/Statistic.h"
15
16namespace {
17  struct Printer : public MachineFunctionPass {
18    std::ostream &O;
19
20    Printer(std::ostream &o) : O(o) {}
21
22    virtual const char *getPassName() const {
23      return "X86 Assembly Printer";
24    }
25
26    bool runOnMachineFunction(MachineFunction &F);
27  };
28}
29
30/// createX86CodePrinterPass - Print out the specified machine code function to
31/// the specified stream.  This function should work regardless of whether or
32/// not the function is in SSA form or not.
33///
34Pass *createX86CodePrinterPass(std::ostream &O) {
35  return new Printer(O);
36}
37
38
39/// runOnFunction - This uses the X86InstructionInfo::print method
40/// to print assembly for each instruction.
41bool Printer::runOnMachineFunction(MachineFunction &MF) {
42  static unsigned BBNumber = 0;
43  const TargetMachine &TM = MF.getTarget();
44  const MachineInstrInfo &MII = TM.getInstrInfo();
45
46  // Print out labels for the function.
47  O << "\t.globl\t" << MF.getFunction()->getName() << "\n";
48  O << "\t.type\t" << MF.getFunction()->getName() << ", @function\n";
49  O << MF.getFunction()->getName() << ":\n";
50
51  // Print out code for the function.
52  for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
53       I != E; ++I) {
54    // Print a label for the basic block.
55    O << ".BB" << BBNumber++ << ":\n";
56    for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
57	 II != E; ++II) {
58      // Print the assembly for the instruction.
59      O << "\t";
60      MII.print(*II, O, TM);
61    }
62  }
63
64  // We didn't modify anything.
65  return false;
66}
67
68static bool isScale(const MachineOperand &MO) {
69  return MO.isImmediate() &&
70           (MO.getImmedValue() == 1 || MO.getImmedValue() == 2 ||
71            MO.getImmedValue() == 4 || MO.getImmedValue() == 8);
72}
73
74static bool isMem(const MachineInstr *MI, unsigned Op) {
75  return Op+4 <= MI->getNumOperands() &&
76         MI->getOperand(Op  ).isRegister() &&isScale(MI->getOperand(Op+1)) &&
77         MI->getOperand(Op+2).isRegister() &&MI->getOperand(Op+3).isImmediate();
78}
79
80static void printOp(std::ostream &O, const MachineOperand &MO,
81                    const MRegisterInfo &RI) {
82  switch (MO.getType()) {
83  case MachineOperand::MO_VirtualRegister:
84    if (Value *V = MO.getVRegValueOrNull()) {
85      O << "<" << V->getName() << ">";
86      return;
87    }
88  case MachineOperand::MO_MachineRegister:
89    if (MO.getReg() < MRegisterInfo::FirstVirtualRegister)
90      O << RI.get(MO.getReg()).Name;
91    else
92      O << "%reg" << MO.getReg();
93    return;
94
95  case MachineOperand::MO_SignExtendedImmed:
96  case MachineOperand::MO_UnextendedImmed:
97    O << (int)MO.getImmedValue();
98    return;
99  case MachineOperand::MO_PCRelativeDisp:
100    O << "<" << MO.getVRegValue()->getName() << ">";
101    return;
102  default:
103    O << "<unknown op ty>"; return;
104  }
105}
106
107static const std::string sizePtr(const MachineInstrDescriptor &Desc) {
108  switch (Desc.TSFlags & X86II::ArgMask) {
109    default: assert(0 && "Unknown arg size!");
110    case X86II::Arg8:   return "BYTE PTR";
111    case X86II::Arg16:  return "WORD PTR";
112    case X86II::Arg32:  return "DWORD PTR";
113    case X86II::ArgF32:  return "DWORD PTR";
114    case X86II::ArgF64:  return "QWORD PTR";
115    case X86II::ArgF80:  return "XWORD PTR";
116  }
117}
118
119static void printMemReference(std::ostream &O, const MachineInstr *MI,
120                              unsigned Op, const MRegisterInfo &RI) {
121  assert(isMem(MI, Op) && "Invalid memory reference!");
122  const MachineOperand &BaseReg  = MI->getOperand(Op);
123  int ScaleVal                   = MI->getOperand(Op+1).getImmedValue();
124  const MachineOperand &IndexReg = MI->getOperand(Op+2);
125  int DispVal                    = MI->getOperand(Op+3).getImmedValue();
126
127  O << "[";
128  bool NeedPlus = false;
129  if (BaseReg.getReg()) {
130    printOp(O, BaseReg, RI);
131    NeedPlus = true;
132  }
133
134  if (IndexReg.getReg()) {
135    if (NeedPlus) O << " + ";
136    if (ScaleVal != 1)
137      O << ScaleVal << "*";
138    printOp(O, IndexReg, RI);
139    NeedPlus = true;
140  }
141
142  if (DispVal) {
143    if (NeedPlus)
144      if (DispVal > 0)
145	O << " + ";
146      else {
147	O << " - ";
148	DispVal = -DispVal;
149      }
150    O << DispVal;
151  }
152  O << "]";
153}
154
155// print - Print out an x86 instruction in intel syntax
156void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
157                         const TargetMachine &TM) const {
158  unsigned Opcode = MI->getOpcode();
159  const MachineInstrDescriptor &Desc = get(Opcode);
160
161  switch (Desc.TSFlags & X86II::FormMask) {
162  case X86II::Pseudo:
163    if (Opcode == X86::PHI) {
164      printOp(O, MI->getOperand(0), RI);
165      O << " = phi ";
166      for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
167	if (i != 1) O << ", ";
168	O << "[";
169	printOp(O, MI->getOperand(i), RI);
170	O << ", ";
171	printOp(O, MI->getOperand(i+1), RI);
172	O << "]";
173      }
174    } else {
175      unsigned i = 0;
176      if (MI->getNumOperands() && MI->getOperand(0).opIsDef()) {
177	printOp(O, MI->getOperand(0), RI);
178	O << " = ";
179	++i;
180      }
181      O << getName(MI->getOpcode());
182
183      for (unsigned e = MI->getNumOperands(); i != e; ++i) {
184	O << " ";
185	if (MI->getOperand(i).opIsDef()) O << "*";
186	printOp(O, MI->getOperand(i), RI);
187	if (MI->getOperand(i).opIsDef()) O << "*";
188      }
189    }
190    O << "\n";
191    return;
192
193  case X86II::RawFrm:
194    // The accepted forms of Raw instructions are:
195    //   1. nop     - No operand required
196    //   2. jmp foo - PC relative displacement operand
197    //
198    assert(MI->getNumOperands() == 0 ||
199           (MI->getNumOperands() == 1 && MI->getOperand(0).isPCRelativeDisp())&&
200           "Illegal raw instruction!");
201    O << getName(MI->getOpcode()) << " ";
202
203    if (MI->getNumOperands() == 1) {
204      printOp(O, MI->getOperand(0), RI);
205    }
206    O << "\n";
207    return;
208
209  case X86II::AddRegFrm: {
210    // There are currently two forms of acceptable AddRegFrm instructions.
211    // Either the instruction JUST takes a single register (like inc, dec, etc),
212    // or it takes a register and an immediate of the same size as the register
213    // (move immediate f.e.).  Note that this immediate value might be stored as
214    // an LLVM value, to represent, for example, loading the address of a global
215    // into a register.  The initial register might be duplicated if this is a
216    // M_2_ADDR_REG instruction
217    //
218    assert(MI->getOperand(0).isRegister() &&
219           (MI->getNumOperands() == 1 ||
220            (MI->getNumOperands() == 2 &&
221             (MI->getOperand(1).getVRegValueOrNull() ||
222              MI->getOperand(1).isImmediate() ||
223	      MI->getOperand(1).isRegister()))) &&
224           "Illegal form for AddRegFrm instruction!");
225
226    unsigned Reg = MI->getOperand(0).getReg();
227
228    O << getName(MI->getOpCode()) << " ";
229    printOp(O, MI->getOperand(0), RI);
230    if (MI->getNumOperands() == 2 && !MI->getOperand(1).isRegister()) {
231      O << ", ";
232      printOp(O, MI->getOperand(1), RI);
233    }
234    O << "\n";
235    return;
236  }
237  case X86II::MRMDestReg: {
238    // There are two acceptable forms of MRMDestReg instructions, those with 3
239    // and 2 operands:
240    //
241    // 3 Operands: in this form, the first two registers (the destination, and
242    // the first operand) should be the same, post register allocation.  The 3rd
243    // operand is an additional input.  This should be for things like add
244    // instructions.
245    //
246    // 2 Operands: this is for things like mov that do not read a second input
247    //
248    assert(MI->getOperand(0).isRegister() &&
249           (MI->getNumOperands() == 2 ||
250            (MI->getNumOperands() == 3 && MI->getOperand(1).isRegister())) &&
251           MI->getOperand(MI->getNumOperands()-1).isRegister()
252           && "Bad format for MRMDestReg!");
253    if (MI->getNumOperands() == 3 &&
254        MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
255      O << "**";
256
257    O << getName(MI->getOpCode()) << " ";
258    printOp(O, MI->getOperand(0), RI);
259    O << ", ";
260    printOp(O, MI->getOperand(MI->getNumOperands()-1), RI);
261    O << "\n";
262    return;
263  }
264
265  case X86II::MRMDestMem: {
266    // These instructions are the same as MRMDestReg, but instead of having a
267    // register reference for the mod/rm field, it's a memory reference.
268    //
269    assert(isMem(MI, 0) && MI->getNumOperands() == 4+1 &&
270           MI->getOperand(4).isRegister() && "Bad format for MRMDestMem!");
271
272    O << getName(MI->getOpCode()) << " " << sizePtr (Desc) << " ";
273    printMemReference(O, MI, 0, RI);
274    O << ", ";
275    printOp(O, MI->getOperand(4), RI);
276    O << "\n";
277    return;
278  }
279
280  case X86II::MRMSrcReg: {
281    // There is a two forms that are acceptable for MRMSrcReg instructions,
282    // those with 3 and 2 operands:
283    //
284    // 3 Operands: in this form, the last register (the second input) is the
285    // ModR/M input.  The first two operands should be the same, post register
286    // allocation.  This is for things like: add r32, r/m32
287    //
288    // 2 Operands: this is for things like mov that do not read a second input
289    //
290    assert(MI->getOperand(0).isRegister() &&
291           MI->getOperand(1).isRegister() &&
292           (MI->getNumOperands() == 2 ||
293            (MI->getNumOperands() == 3 && MI->getOperand(2).isRegister()))
294           && "Bad format for MRMDestReg!");
295    if (MI->getNumOperands() == 3 &&
296        MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
297      O << "**";
298
299    O << getName(MI->getOpCode()) << " ";
300    printOp(O, MI->getOperand(0), RI);
301    O << ", ";
302    printOp(O, MI->getOperand(MI->getNumOperands()-1), RI);
303    O << "\n";
304    return;
305  }
306
307  case X86II::MRMSrcMem: {
308    // These instructions are the same as MRMSrcReg, but instead of having a
309    // register reference for the mod/rm field, it's a memory reference.
310    //
311    assert(MI->getOperand(0).isRegister() &&
312           (MI->getNumOperands() == 1+4 && isMem(MI, 1)) ||
313           (MI->getNumOperands() == 2+4 && MI->getOperand(1).isRegister() &&
314            isMem(MI, 2))
315           && "Bad format for MRMDestReg!");
316    if (MI->getNumOperands() == 2+4 &&
317        MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
318      O << "**";
319
320    O << getName(MI->getOpCode()) << " ";
321    printOp(O, MI->getOperand(0), RI);
322    O << ", " << sizePtr (Desc) << " ";
323    printMemReference(O, MI, MI->getNumOperands()-4, RI);
324    O << "\n";
325    return;
326  }
327
328  case X86II::MRMS0r: case X86II::MRMS1r:
329  case X86II::MRMS2r: case X86II::MRMS3r:
330  case X86II::MRMS4r: case X86II::MRMS5r:
331  case X86II::MRMS6r: case X86II::MRMS7r: {
332    // In this form, the following are valid formats:
333    //  1. sete r
334    //  2. cmp reg, immediate
335    //  2. shl rdest, rinput  <implicit CL or 1>
336    //  3. sbb rdest, rinput, immediate   [rdest = rinput]
337    //
338    assert(MI->getNumOperands() > 0 && MI->getNumOperands() < 4 &&
339           MI->getOperand(0).isRegister() && "Bad MRMSxR format!");
340    assert((MI->getNumOperands() != 2 ||
341            MI->getOperand(1).isRegister() || MI->getOperand(1).isImmediate())&&
342           "Bad MRMSxR format!");
343    assert((MI->getNumOperands() < 3 ||
344        (MI->getOperand(1).isRegister() && MI->getOperand(2).isImmediate())) &&
345           "Bad MRMSxR format!");
346
347    if (MI->getNumOperands() > 1 && MI->getOperand(1).isRegister() &&
348        MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
349      O << "**";
350
351    O << getName(MI->getOpCode()) << " ";
352    printOp(O, MI->getOperand(0), RI);
353    if (MI->getOperand(MI->getNumOperands()-1).isImmediate()) {
354      O << ", ";
355      printOp(O, MI->getOperand(MI->getNumOperands()-1), RI);
356    }
357    O << "\n";
358
359    return;
360  }
361
362  default:
363    O << "\t\t\t-"; MI->print(O, TM); break;
364  }
365}
366