X86AsmPrinter.cpp revision 3e119c68fe9aa1cbd93f186747961a6ece1a0c5a
1//===-- X86/Printer.cpp - Convert X86 LLVM code to Intel assembly ---------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains a printer that converts from our internal 11// representation of machine-dependent LLVM code to Intel-format 12// assembly language. This printer is the output mechanism used 13// by `llc' and `lli -print-machineinstrs' on X86. 14// 15//===----------------------------------------------------------------------===// 16 17#include "X86.h" 18#include "X86InstrInfo.h" 19#include "llvm/Constants.h" 20#include "llvm/DerivedTypes.h" 21#include "llvm/Module.h" 22#include "llvm/Assembly/Writer.h" 23#include "llvm/CodeGen/MachineFunctionPass.h" 24#include "llvm/CodeGen/MachineConstantPool.h" 25#include "llvm/CodeGen/MachineInstr.h" 26#include "llvm/Target/TargetMachine.h" 27#include "llvm/Support/Mangler.h" 28#include "Support/Statistic.h" 29#include "Support/StringExtras.h" 30#include "Support/CommandLine.h" 31 32namespace { 33 Statistic<> EmittedInsts("asm-printer", "Number of machine instrs printed"); 34 35 // FIXME: This should be automatically picked up by autoconf from the C 36 // frontend 37 cl::opt<bool> EmitCygwin("enable-cygwin-compatible-output", cl::Hidden, 38 cl::desc("Emit X86 assembly code suitable for consumption by cygwin")); 39 40 struct Printer : public MachineFunctionPass { 41 /// Output stream on which we're printing assembly code. 42 /// 43 std::ostream &O; 44 45 /// Target machine description which we query for reg. names, data 46 /// layout, etc. 47 /// 48 TargetMachine &TM; 49 50 /// Name-mangler for global names. 51 /// 52 Mangler *Mang; 53 54 Printer(std::ostream &o, TargetMachine &tm) : O(o), TM(tm) { } 55 56 /// We name each basic block in a Function with a unique number, so 57 /// that we can consistently refer to them later. This is cleared 58 /// at the beginning of each call to runOnMachineFunction(). 59 /// 60 typedef std::map<const Value *, unsigned> ValueMapTy; 61 ValueMapTy NumberForBB; 62 63 /// Cache of mangled name for current function. This is 64 /// recalculated at the beginning of each call to 65 /// runOnMachineFunction(). 66 /// 67 std::string CurrentFnName; 68 69 virtual const char *getPassName() const { 70 return "X86 Assembly Printer"; 71 } 72 73 void checkImplUses (const TargetInstrDescriptor &Desc); 74 void printMachineInstruction(const MachineInstr *MI); 75 void printOp(const MachineOperand &MO, 76 bool elideOffsetKeyword = false); 77 void printMemReference(const MachineInstr *MI, unsigned Op); 78 void printConstantPool(MachineConstantPool *MCP); 79 bool runOnMachineFunction(MachineFunction &F); 80 std::string ConstantExprToString(const ConstantExpr* CE); 81 std::string valToExprString(const Value* V); 82 bool doInitialization(Module &M); 83 bool doFinalization(Module &M); 84 void printConstantValueOnly(const Constant* CV); 85 }; 86} // end of anonymous namespace 87 88/// createX86CodePrinterPass - Returns a pass that prints the X86 89/// assembly code for a MachineFunction to the given output stream, 90/// using the given target machine description. This should work 91/// regardless of whether the function is in SSA form. 92/// 93FunctionPass *createX86CodePrinterPass(std::ostream &o,TargetMachine &tm){ 94 return new Printer(o, tm); 95} 96 97/// valToExprString - Helper function for ConstantExprToString(). 98/// Appends result to argument string S. 99/// 100std::string Printer::valToExprString(const Value* V) { 101 std::string S; 102 bool failed = false; 103 if (const Constant* CV = dyn_cast<Constant>(V)) { // symbolic or known 104 if (const ConstantBool *CB = dyn_cast<ConstantBool>(CV)) 105 S += std::string(CB == ConstantBool::True ? "1" : "0"); 106 else if (const ConstantSInt *CI = dyn_cast<ConstantSInt>(CV)) 107 S += itostr(CI->getValue()); 108 else if (const ConstantUInt *CI = dyn_cast<ConstantUInt>(CV)) 109 S += utostr(CI->getValue()); 110 else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) 111 S += ftostr(CFP->getValue()); 112 else if (isa<ConstantPointerNull>(CV)) 113 S += "0"; 114 else if (const ConstantPointerRef *CPR = dyn_cast<ConstantPointerRef>(CV)) 115 S += valToExprString(CPR->getValue()); 116 else if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(CV)) 117 S += ConstantExprToString(CE); 118 else 119 failed = true; 120 } else if (const GlobalValue* GV = dyn_cast<GlobalValue>(V)) { 121 S += Mang->getValueName(GV); 122 } 123 else 124 failed = true; 125 126 if (failed) { 127 assert(0 && "Cannot convert value to string"); 128 S += "<illegal-value>"; 129 } 130 return S; 131} 132 133/// ConstantExprToString - Convert a ConstantExpr to an asm expression 134/// and return this as a string. 135/// 136std::string Printer::ConstantExprToString(const ConstantExpr* CE) { 137 const TargetData &TD = TM.getTargetData(); 138 switch(CE->getOpcode()) { 139 case Instruction::GetElementPtr: 140 { // generate a symbolic expression for the byte address 141 const Value* ptrVal = CE->getOperand(0); 142 std::vector<Value*> idxVec(CE->op_begin()+1, CE->op_end()); 143 if (unsigned Offset = TD.getIndexedOffset(ptrVal->getType(), idxVec)) 144 return "(" + valToExprString(ptrVal) + ") + " + utostr(Offset); 145 else 146 return valToExprString(ptrVal); 147 } 148 149 case Instruction::Cast: 150 // Support only non-converting or widening casts for now, that is, 151 // ones that do not involve a change in value. This assertion is 152 // not a complete check. 153 { 154 Constant *Op = CE->getOperand(0); 155 const Type *OpTy = Op->getType(), *Ty = CE->getType(); 156 assert(((isa<PointerType>(OpTy) 157 && (Ty == Type::LongTy || Ty == Type::ULongTy)) 158 || (isa<PointerType>(Ty) 159 && (OpTy == Type::LongTy || OpTy == Type::ULongTy))) 160 || (((TD.getTypeSize(Ty) >= TD.getTypeSize(OpTy)) 161 && (OpTy->isLosslesslyConvertibleTo(Ty)))) 162 && "FIXME: Don't yet support this kind of constant cast expr"); 163 return "(" + valToExprString(Op) + ")"; 164 } 165 166 case Instruction::Add: 167 return "(" + valToExprString(CE->getOperand(0)) + ") + (" 168 + valToExprString(CE->getOperand(1)) + ")"; 169 170 default: 171 assert(0 && "Unsupported operator in ConstantExprToString()"); 172 return ""; 173 } 174} 175 176/// isStringCompatible - Can we treat the specified array as a string? 177/// Only if it is an array of ubytes or non-negative sbytes. 178/// 179static bool isStringCompatible(const ConstantArray *CVA) { 180 const Type *ETy = cast<ArrayType>(CVA->getType())->getElementType(); 181 if (ETy == Type::UByteTy) return true; 182 if (ETy != Type::SByteTy) return false; 183 184 for (unsigned i = 0; i < CVA->getNumOperands(); ++i) 185 if (cast<ConstantSInt>(CVA->getOperand(i))->getValue() < 0) 186 return false; 187 188 return true; 189} 190 191/// toOctal - Convert the low order bits of X into an octal digit. 192/// 193static inline char toOctal(int X) { 194 return (X&7)+'0'; 195} 196 197/// getAsCString - Return the specified array as a C compatible 198/// string, only if the predicate isStringCompatible is true. 199/// 200static std::string getAsCString(const ConstantArray *CVA) { 201 assert(isStringCompatible(CVA) && "Array is not string compatible!"); 202 203 std::string Result; 204 const Type *ETy = cast<ArrayType>(CVA->getType())->getElementType(); 205 Result = "\""; 206 for (unsigned i = 0; i < CVA->getNumOperands(); ++i) { 207 unsigned char C = cast<ConstantInt>(CVA->getOperand(i))->getRawValue(); 208 209 if (C == '"') { 210 Result += "\\\""; 211 } else if (C == '\\') { 212 Result += "\\\\"; 213 } else if (isprint(C)) { 214 Result += C; 215 } else { 216 switch(C) { 217 case '\b': Result += "\\b"; break; 218 case '\f': Result += "\\f"; break; 219 case '\n': Result += "\\n"; break; 220 case '\r': Result += "\\r"; break; 221 case '\t': Result += "\\t"; break; 222 default: 223 Result += '\\'; 224 Result += toOctal(C >> 6); 225 Result += toOctal(C >> 3); 226 Result += toOctal(C >> 0); 227 break; 228 } 229 } 230 } 231 Result += "\""; 232 return Result; 233} 234 235// Print a constant value or values (it may be an aggregate). 236void Printer::printConstantValueOnly(const Constant *CV) { 237 const TargetData &TD = TM.getTargetData(); 238 239 if (CV->isNullValue()) { 240 O << "\t.zero\t " << TD.getTypeSize(CV->getType()) << "\n"; 241 return; 242 } else if (const ConstantArray *CVA = dyn_cast<ConstantArray>(CV)) { 243 if (isStringCompatible(CVA)) { 244 // print the string alone and return 245 O << "\t.ascii\t" << getAsCString(CVA) << "\n"; 246 } else { // Not a string. Print the values in successive locations 247 const std::vector<Use> &constValues = CVA->getValues(); 248 for (unsigned i=0; i < constValues.size(); i++) 249 printConstantValueOnly(cast<Constant>(constValues[i].get())); 250 } 251 return; 252 } else if (const ConstantStruct *CVS = dyn_cast<ConstantStruct>(CV)) { 253 // Print the fields in successive locations. Pad to align if needed! 254 const StructLayout *cvsLayout = TD.getStructLayout(CVS->getType()); 255 const std::vector<Use>& constValues = CVS->getValues(); 256 unsigned sizeSoFar = 0; 257 for (unsigned i=0, N = constValues.size(); i < N; i++) { 258 const Constant* field = cast<Constant>(constValues[i].get()); 259 260 // Check if padding is needed and insert one or more 0s. 261 unsigned fieldSize = TD.getTypeSize(field->getType()); 262 unsigned padSize = ((i == N-1? cvsLayout->StructSize 263 : cvsLayout->MemberOffsets[i+1]) 264 - cvsLayout->MemberOffsets[i]) - fieldSize; 265 sizeSoFar += fieldSize + padSize; 266 267 // Now print the actual field value 268 printConstantValueOnly(field); 269 270 // Insert the field padding unless it's zero bytes... 271 if (padSize) 272 O << "\t.zero\t " << padSize << "\n"; 273 } 274 assert(sizeSoFar == cvsLayout->StructSize && 275 "Layout of constant struct may be incorrect!"); 276 return; 277 } 278 279 const Type *type = CV->getType(); 280 O << "\t"; 281 switch (type->getPrimitiveID()) { 282 case Type::BoolTyID: case Type::UByteTyID: case Type::SByteTyID: 283 O << ".byte"; 284 break; 285 case Type::UShortTyID: case Type::ShortTyID: 286 O << ".word"; 287 break; 288 case Type::FloatTyID: case Type::PointerTyID: 289 case Type::UIntTyID: case Type::IntTyID: 290 O << ".long"; 291 break; 292 case Type::DoubleTyID: 293 case Type::ULongTyID: case Type::LongTyID: 294 O << ".quad"; 295 break; 296 default: 297 assert (0 && "Can't handle printing this type of thing"); 298 break; 299 } 300 O << "\t"; 301 302 if (const ConstantExpr* CE = dyn_cast<ConstantExpr>(CV)) { 303 // Constant expression built from operators, constants, and 304 // symbolic addrs 305 O << ConstantExprToString(CE) << "\n"; 306 } else if (const ConstantBool *CB = dyn_cast<ConstantBool>(CV)) { 307 O << (CB->getValue() ? "1\n" : "0\n"); 308 } else if (type->isFloatingPoint()) { 309 // FP Constants are printed as integer constants to avoid losing 310 // precision... 311 double Val = cast<ConstantFP>(CV)->getValue(); 312 if (type == Type::FloatTy) { 313 union FU { // Abide by C TBAA rules 314 float FVal; 315 unsigned UVal; 316 } U; 317 U.FVal = Val; 318 O << U.UVal; 319 } else if (type == Type::DoubleTy) { 320 union DU { // Abide by C TBAA rules 321 double FVal; 322 uint64_t UVal; 323 } U; 324 U.FVal = Val; 325 O << U.UVal; 326 } else { 327 assert(0 && "Unknown floating point type!"); 328 } 329 330 O << "\t# " << *type << " value: " << Val << "\n"; 331 } else if (type->isPrimitiveType()) { 332 WriteAsOperand(O, CV, false, false) << "\n"; 333 } else if (const ConstantPointerRef* CPR = dyn_cast<ConstantPointerRef>(CV)) { 334 // This is a constant address for a global variable or method. 335 // Use the name of the variable or method as the address value. 336 O << Mang->getValueName(CPR->getValue()) << "\n"; 337 } else { 338 assert(0 && "Unknown elementary type for constant"); 339 } 340} 341 342/// printConstantPool - Print to the current output stream assembly 343/// representations of the constants in the constant pool MCP. This is 344/// used to print out constants which have been "spilled to memory" by 345/// the code generator. 346/// 347void Printer::printConstantPool(MachineConstantPool *MCP) { 348 const std::vector<Constant*> &CP = MCP->getConstants(); 349 const TargetData &TD = TM.getTargetData(); 350 351 if (CP.empty()) return; 352 353 for (unsigned i = 0, e = CP.size(); i != e; ++i) { 354 O << "\t.section .rodata\n"; 355 O << "\t.align " << (unsigned)TD.getTypeAlignment(CP[i]->getType()) 356 << "\n"; 357 O << ".CPI" << CurrentFnName << "_" << i << ":\t\t\t\t\t#" 358 << *CP[i] << "\n"; 359 printConstantValueOnly (CP[i]); 360 } 361} 362 363/// runOnMachineFunction - This uses the printMachineInstruction() 364/// method to print assembly for each instruction. 365/// 366bool Printer::runOnMachineFunction(MachineFunction &MF) { 367 // BBNumber is used here so that a given Printer will never give two 368 // BBs the same name. (If you have a better way, please let me know!) 369 static unsigned BBNumber = 0; 370 371 O << "\n\n"; 372 // What's my mangled name? 373 CurrentFnName = Mang->getValueName(MF.getFunction()); 374 375 // Print out constants referenced by the function 376 printConstantPool(MF.getConstantPool()); 377 378 // Print out labels for the function. 379 O << "\t.text\n"; 380 O << "\t.align 16\n"; 381 O << "\t.globl\t" << CurrentFnName << "\n"; 382 if (!EmitCygwin) 383 O << "\t.type\t" << CurrentFnName << ", @function\n"; 384 O << CurrentFnName << ":\n"; 385 386 // Number each basic block so that we can consistently refer to them 387 // in PC-relative references. 388 NumberForBB.clear(); 389 for (MachineFunction::const_iterator I = MF.begin(), E = MF.end(); 390 I != E; ++I) { 391 NumberForBB[I->getBasicBlock()] = BBNumber++; 392 } 393 394 // Print out code for the function. 395 for (MachineFunction::const_iterator I = MF.begin(), E = MF.end(); 396 I != E; ++I) { 397 // Print a label for the basic block. 398 O << ".LBB" << NumberForBB[I->getBasicBlock()] << ":\t# " 399 << I->getBasicBlock()->getName() << "\n"; 400 for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end(); 401 II != E; ++II) { 402 // Print the assembly for the instruction. 403 O << "\t"; 404 printMachineInstruction(*II); 405 } 406 } 407 408 // We didn't modify anything. 409 return false; 410} 411 412static bool isScale(const MachineOperand &MO) { 413 return MO.isImmediate() && 414 (MO.getImmedValue() == 1 || MO.getImmedValue() == 2 || 415 MO.getImmedValue() == 4 || MO.getImmedValue() == 8); 416} 417 418static bool isMem(const MachineInstr *MI, unsigned Op) { 419 if (MI->getOperand(Op).isFrameIndex()) return true; 420 if (MI->getOperand(Op).isConstantPoolIndex()) return true; 421 return Op+4 <= MI->getNumOperands() && 422 MI->getOperand(Op ).isRegister() &&isScale(MI->getOperand(Op+1)) && 423 MI->getOperand(Op+2).isRegister() &&MI->getOperand(Op+3).isImmediate(); 424} 425 426 427 428void Printer::printOp(const MachineOperand &MO, 429 bool elideOffsetKeyword /* = false */) { 430 const MRegisterInfo &RI = *TM.getRegisterInfo(); 431 switch (MO.getType()) { 432 case MachineOperand::MO_VirtualRegister: 433 if (Value *V = MO.getVRegValueOrNull()) { 434 O << "<" << V->getName() << ">"; 435 return; 436 } 437 // FALLTHROUGH 438 case MachineOperand::MO_MachineRegister: 439 if (MO.getReg() < MRegisterInfo::FirstVirtualRegister) 440 // Bug Workaround: See note in Printer::doInitialization about %. 441 O << "%" << RI.get(MO.getReg()).Name; 442 else 443 O << "%reg" << MO.getReg(); 444 return; 445 446 case MachineOperand::MO_SignExtendedImmed: 447 case MachineOperand::MO_UnextendedImmed: 448 O << (int)MO.getImmedValue(); 449 return; 450 case MachineOperand::MO_PCRelativeDisp: { 451 ValueMapTy::const_iterator i = NumberForBB.find(MO.getVRegValue()); 452 assert (i != NumberForBB.end() 453 && "Could not find a BB in the NumberForBB map!"); 454 O << ".LBB" << i->second << " # PC rel: " << MO.getVRegValue()->getName(); 455 return; 456 } 457 case MachineOperand::MO_GlobalAddress: 458 if (!elideOffsetKeyword) 459 O << "OFFSET "; 460 O << Mang->getValueName(MO.getGlobal()); 461 return; 462 case MachineOperand::MO_ExternalSymbol: 463 O << MO.getSymbolName(); 464 return; 465 default: 466 O << "<unknown operand type>"; return; 467 } 468} 469 470static const std::string sizePtr(const TargetInstrDescriptor &Desc) { 471 switch (Desc.TSFlags & X86II::ArgMask) { 472 default: assert(0 && "Unknown arg size!"); 473 case X86II::Arg8: return "BYTE PTR"; 474 case X86II::Arg16: return "WORD PTR"; 475 case X86II::Arg32: return "DWORD PTR"; 476 case X86II::Arg64: return "QWORD PTR"; 477 case X86II::ArgF32: return "DWORD PTR"; 478 case X86II::ArgF64: return "QWORD PTR"; 479 case X86II::ArgF80: return "XWORD PTR"; 480 } 481} 482 483void Printer::printMemReference(const MachineInstr *MI, unsigned Op) { 484 assert(isMem(MI, Op) && "Invalid memory reference!"); 485 486 if (MI->getOperand(Op).isFrameIndex()) { 487 O << "[frame slot #" << MI->getOperand(Op).getFrameIndex(); 488 if (MI->getOperand(Op+3).getImmedValue()) 489 O << " + " << MI->getOperand(Op+3).getImmedValue(); 490 O << "]"; 491 return; 492 } else if (MI->getOperand(Op).isConstantPoolIndex()) { 493 O << "[.CPI" << CurrentFnName << "_" 494 << MI->getOperand(Op).getConstantPoolIndex(); 495 if (MI->getOperand(Op+3).getImmedValue()) 496 O << " + " << MI->getOperand(Op+3).getImmedValue(); 497 O << "]"; 498 return; 499 } 500 501 const MachineOperand &BaseReg = MI->getOperand(Op); 502 int ScaleVal = MI->getOperand(Op+1).getImmedValue(); 503 const MachineOperand &IndexReg = MI->getOperand(Op+2); 504 int DispVal = MI->getOperand(Op+3).getImmedValue(); 505 506 O << "["; 507 bool NeedPlus = false; 508 if (BaseReg.getReg()) { 509 printOp(BaseReg); 510 NeedPlus = true; 511 } 512 513 if (IndexReg.getReg()) { 514 if (NeedPlus) O << " + "; 515 if (ScaleVal != 1) 516 O << ScaleVal << "*"; 517 printOp(IndexReg); 518 NeedPlus = true; 519 } 520 521 if (DispVal) { 522 if (NeedPlus) 523 if (DispVal > 0) 524 O << " + "; 525 else { 526 O << " - "; 527 DispVal = -DispVal; 528 } 529 O << DispVal; 530 } 531 O << "]"; 532} 533 534/// checkImplUses - Emit the implicit-use registers for the 535/// instruction described by DESC, if its PrintImplUses flag is set. 536/// 537void Printer::checkImplUses (const TargetInstrDescriptor &Desc) { 538 const MRegisterInfo &RI = *TM.getRegisterInfo(); 539 if (Desc.TSFlags & X86II::PrintImplUses) { 540 for (const unsigned *p = Desc.ImplicitUses; *p; ++p) { 541 // Bug Workaround: See note in Printer::doInitialization about %. 542 O << ", %" << RI.get(*p).Name; 543 } 544 } 545} 546 547/// printMachineInstruction -- Print out a single X86 LLVM instruction 548/// MI in Intel syntax to the current output stream. 549/// 550void Printer::printMachineInstruction(const MachineInstr *MI) { 551 unsigned Opcode = MI->getOpcode(); 552 const TargetInstrInfo &TII = TM.getInstrInfo(); 553 const TargetInstrDescriptor &Desc = TII.get(Opcode); 554 555 ++EmittedInsts; 556 switch (Desc.TSFlags & X86II::FormMask) { 557 case X86II::Pseudo: 558 // Print pseudo-instructions as comments; either they should have been 559 // turned into real instructions by now, or they don't need to be 560 // seen by the assembler (e.g., IMPLICIT_USEs.) 561 O << "# "; 562 if (Opcode == X86::PHI) { 563 printOp(MI->getOperand(0)); 564 O << " = phi "; 565 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) { 566 if (i != 1) O << ", "; 567 O << "["; 568 printOp(MI->getOperand(i)); 569 O << ", "; 570 printOp(MI->getOperand(i+1)); 571 O << "]"; 572 } 573 } else { 574 unsigned i = 0; 575 if (MI->getNumOperands() && (MI->getOperand(0).opIsDefOnly() || 576 MI->getOperand(0).opIsDefAndUse())) { 577 printOp(MI->getOperand(0)); 578 O << " = "; 579 ++i; 580 } 581 O << TII.getName(MI->getOpcode()); 582 583 for (unsigned e = MI->getNumOperands(); i != e; ++i) { 584 O << " "; 585 if (MI->getOperand(i).opIsDefOnly() || 586 MI->getOperand(i).opIsDefAndUse()) O << "*"; 587 printOp(MI->getOperand(i)); 588 if (MI->getOperand(i).opIsDefOnly() || 589 MI->getOperand(i).opIsDefAndUse()) O << "*"; 590 } 591 } 592 O << "\n"; 593 return; 594 595 case X86II::RawFrm: 596 // The accepted forms of Raw instructions are: 597 // 1. nop - No operand required 598 // 2. jmp foo - PC relative displacement operand 599 // 3. call bar - GlobalAddress Operand or External Symbol Operand 600 // 601 assert(MI->getNumOperands() == 0 || 602 (MI->getNumOperands() == 1 && 603 (MI->getOperand(0).isPCRelativeDisp() || 604 MI->getOperand(0).isGlobalAddress() || 605 MI->getOperand(0).isExternalSymbol())) && 606 "Illegal raw instruction!"); 607 O << TII.getName(MI->getOpcode()) << " "; 608 609 if (MI->getNumOperands() == 1) { 610 printOp(MI->getOperand(0), true); // Don't print "OFFSET"... 611 } 612 O << "\n"; 613 return; 614 615 case X86II::AddRegFrm: { 616 // There are currently two forms of acceptable AddRegFrm instructions. 617 // Either the instruction JUST takes a single register (like inc, dec, etc), 618 // or it takes a register and an immediate of the same size as the register 619 // (move immediate f.e.). Note that this immediate value might be stored as 620 // an LLVM value, to represent, for example, loading the address of a global 621 // into a register. The initial register might be duplicated if this is a 622 // M_2_ADDR_REG instruction 623 // 624 assert(MI->getOperand(0).isRegister() && 625 (MI->getNumOperands() == 1 || 626 (MI->getNumOperands() == 2 && 627 (MI->getOperand(1).getVRegValueOrNull() || 628 MI->getOperand(1).isImmediate() || 629 MI->getOperand(1).isRegister() || 630 MI->getOperand(1).isGlobalAddress() || 631 MI->getOperand(1).isExternalSymbol()))) && 632 "Illegal form for AddRegFrm instruction!"); 633 634 unsigned Reg = MI->getOperand(0).getReg(); 635 636 O << TII.getName(MI->getOpCode()) << " "; 637 printOp(MI->getOperand(0)); 638 if (MI->getNumOperands() == 2 && 639 (!MI->getOperand(1).isRegister() || 640 MI->getOperand(1).getVRegValueOrNull() || 641 MI->getOperand(1).isGlobalAddress() || 642 MI->getOperand(1).isExternalSymbol())) { 643 O << ", "; 644 printOp(MI->getOperand(1)); 645 } 646 checkImplUses(Desc); 647 O << "\n"; 648 return; 649 } 650 case X86II::MRMDestReg: { 651 // There are two acceptable forms of MRMDestReg instructions, those with 2, 652 // 3 and 4 operands: 653 // 654 // 2 Operands: this is for things like mov that do not read a second input 655 // 656 // 3 Operands: in this form, the first two registers (the destination, and 657 // the first operand) should be the same, post register allocation. The 3rd 658 // operand is an additional input. This should be for things like add 659 // instructions. 660 // 661 // 4 Operands: This form is for instructions which are 3 operands forms, but 662 // have a constant argument as well. 663 // 664 bool isTwoAddr = TII.isTwoAddrInstr(Opcode); 665 assert(MI->getOperand(0).isRegister() && 666 (MI->getNumOperands() == 2 || 667 (isTwoAddr && MI->getOperand(1).isRegister() && 668 MI->getOperand(0).getReg() == MI->getOperand(1).getReg() && 669 (MI->getNumOperands() == 3 || 670 (MI->getNumOperands() == 4 && MI->getOperand(3).isImmediate())))) 671 && "Bad format for MRMDestReg!"); 672 673 O << TII.getName(MI->getOpCode()) << " "; 674 printOp(MI->getOperand(0)); 675 O << ", "; 676 printOp(MI->getOperand(1+isTwoAddr)); 677 if (MI->getNumOperands() == 4) { 678 O << ", "; 679 printOp(MI->getOperand(3)); 680 } 681 O << "\n"; 682 return; 683 } 684 685 case X86II::MRMDestMem: { 686 // These instructions are the same as MRMDestReg, but instead of having a 687 // register reference for the mod/rm field, it's a memory reference. 688 // 689 assert(isMem(MI, 0) && MI->getNumOperands() == 4+1 && 690 MI->getOperand(4).isRegister() && "Bad format for MRMDestMem!"); 691 692 O << TII.getName(MI->getOpCode()) << " " << sizePtr(Desc) << " "; 693 printMemReference(MI, 0); 694 O << ", "; 695 printOp(MI->getOperand(4)); 696 O << "\n"; 697 return; 698 } 699 700 case X86II::MRMSrcReg: { 701 // There are three forms that are acceptable for MRMSrcReg instructions, 702 // those with 3 and 2 operands: 703 // 704 // 3 Operands: in this form, the last register (the second input) is the 705 // ModR/M input. The first two operands should be the same, post register 706 // allocation. This is for things like: add r32, r/m32 707 // 708 // 3 Operands: in this form, we can have 'INST R, R, imm', which is used for 709 // instructions like the IMULri instructions. 710 // 711 // 2 Operands: this is for things like mov that do not read a second input 712 // 713 assert(MI->getOperand(0).isRegister() && 714 MI->getOperand(1).isRegister() && 715 (MI->getNumOperands() == 2 || 716 (MI->getNumOperands() == 3 && 717 (MI->getOperand(2).isRegister() || 718 MI->getOperand(2).isImmediate()))) 719 && "Bad format for MRMSrcReg!"); 720 if (MI->getNumOperands() == 3 && 721 MI->getOperand(0).getReg() != MI->getOperand(1).getReg()) 722 O << "**"; 723 724 O << TII.getName(MI->getOpCode()) << " "; 725 printOp(MI->getOperand(0)); 726 727 // If this is IMULri* instructions, print the non-two-address operand. 728 if (MI->getNumOperands() == 3 && MI->getOperand(2).isImmediate()) { 729 O << ", "; 730 printOp(MI->getOperand(1)); 731 } 732 733 O << ", "; 734 printOp(MI->getOperand(MI->getNumOperands()-1)); 735 O << "\n"; 736 return; 737 } 738 739 case X86II::MRMSrcMem: { 740 // These instructions are the same as MRMSrcReg, but instead of having a 741 // register reference for the mod/rm field, it's a memory reference. 742 // 743 assert(MI->getOperand(0).isRegister() && 744 (MI->getNumOperands() == 1+4 && isMem(MI, 1)) || 745 (MI->getNumOperands() == 2+4 && MI->getOperand(1).isRegister() && 746 isMem(MI, 2)) 747 && "Bad format for MRMDestReg!"); 748 if (MI->getNumOperands() == 2+4 && 749 MI->getOperand(0).getReg() != MI->getOperand(1).getReg()) 750 O << "**"; 751 752 O << TII.getName(MI->getOpCode()) << " "; 753 printOp(MI->getOperand(0)); 754 O << ", " << sizePtr(Desc) << " "; 755 printMemReference(MI, MI->getNumOperands()-4); 756 O << "\n"; 757 return; 758 } 759 760 case X86II::MRMS0r: case X86II::MRMS1r: 761 case X86II::MRMS2r: case X86II::MRMS3r: 762 case X86II::MRMS4r: case X86II::MRMS5r: 763 case X86II::MRMS6r: case X86II::MRMS7r: { 764 // In this form, the following are valid formats: 765 // 1. sete r 766 // 2. cmp reg, immediate 767 // 2. shl rdest, rinput <implicit CL or 1> 768 // 3. sbb rdest, rinput, immediate [rdest = rinput] 769 // 770 assert(MI->getNumOperands() > 0 && MI->getNumOperands() < 4 && 771 MI->getOperand(0).isRegister() && "Bad MRMSxR format!"); 772 assert((MI->getNumOperands() != 2 || 773 MI->getOperand(1).isRegister() || MI->getOperand(1).isImmediate())&& 774 "Bad MRMSxR format!"); 775 assert((MI->getNumOperands() < 3 || 776 (MI->getOperand(1).isRegister() && MI->getOperand(2).isImmediate())) && 777 "Bad MRMSxR format!"); 778 779 if (MI->getNumOperands() > 1 && MI->getOperand(1).isRegister() && 780 MI->getOperand(0).getReg() != MI->getOperand(1).getReg()) 781 O << "**"; 782 783 O << TII.getName(MI->getOpCode()) << " "; 784 printOp(MI->getOperand(0)); 785 if (MI->getOperand(MI->getNumOperands()-1).isImmediate()) { 786 O << ", "; 787 printOp(MI->getOperand(MI->getNumOperands()-1)); 788 } 789 checkImplUses(Desc); 790 O << "\n"; 791 792 return; 793 } 794 795 case X86II::MRMS0m: case X86II::MRMS1m: 796 case X86II::MRMS2m: case X86II::MRMS3m: 797 case X86II::MRMS4m: case X86II::MRMS5m: 798 case X86II::MRMS6m: case X86II::MRMS7m: { 799 // In this form, the following are valid formats: 800 // 1. sete [m] 801 // 2. cmp [m], immediate 802 // 2. shl [m], rinput <implicit CL or 1> 803 // 3. sbb [m], immediate 804 // 805 assert(MI->getNumOperands() >= 4 && MI->getNumOperands() <= 5 && 806 isMem(MI, 0) && "Bad MRMSxM format!"); 807 assert((MI->getNumOperands() != 5 || MI->getOperand(4).isImmediate()) && 808 "Bad MRMSxM format!"); 809 // Bug: The 80-bit FP store-pop instruction "fstp XWORD PTR [...]" 810 // is misassembled by gas in intel_syntax mode as its 32-bit 811 // equivalent "fstp DWORD PTR [...]". Workaround: Output the raw 812 // opcode bytes instead of the instruction. 813 if (MI->getOpCode() == X86::FSTPr80) { 814 if ((MI->getOperand(0).getReg() == X86::ESP) 815 && (MI->getOperand(1).getImmedValue() == 1)) { 816 int DispVal = MI->getOperand(3).getImmedValue(); 817 if ((DispVal < -128) || (DispVal > 127)) { // 4 byte disp. 818 unsigned int val = (unsigned int) DispVal; 819 O << ".byte 0xdb, 0xbc, 0x24\n\t"; 820 O << ".long 0x" << std::hex << (unsigned) val << std::dec << "\t# "; 821 } else { // 1 byte disp. 822 unsigned char val = (unsigned char) DispVal; 823 O << ".byte 0xdb, 0x7c, 0x24, 0x" << std::hex << (unsigned) val 824 << std::dec << "\t# "; 825 } 826 } 827 } 828 // Bug: The 80-bit FP load instruction "fld XWORD PTR [...]" is 829 // misassembled by gas in intel_syntax mode as its 32-bit 830 // equivalent "fld DWORD PTR [...]". Workaround: Output the raw 831 // opcode bytes instead of the instruction. 832 if (MI->getOpCode() == X86::FLDr80) { 833 if ((MI->getOperand(0).getReg() == X86::ESP) 834 && (MI->getOperand(1).getImmedValue() == 1)) { 835 int DispVal = MI->getOperand(3).getImmedValue(); 836 if ((DispVal < -128) || (DispVal > 127)) { // 4 byte disp. 837 unsigned int val = (unsigned int) DispVal; 838 O << ".byte 0xdb, 0xac, 0x24\n\t"; 839 O << ".long 0x" << std::hex << (unsigned) val << std::dec << "\t# "; 840 } else { // 1 byte disp. 841 unsigned char val = (unsigned char) DispVal; 842 O << ".byte 0xdb, 0x6c, 0x24, 0x" << std::hex << (unsigned) val 843 << std::dec << "\t# "; 844 } 845 } 846 } 847 // Bug: gas intel_syntax mode treats "fild QWORD PTR [...]" as an 848 // invalid opcode, saying "64 bit operations are only supported in 849 // 64 bit modes." libopcodes disassembles it as "fild DWORD PTR 850 // [...]", which is wrong. Workaround: Output the raw opcode bytes 851 // instead of the instruction. 852 if (MI->getOpCode() == X86::FILDr64) { 853 if ((MI->getOperand(0).getReg() == X86::ESP) 854 && (MI->getOperand(1).getImmedValue() == 1)) { 855 int DispVal = MI->getOperand(3).getImmedValue(); 856 if ((DispVal < -128) || (DispVal > 127)) { // 4 byte disp. 857 unsigned int val = (unsigned int) DispVal; 858 O << ".byte 0xdf, 0xac, 0x24\n\t"; 859 O << ".long 0x" << std::hex << (unsigned) val << std::dec << "\t# "; 860 } else { // 1 byte disp. 861 unsigned char val = (unsigned char) DispVal; 862 O << ".byte 0xdf, 0x6c, 0x24, 0x" << std::hex << (unsigned) val 863 << std::dec << "\t# "; 864 } 865 } 866 } 867 // Bug: gas intel_syntax mode treats "fistp QWORD PTR [...]" as 868 // an invalid opcode, saying "64 bit operations are only 869 // supported in 64 bit modes." libopcodes disassembles it as 870 // "fistpll DWORD PTR [...]", which is wrong. Workaround: Output 871 // "fistpll DWORD PTR " instead, which is what libopcodes is 872 // expecting to see. 873 if (MI->getOpCode() == X86::FISTPr64) { 874 O << "fistpll DWORD PTR "; 875 printMemReference(MI, 0); 876 if (MI->getNumOperands() == 5) { 877 O << ", "; 878 printOp(MI->getOperand(4)); 879 } 880 O << "\t# "; 881 } 882 883 O << TII.getName(MI->getOpCode()) << " "; 884 O << sizePtr(Desc) << " "; 885 printMemReference(MI, 0); 886 if (MI->getNumOperands() == 5) { 887 O << ", "; 888 printOp(MI->getOperand(4)); 889 } 890 O << "\n"; 891 return; 892 } 893 894 default: 895 O << "\tUNKNOWN FORM:\t\t-"; MI->print(O, TM); break; 896 } 897} 898 899bool Printer::doInitialization(Module &M) { 900 // Tell gas we are outputting Intel syntax (not AT&T syntax) assembly. 901 // 902 // Bug: gas in `intel_syntax noprefix' mode interprets the symbol `Sp' in an 903 // instruction as a reference to the register named sp, and if you try to 904 // reference a symbol `Sp' (e.g. `mov ECX, OFFSET Sp') then it gets lowercased 905 // before being looked up in the symbol table. This creates spurious 906 // `undefined symbol' errors when linking. Workaround: Do not use `noprefix' 907 // mode, and decorate all register names with percent signs. 908 O << "\t.intel_syntax\n"; 909 Mang = new Mangler(M, EmitCygwin); 910 return false; // success 911} 912 913// SwitchSection - Switch to the specified section of the executable if we are 914// not already in it! 915// 916static void SwitchSection(std::ostream &OS, std::string &CurSection, 917 const char *NewSection) { 918 if (CurSection != NewSection) { 919 CurSection = NewSection; 920 if (!CurSection.empty()) 921 OS << "\t" << NewSection << "\n"; 922 } 923} 924 925bool Printer::doFinalization(Module &M) { 926 const TargetData &TD = TM.getTargetData(); 927 std::string CurSection; 928 929 // Print out module-level global variables here. 930 for (Module::const_giterator I = M.gbegin(), E = M.gend(); I != E; ++I) 931 if (I->hasInitializer()) { // External global require no code 932 O << "\n\n"; 933 std::string name = Mang->getValueName(I); 934 Constant *C = I->getInitializer(); 935 unsigned Size = TD.getTypeSize(C->getType()); 936 unsigned Align = TD.getTypeAlignment(C->getType()); 937 938 if (C->isNullValue() && 939 (I->hasLinkOnceLinkage() || I->hasInternalLinkage() || 940 I->hasWeakLinkage() /* FIXME: Verify correct */)) { 941 SwitchSection(O, CurSection, ".data"); 942 if (I->hasInternalLinkage()) 943 O << "\t.local " << name << "\n"; 944 945 O << "\t.comm " << name << "," << TD.getTypeSize(C->getType()) 946 << "," << (unsigned)TD.getTypeAlignment(C->getType()); 947 O << "\t\t# "; 948 WriteAsOperand(O, I, true, true, &M); 949 O << "\n"; 950 } else { 951 switch (I->getLinkage()) { 952 case GlobalValue::LinkOnceLinkage: 953 case GlobalValue::WeakLinkage: // FIXME: Verify correct for weak. 954 // Nonnull linkonce -> weak 955 O << "\t.weak " << name << "\n"; 956 SwitchSection(O, CurSection, ""); 957 O << "\t.section\t.llvm.linkonce.d." << name << ",\"aw\",@progbits\n"; 958 break; 959 960 case GlobalValue::AppendingLinkage: 961 // FIXME: appending linkage variables should go into a section of 962 // their name or something. For now, just emit them as external. 963 case GlobalValue::ExternalLinkage: 964 // If external or appending, declare as a global symbol 965 O << "\t.globl " << name << "\n"; 966 // FALL THROUGH 967 case GlobalValue::InternalLinkage: 968 if (C->isNullValue()) 969 SwitchSection(O, CurSection, ".bss"); 970 else 971 SwitchSection(O, CurSection, ".data"); 972 break; 973 } 974 975 O << "\t.align " << Align << "\n"; 976 O << "\t.type " << name << ",@object\n"; 977 O << "\t.size " << name << "," << Size << "\n"; 978 O << name << ":\t\t\t\t# "; 979 WriteAsOperand(O, I, true, true, &M); 980 O << " = "; 981 WriteAsOperand(O, C, false, false, &M); 982 O << "\n"; 983 printConstantValueOnly(C); 984 } 985 } 986 987 delete Mang; 988 return false; // success 989} 990