X86AsmPrinter.cpp revision 5b672526205cc4438deb529363fb9bdaebbe086a
1//===-- X86/Printer.cpp - Convert X86 LLVM code to Intel assembly ---------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains a printer that converts from our internal 11// representation of machine-dependent LLVM code to Intel-format 12// assembly language. This printer is the output mechanism used 13// by `llc' and `lli -print-machineinstrs' on X86. 14// 15//===----------------------------------------------------------------------===// 16 17#include "X86.h" 18#include "X86InstrInfo.h" 19#include "llvm/Constants.h" 20#include "llvm/DerivedTypes.h" 21#include "llvm/Module.h" 22#include "llvm/Assembly/Writer.h" 23#include "llvm/CodeGen/MachineFunctionPass.h" 24#include "llvm/CodeGen/MachineConstantPool.h" 25#include "llvm/CodeGen/MachineInstr.h" 26#include "llvm/Target/TargetMachine.h" 27#include "llvm/Support/Mangler.h" 28#include "Support/Statistic.h" 29#include "Support/StringExtras.h" 30#include "Support/CommandLine.h" 31using namespace llvm; 32 33namespace { 34 Statistic<> EmittedInsts("asm-printer", "Number of machine instrs printed"); 35 36 // FIXME: This should be automatically picked up by autoconf from the C 37 // frontend 38 cl::opt<bool> EmitCygwin("enable-cygwin-compatible-output", cl::Hidden, 39 cl::desc("Emit X86 assembly code suitable for consumption by cygwin")); 40 41 struct Printer : public MachineFunctionPass { 42 /// Output stream on which we're printing assembly code. 43 /// 44 std::ostream &O; 45 46 /// Target machine description which we query for reg. names, data 47 /// layout, etc. 48 /// 49 TargetMachine &TM; 50 51 /// Name-mangler for global names. 52 /// 53 Mangler *Mang; 54 55 Printer(std::ostream &o, TargetMachine &tm) : O(o), TM(tm) { } 56 57 /// We name each basic block in a Function with a unique number, so 58 /// that we can consistently refer to them later. This is cleared 59 /// at the beginning of each call to runOnMachineFunction(). 60 /// 61 typedef std::map<const Value *, unsigned> ValueMapTy; 62 ValueMapTy NumberForBB; 63 64 /// Cache of mangled name for current function. This is 65 /// recalculated at the beginning of each call to 66 /// runOnMachineFunction(). 67 /// 68 std::string CurrentFnName; 69 70 virtual const char *getPassName() const { 71 return "X86 Assembly Printer"; 72 } 73 74 void checkImplUses (const TargetInstrDescriptor &Desc); 75 void printMachineInstruction(const MachineInstr *MI); 76 void printOp(const MachineOperand &MO, 77 bool elideOffsetKeyword = false); 78 void printMemReference(const MachineInstr *MI, unsigned Op); 79 void printConstantPool(MachineConstantPool *MCP); 80 bool runOnMachineFunction(MachineFunction &F); 81 bool doInitialization(Module &M); 82 bool doFinalization(Module &M); 83 void emitGlobalConstant(const Constant* CV); 84 void emitConstantValueOnly(const Constant *CV); 85 }; 86} // end of anonymous namespace 87 88/// createX86CodePrinterPass - Returns a pass that prints the X86 89/// assembly code for a MachineFunction to the given output stream, 90/// using the given target machine description. This should work 91/// regardless of whether the function is in SSA form. 92/// 93FunctionPass *llvm::createX86CodePrinterPass(std::ostream &o,TargetMachine &tm){ 94 return new Printer(o, tm); 95} 96 97/// toOctal - Convert the low order bits of X into an octal digit. 98/// 99static inline char toOctal(int X) { 100 return (X&7)+'0'; 101} 102 103/// getAsCString - Return the specified array as a C compatible 104/// string, only if the predicate isStringCompatible is true. 105/// 106static void printAsCString(std::ostream &O, const ConstantArray *CVA) { 107 assert(CVA->isString() && "Array is not string compatible!"); 108 109 O << "\""; 110 for (unsigned i = 0; i != CVA->getNumOperands(); ++i) { 111 unsigned char C = cast<ConstantInt>(CVA->getOperand(i))->getRawValue(); 112 113 if (C == '"') { 114 O << "\\\""; 115 } else if (C == '\\') { 116 O << "\\\\"; 117 } else if (isprint(C)) { 118 O << C; 119 } else { 120 switch(C) { 121 case '\b': O << "\\b"; break; 122 case '\f': O << "\\f"; break; 123 case '\n': O << "\\n"; break; 124 case '\r': O << "\\r"; break; 125 case '\t': O << "\\t"; break; 126 default: 127 O << '\\'; 128 O << toOctal(C >> 6); 129 O << toOctal(C >> 3); 130 O << toOctal(C >> 0); 131 break; 132 } 133 } 134 } 135 O << "\""; 136} 137 138// Print out the specified constant, without a storage class. Only the 139// constants valid in constant expressions can occur here. 140void Printer::emitConstantValueOnly(const Constant *CV) { 141 if (CV->isNullValue()) 142 O << "0"; 143 else if (const ConstantBool *CB = dyn_cast<ConstantBool>(CV)) { 144 assert(CB == ConstantBool::True); 145 O << "1"; 146 } else if (const ConstantSInt *CI = dyn_cast<ConstantSInt>(CV)) 147 O << CI->getValue(); 148 else if (const ConstantUInt *CI = dyn_cast<ConstantUInt>(CV)) 149 O << CI->getValue(); 150 else if (const ConstantPointerRef *CPR = dyn_cast<ConstantPointerRef>(CV)) 151 // This is a constant address for a global variable or function. Use the 152 // name of the variable or function as the address value. 153 O << Mang->getValueName(CPR->getValue()); 154 else if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(CV)) { 155 const TargetData &TD = TM.getTargetData(); 156 switch(CE->getOpcode()) { 157 case Instruction::GetElementPtr: { 158 // generate a symbolic expression for the byte address 159 const Constant *ptrVal = CE->getOperand(0); 160 std::vector<Value*> idxVec(CE->op_begin()+1, CE->op_end()); 161 if (unsigned Offset = TD.getIndexedOffset(ptrVal->getType(), idxVec)) { 162 O << "("; 163 emitConstantValueOnly(ptrVal); 164 O << ") + " << Offset; 165 } else { 166 emitConstantValueOnly(ptrVal); 167 } 168 break; 169 } 170 case Instruction::Cast: { 171 // Support only non-converting or widening casts for now, that is, ones 172 // that do not involve a change in value. This assertion is really gross, 173 // and may not even be a complete check. 174 Constant *Op = CE->getOperand(0); 175 const Type *OpTy = Op->getType(), *Ty = CE->getType(); 176 177 // Remember, kids, pointers on x86 can be losslessly converted back and 178 // forth into 32-bit or wider integers, regardless of signedness. :-P 179 assert(((isa<PointerType>(OpTy) 180 && (Ty == Type::LongTy || Ty == Type::ULongTy 181 || Ty == Type::IntTy || Ty == Type::UIntTy)) 182 || (isa<PointerType>(Ty) 183 && (OpTy == Type::LongTy || OpTy == Type::ULongTy 184 || OpTy == Type::IntTy || OpTy == Type::UIntTy)) 185 || (((TD.getTypeSize(Ty) >= TD.getTypeSize(OpTy)) 186 && OpTy->isLosslesslyConvertibleTo(Ty)))) 187 && "FIXME: Don't yet support this kind of constant cast expr"); 188 O << "("; 189 emitConstantValueOnly(Op); 190 O << ")"; 191 break; 192 } 193 case Instruction::Add: 194 O << "("; 195 emitConstantValueOnly(CE->getOperand(0)); 196 O << ") + ("; 197 emitConstantValueOnly(CE->getOperand(1)); 198 O << ")"; 199 break; 200 default: 201 assert(0 && "Unsupported operator!"); 202 } 203 } else { 204 assert(0 && "Unknown constant value!"); 205 } 206} 207 208// Print a constant value or values, with the appropriate storage class as a 209// prefix. 210void Printer::emitGlobalConstant(const Constant *CV) { 211 const TargetData &TD = TM.getTargetData(); 212 213 if (CV->isNullValue()) { 214 O << "\t.zero\t " << TD.getTypeSize(CV->getType()) << "\n"; 215 return; 216 } else if (const ConstantArray *CVA = dyn_cast<ConstantArray>(CV)) { 217 if (CVA->isString()) { 218 O << "\t.ascii\t"; 219 printAsCString(O, CVA); 220 O << "\n"; 221 } else { // Not a string. Print the values in successive locations 222 const std::vector<Use> &constValues = CVA->getValues(); 223 for (unsigned i=0; i < constValues.size(); i++) 224 emitGlobalConstant(cast<Constant>(constValues[i].get())); 225 } 226 return; 227 } else if (const ConstantStruct *CVS = dyn_cast<ConstantStruct>(CV)) { 228 // Print the fields in successive locations. Pad to align if needed! 229 const StructLayout *cvsLayout = TD.getStructLayout(CVS->getType()); 230 const std::vector<Use>& constValues = CVS->getValues(); 231 unsigned sizeSoFar = 0; 232 for (unsigned i=0, N = constValues.size(); i < N; i++) { 233 const Constant* field = cast<Constant>(constValues[i].get()); 234 235 // Check if padding is needed and insert one or more 0s. 236 unsigned fieldSize = TD.getTypeSize(field->getType()); 237 unsigned padSize = ((i == N-1? cvsLayout->StructSize 238 : cvsLayout->MemberOffsets[i+1]) 239 - cvsLayout->MemberOffsets[i]) - fieldSize; 240 sizeSoFar += fieldSize + padSize; 241 242 // Now print the actual field value 243 emitGlobalConstant(field); 244 245 // Insert the field padding unless it's zero bytes... 246 if (padSize) 247 O << "\t.zero\t " << padSize << "\n"; 248 } 249 assert(sizeSoFar == cvsLayout->StructSize && 250 "Layout of constant struct may be incorrect!"); 251 return; 252 } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) { 253 // FP Constants are printed as integer constants to avoid losing 254 // precision... 255 double Val = CFP->getValue(); 256 switch (CFP->getType()->getPrimitiveID()) { 257 default: assert(0 && "Unknown floating point type!"); 258 case Type::FloatTyID: { 259 union FU { // Abide by C TBAA rules 260 float FVal; 261 unsigned UVal; 262 } U; 263 U.FVal = Val; 264 O << ".long\t" << U.UVal << "\t# float " << Val << "\n"; 265 return; 266 } 267 case Type::DoubleTyID: { 268 union DU { // Abide by C TBAA rules 269 double FVal; 270 uint64_t UVal; 271 } U; 272 U.FVal = Val; 273 O << ".quad\t" << U.UVal << "\t# double " << Val << "\n"; 274 return; 275 } 276 } 277 } 278 279 const Type *type = CV->getType(); 280 O << "\t"; 281 switch (type->getPrimitiveID()) { 282 case Type::BoolTyID: case Type::UByteTyID: case Type::SByteTyID: 283 O << ".byte"; 284 break; 285 case Type::UShortTyID: case Type::ShortTyID: 286 O << ".word"; 287 break; 288 case Type::FloatTyID: case Type::PointerTyID: 289 case Type::UIntTyID: case Type::IntTyID: 290 O << ".long"; 291 break; 292 case Type::DoubleTyID: 293 case Type::ULongTyID: case Type::LongTyID: 294 O << ".quad"; 295 break; 296 default: 297 assert (0 && "Can't handle printing this type of thing"); 298 break; 299 } 300 O << "\t"; 301 emitConstantValueOnly(CV); 302 O << "\n"; 303} 304 305/// printConstantPool - Print to the current output stream assembly 306/// representations of the constants in the constant pool MCP. This is 307/// used to print out constants which have been "spilled to memory" by 308/// the code generator. 309/// 310void Printer::printConstantPool(MachineConstantPool *MCP) { 311 const std::vector<Constant*> &CP = MCP->getConstants(); 312 const TargetData &TD = TM.getTargetData(); 313 314 if (CP.empty()) return; 315 316 for (unsigned i = 0, e = CP.size(); i != e; ++i) { 317 O << "\t.section .rodata\n"; 318 O << "\t.align " << (unsigned)TD.getTypeAlignment(CP[i]->getType()) 319 << "\n"; 320 O << ".CPI" << CurrentFnName << "_" << i << ":\t\t\t\t\t#" 321 << *CP[i] << "\n"; 322 emitGlobalConstant(CP[i]); 323 } 324} 325 326/// runOnMachineFunction - This uses the printMachineInstruction() 327/// method to print assembly for each instruction. 328/// 329bool Printer::runOnMachineFunction(MachineFunction &MF) { 330 // BBNumber is used here so that a given Printer will never give two 331 // BBs the same name. (If you have a better way, please let me know!) 332 static unsigned BBNumber = 0; 333 334 O << "\n\n"; 335 // What's my mangled name? 336 CurrentFnName = Mang->getValueName(MF.getFunction()); 337 338 // Print out constants referenced by the function 339 printConstantPool(MF.getConstantPool()); 340 341 // Print out labels for the function. 342 O << "\t.text\n"; 343 O << "\t.align 16\n"; 344 O << "\t.globl\t" << CurrentFnName << "\n"; 345 if (!EmitCygwin) 346 O << "\t.type\t" << CurrentFnName << ", @function\n"; 347 O << CurrentFnName << ":\n"; 348 349 // Number each basic block so that we can consistently refer to them 350 // in PC-relative references. 351 NumberForBB.clear(); 352 for (MachineFunction::const_iterator I = MF.begin(), E = MF.end(); 353 I != E; ++I) { 354 NumberForBB[I->getBasicBlock()] = BBNumber++; 355 } 356 357 // Print out code for the function. 358 for (MachineFunction::const_iterator I = MF.begin(), E = MF.end(); 359 I != E; ++I) { 360 // Print a label for the basic block. 361 O << ".LBB" << NumberForBB[I->getBasicBlock()] << ":\t# " 362 << I->getBasicBlock()->getName() << "\n"; 363 for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end(); 364 II != E; ++II) { 365 // Print the assembly for the instruction. 366 O << "\t"; 367 printMachineInstruction(II); 368 } 369 } 370 371 // We didn't modify anything. 372 return false; 373} 374 375static bool isScale(const MachineOperand &MO) { 376 return MO.isImmediate() && 377 (MO.getImmedValue() == 1 || MO.getImmedValue() == 2 || 378 MO.getImmedValue() == 4 || MO.getImmedValue() == 8); 379} 380 381static bool isMem(const MachineInstr *MI, unsigned Op) { 382 if (MI->getOperand(Op).isFrameIndex()) return true; 383 if (MI->getOperand(Op).isConstantPoolIndex()) return true; 384 return Op+4 <= MI->getNumOperands() && 385 MI->getOperand(Op ).isRegister() &&isScale(MI->getOperand(Op+1)) && 386 MI->getOperand(Op+2).isRegister() &&MI->getOperand(Op+3).isImmediate(); 387} 388 389 390 391void Printer::printOp(const MachineOperand &MO, 392 bool elideOffsetKeyword /* = false */) { 393 const MRegisterInfo &RI = *TM.getRegisterInfo(); 394 switch (MO.getType()) { 395 case MachineOperand::MO_VirtualRegister: 396 if (Value *V = MO.getVRegValueOrNull()) { 397 O << "<" << V->getName() << ">"; 398 return; 399 } 400 // FALLTHROUGH 401 case MachineOperand::MO_MachineRegister: 402 if (MRegisterInfo::isPhysicalRegister(MO.getReg())) 403 // Bug Workaround: See note in Printer::doInitialization about %. 404 O << "%" << RI.get(MO.getReg()).Name; 405 else 406 O << "%reg" << MO.getReg(); 407 return; 408 409 case MachineOperand::MO_SignExtendedImmed: 410 case MachineOperand::MO_UnextendedImmed: 411 O << (int)MO.getImmedValue(); 412 return; 413 case MachineOperand::MO_PCRelativeDisp: { 414 ValueMapTy::const_iterator i = NumberForBB.find(MO.getVRegValue()); 415 assert (i != NumberForBB.end() 416 && "Could not find a BB in the NumberForBB map!"); 417 O << ".LBB" << i->second << " # PC rel: " << MO.getVRegValue()->getName(); 418 return; 419 } 420 case MachineOperand::MO_GlobalAddress: 421 if (!elideOffsetKeyword) 422 O << "OFFSET "; 423 O << Mang->getValueName(MO.getGlobal()); 424 return; 425 case MachineOperand::MO_ExternalSymbol: 426 O << MO.getSymbolName(); 427 return; 428 default: 429 O << "<unknown operand type>"; return; 430 } 431} 432 433static const std::string sizePtr(const TargetInstrDescriptor &Desc) { 434 switch (Desc.TSFlags & X86II::ArgMask) { 435 default: assert(0 && "Unknown arg size!"); 436 case X86II::Arg8: return "BYTE PTR"; 437 case X86II::Arg16: return "WORD PTR"; 438 case X86II::Arg32: return "DWORD PTR"; 439 case X86II::Arg64: return "QWORD PTR"; 440 case X86II::ArgF32: return "DWORD PTR"; 441 case X86II::ArgF64: return "QWORD PTR"; 442 case X86II::ArgF80: return "XWORD PTR"; 443 } 444} 445 446void Printer::printMemReference(const MachineInstr *MI, unsigned Op) { 447 assert(isMem(MI, Op) && "Invalid memory reference!"); 448 449 if (MI->getOperand(Op).isFrameIndex()) { 450 O << "[frame slot #" << MI->getOperand(Op).getFrameIndex(); 451 if (MI->getOperand(Op+3).getImmedValue()) 452 O << " + " << MI->getOperand(Op+3).getImmedValue(); 453 O << "]"; 454 return; 455 } else if (MI->getOperand(Op).isConstantPoolIndex()) { 456 O << "[.CPI" << CurrentFnName << "_" 457 << MI->getOperand(Op).getConstantPoolIndex(); 458 if (MI->getOperand(Op+3).getImmedValue()) 459 O << " + " << MI->getOperand(Op+3).getImmedValue(); 460 O << "]"; 461 return; 462 } 463 464 const MachineOperand &BaseReg = MI->getOperand(Op); 465 int ScaleVal = MI->getOperand(Op+1).getImmedValue(); 466 const MachineOperand &IndexReg = MI->getOperand(Op+2); 467 int DispVal = MI->getOperand(Op+3).getImmedValue(); 468 469 O << "["; 470 bool NeedPlus = false; 471 if (BaseReg.getReg()) { 472 printOp(BaseReg); 473 NeedPlus = true; 474 } 475 476 if (IndexReg.getReg()) { 477 if (NeedPlus) O << " + "; 478 if (ScaleVal != 1) 479 O << ScaleVal << "*"; 480 printOp(IndexReg); 481 NeedPlus = true; 482 } 483 484 if (DispVal) { 485 if (NeedPlus) 486 if (DispVal > 0) 487 O << " + "; 488 else { 489 O << " - "; 490 DispVal = -DispVal; 491 } 492 O << DispVal; 493 } 494 O << "]"; 495} 496 497/// checkImplUses - Emit the implicit-use registers for the 498/// instruction described by DESC, if its PrintImplUses flag is set. 499/// 500void Printer::checkImplUses (const TargetInstrDescriptor &Desc) { 501 const MRegisterInfo &RI = *TM.getRegisterInfo(); 502 if (Desc.TSFlags & X86II::PrintImplUses) { 503 for (const unsigned *p = Desc.ImplicitUses; *p; ++p) { 504 // Bug Workaround: See note in Printer::doInitialization about %. 505 O << ", %" << RI.get(*p).Name; 506 } 507 } 508} 509 510/// printMachineInstruction -- Print out a single X86 LLVM instruction 511/// MI in Intel syntax to the current output stream. 512/// 513void Printer::printMachineInstruction(const MachineInstr *MI) { 514 unsigned Opcode = MI->getOpcode(); 515 const TargetInstrInfo &TII = TM.getInstrInfo(); 516 const TargetInstrDescriptor &Desc = TII.get(Opcode); 517 518 ++EmittedInsts; 519 switch (Desc.TSFlags & X86II::FormMask) { 520 case X86II::Pseudo: 521 // Print pseudo-instructions as comments; either they should have been 522 // turned into real instructions by now, or they don't need to be 523 // seen by the assembler (e.g., IMPLICIT_USEs.) 524 O << "# "; 525 if (Opcode == X86::PHI) { 526 printOp(MI->getOperand(0)); 527 O << " = phi "; 528 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) { 529 if (i != 1) O << ", "; 530 O << "["; 531 printOp(MI->getOperand(i)); 532 O << ", "; 533 printOp(MI->getOperand(i+1)); 534 O << "]"; 535 } 536 } else { 537 unsigned i = 0; 538 if (MI->getNumOperands() && MI->getOperand(0).isDef()) { 539 printOp(MI->getOperand(0)); 540 O << " = "; 541 ++i; 542 } 543 O << TII.getName(MI->getOpcode()); 544 545 for (unsigned e = MI->getNumOperands(); i != e; ++i) { 546 O << " "; 547 if (MI->getOperand(i).isDef()) O << "*"; 548 printOp(MI->getOperand(i)); 549 if (MI->getOperand(i).isDef()) O << "*"; 550 } 551 } 552 O << "\n"; 553 return; 554 555 case X86II::RawFrm: 556 // The accepted forms of Raw instructions are: 557 // 1. nop - No operand required 558 // 2. jmp foo - PC relative displacement operand 559 // 3. call bar - GlobalAddress Operand or External Symbol Operand 560 // 561 assert(MI->getNumOperands() == 0 || 562 (MI->getNumOperands() == 1 && 563 (MI->getOperand(0).isPCRelativeDisp() || 564 MI->getOperand(0).isGlobalAddress() || 565 MI->getOperand(0).isExternalSymbol())) && 566 "Illegal raw instruction!"); 567 O << TII.getName(MI->getOpcode()) << " "; 568 569 if (MI->getNumOperands() == 1) { 570 printOp(MI->getOperand(0), true); // Don't print "OFFSET"... 571 } 572 O << "\n"; 573 return; 574 575 case X86II::AddRegFrm: { 576 // There are currently two forms of acceptable AddRegFrm instructions. 577 // Either the instruction JUST takes a single register (like inc, dec, etc), 578 // or it takes a register and an immediate of the same size as the register 579 // (move immediate f.e.). Note that this immediate value might be stored as 580 // an LLVM value, to represent, for example, loading the address of a global 581 // into a register. The initial register might be duplicated if this is a 582 // M_2_ADDR_REG instruction 583 // 584 assert(MI->getOperand(0).isRegister() && 585 (MI->getNumOperands() == 1 || 586 (MI->getNumOperands() == 2 && 587 (MI->getOperand(1).getVRegValueOrNull() || 588 MI->getOperand(1).isImmediate() || 589 MI->getOperand(1).isRegister() || 590 MI->getOperand(1).isGlobalAddress() || 591 MI->getOperand(1).isExternalSymbol()))) && 592 "Illegal form for AddRegFrm instruction!"); 593 594 unsigned Reg = MI->getOperand(0).getReg(); 595 596 O << TII.getName(MI->getOpcode()) << " "; 597 printOp(MI->getOperand(0)); 598 if (MI->getNumOperands() == 2 && 599 (!MI->getOperand(1).isRegister() || 600 MI->getOperand(1).getVRegValueOrNull() || 601 MI->getOperand(1).isGlobalAddress() || 602 MI->getOperand(1).isExternalSymbol())) { 603 O << ", "; 604 printOp(MI->getOperand(1)); 605 } 606 checkImplUses(Desc); 607 O << "\n"; 608 return; 609 } 610 case X86II::MRMDestReg: { 611 // There are three forms of MRMDestReg instructions, those with 2 612 // or 3 operands: 613 // 614 // 2 Operands: this is for things like mov that do not read a 615 // second input. 616 // 617 // 2 Operands: two address instructions which def&use the first 618 // argument and use the second as input. 619 // 620 // 3 Operands: in this form, two address instructions are the same 621 // as in 2 but have a constant argument as well. 622 // 623 bool isTwoAddr = TII.isTwoAddrInstr(Opcode); 624 assert(MI->getOperand(0).isRegister() && 625 (MI->getNumOperands() == 2 || 626 (MI->getNumOperands() == 3 && MI->getOperand(2).isImmediate())) 627 && "Bad format for MRMDestReg!"); 628 629 O << TII.getName(MI->getOpcode()) << " "; 630 printOp(MI->getOperand(0)); 631 O << ", "; 632 printOp(MI->getOperand(1)); 633 if (MI->getNumOperands() == 3) { 634 O << ", "; 635 printOp(MI->getOperand(2)); 636 } 637 O << "\n"; 638 return; 639 } 640 641 case X86II::MRMDestMem: { 642 // These instructions are the same as MRMDestReg, but instead of having a 643 // register reference for the mod/rm field, it's a memory reference. 644 // 645 assert(isMem(MI, 0) && 646 (MI->getNumOperands() == 4+1 || 647 (MI->getNumOperands() == 4+2 && MI->getOperand(5).isImmediate())) 648 && "Bad format for MRMDestMem!"); 649 650 O << TII.getName(MI->getOpcode()) << " " << sizePtr(Desc) << " "; 651 printMemReference(MI, 0); 652 O << ", "; 653 printOp(MI->getOperand(4)); 654 if (MI->getNumOperands() == 4+2) { 655 O << ", "; 656 printOp(MI->getOperand(5)); 657 } 658 O << "\n"; 659 return; 660 } 661 662 case X86II::MRMSrcReg: { 663 // There are three forms that are acceptable for MRMSrcReg 664 // instructions, those with 2 or 3 operands: 665 // 666 // 2 Operands: this is for things like mov that do not read a 667 // second input. 668 // 669 // 2 Operands: in this form, the last register is the ModR/M 670 // input. The first operand is a def&use. This is for things 671 // like: add r32, r/m32 672 // 673 // 3 Operands: in this form, we can have 'INST R1, R2, imm', which is used 674 // for instructions like the IMULrri instructions. 675 // 676 // 677 assert(MI->getOperand(0).isRegister() && 678 MI->getOperand(1).isRegister() && 679 (MI->getNumOperands() == 2 || 680 (MI->getNumOperands() == 3 && 681 (MI->getOperand(2).isImmediate()))) 682 && "Bad format for MRMSrcReg!"); 683 684 O << TII.getName(MI->getOpcode()) << " "; 685 printOp(MI->getOperand(0)); 686 O << ", "; 687 printOp(MI->getOperand(1)); 688 if (MI->getNumOperands() == 3) { 689 O << ", "; 690 printOp(MI->getOperand(2)); 691 } 692 O << "\n"; 693 return; 694 } 695 696 case X86II::MRMSrcMem: { 697 // These instructions are the same as MRMSrcReg, but instead of having a 698 // register reference for the mod/rm field, it's a memory reference. 699 // 700 assert(MI->getOperand(0).isRegister() && 701 (MI->getNumOperands() == 1+4 && isMem(MI, 1)) || 702(MI->getNumOperands() == 2+4 && MI->getOperand(5).isImmediate() && isMem(MI, 1)) 703 && "Bad format for MRMSrcMem!"); 704 O << TII.getName(MI->getOpcode()) << " "; 705 printOp(MI->getOperand(0)); 706 O << ", " << sizePtr(Desc) << " "; 707 printMemReference(MI, 1); 708 if (MI->getNumOperands() == 2+4) { 709 O << ", "; 710 printOp(MI->getOperand(5)); 711 } 712 O << "\n"; 713 return; 714 } 715 716 case X86II::MRMS0r: case X86II::MRMS1r: 717 case X86II::MRMS2r: case X86II::MRMS3r: 718 case X86II::MRMS4r: case X86II::MRMS5r: 719 case X86II::MRMS6r: case X86II::MRMS7r: { 720 // In this form, the following are valid formats: 721 // 1. sete r 722 // 2. cmp reg, immediate 723 // 2. shl rdest, rinput <implicit CL or 1> 724 // 3. sbb rdest, rinput, immediate [rdest = rinput] 725 // 726 assert(MI->getNumOperands() > 0 && MI->getNumOperands() < 4 && 727 MI->getOperand(0).isRegister() && "Bad MRMSxR format!"); 728 assert((MI->getNumOperands() != 2 || 729 MI->getOperand(1).isRegister() || MI->getOperand(1).isImmediate())&& 730 "Bad MRMSxR format!"); 731 assert((MI->getNumOperands() < 3 || 732 (MI->getOperand(1).isRegister() && MI->getOperand(2).isImmediate())) && 733 "Bad MRMSxR format!"); 734 735 if (MI->getNumOperands() > 1 && MI->getOperand(1).isRegister() && 736 MI->getOperand(0).getReg() != MI->getOperand(1).getReg()) 737 O << "**"; 738 739 O << TII.getName(MI->getOpcode()) << " "; 740 printOp(MI->getOperand(0)); 741 if (MI->getOperand(MI->getNumOperands()-1).isImmediate()) { 742 O << ", "; 743 printOp(MI->getOperand(MI->getNumOperands()-1)); 744 } 745 checkImplUses(Desc); 746 O << "\n"; 747 748 return; 749 } 750 751 case X86II::MRMS0m: case X86II::MRMS1m: 752 case X86II::MRMS2m: case X86II::MRMS3m: 753 case X86II::MRMS4m: case X86II::MRMS5m: 754 case X86II::MRMS6m: case X86II::MRMS7m: { 755 // In this form, the following are valid formats: 756 // 1. sete [m] 757 // 2. cmp [m], immediate 758 // 2. shl [m], rinput <implicit CL or 1> 759 // 3. sbb [m], immediate 760 // 761 assert(MI->getNumOperands() >= 4 && MI->getNumOperands() <= 5 && 762 isMem(MI, 0) && "Bad MRMSxM format!"); 763 assert((MI->getNumOperands() != 5 || 764 (MI->getOperand(4).isImmediate() || 765 MI->getOperand(4).isGlobalAddress())) && 766 "Bad MRMSxM format!"); 767 768 const MachineOperand &Op3 = MI->getOperand(3); 769 770 // Bug: The 80-bit FP store-pop instruction "fstp XWORD PTR [...]" 771 // is misassembled by gas in intel_syntax mode as its 32-bit 772 // equivalent "fstp DWORD PTR [...]". Workaround: Output the raw 773 // opcode bytes instead of the instruction. 774 if (MI->getOpcode() == X86::FSTPr80) { 775 if ((MI->getOperand(0).getReg() == X86::ESP) 776 && (MI->getOperand(1).getImmedValue() == 1)) { 777 if (Op3.isImmediate() && 778 Op3.getImmedValue() >= -128 && Op3.getImmedValue() <= 127) { 779 // 1 byte disp. 780 O << ".byte 0xdb, 0x7c, 0x24, 0x" << std::hex 781 << ((unsigned)Op3.getImmedValue() & 255) << std::dec << "\t# "; 782 } else { 783 O << ".byte 0xdb, 0xbc, 0x24\n\t"; 784 O << ".long "; 785 printOp(Op3); 786 O << "\t# "; 787 } 788 } 789 } 790 791 // Bug: The 80-bit FP load instruction "fld XWORD PTR [...]" is 792 // misassembled by gas in intel_syntax mode as its 32-bit 793 // equivalent "fld DWORD PTR [...]". Workaround: Output the raw 794 // opcode bytes instead of the instruction. 795 if (MI->getOpcode() == X86::FLDr80 && 796 MI->getOperand(0).getReg() == X86::ESP && 797 MI->getOperand(1).getImmedValue() == 1) { 798 if (Op3.isImmediate() && Op3.getImmedValue() >= -128 && 799 Op3.getImmedValue() <= 127) { // 1 byte displacement 800 O << ".byte 0xdb, 0x6c, 0x24, 0x" << std::hex 801 << ((unsigned)Op3.getImmedValue() & 255) << std::dec << "\t# "; 802 } else { 803 O << ".byte 0xdb, 0xac, 0x24\n\t"; 804 O << ".long "; 805 printOp(Op3); 806 O << "\t# "; 807 } 808 } 809 810 // Bug: gas intel_syntax mode treats "fild QWORD PTR [...]" as an 811 // invalid opcode, saying "64 bit operations are only supported in 812 // 64 bit modes." libopcodes disassembles it as "fild DWORD PTR 813 // [...]", which is wrong. Workaround: Output the raw opcode bytes 814 // instead of the instruction. 815 if (MI->getOpcode() == X86::FILDr64 && 816 MI->getOperand(0).getReg() == X86::ESP && 817 MI->getOperand(1).getImmedValue() == 1) { 818 if (Op3.isImmediate() && Op3.getImmedValue() >= -128 && 819 Op3.getImmedValue() <= 127) { // 1 byte displacement 820 O << ".byte 0xdf, 0x6c, 0x24, 0x" << std::hex 821 << ((unsigned)Op3.getImmedValue() & 255) << std::dec << "\t# "; 822 } else { 823 O << ".byte 0xdf, 0xac, 0x24\n\t"; 824 O << ".long "; 825 printOp(Op3); 826 O << std::dec << "\t# "; 827 } 828 } 829 830 // Bug: gas intel_syntax mode treats "fistp QWORD PTR [...]" as 831 // an invalid opcode, saying "64 bit operations are only 832 // supported in 64 bit modes." libopcodes disassembles it as 833 // "fistpll DWORD PTR [...]", which is wrong. Workaround: Output 834 // "fistpll DWORD PTR " instead, which is what libopcodes is 835 // expecting to see. 836 if (MI->getOpcode() == X86::FISTPr64) { 837 O << "fistpll DWORD PTR "; 838 printMemReference(MI, 0); 839 if (MI->getNumOperands() == 5) { 840 O << ", "; 841 printOp(MI->getOperand(4)); 842 } 843 O << "\t# "; 844 } 845 846 O << TII.getName(MI->getOpcode()) << " "; 847 O << sizePtr(Desc) << " "; 848 printMemReference(MI, 0); 849 if (MI->getNumOperands() == 5) { 850 O << ", "; 851 printOp(MI->getOperand(4)); 852 } 853 O << "\n"; 854 return; 855 } 856 857 default: 858 O << "\tUNKNOWN FORM:\t\t-"; MI->print(O, TM); break; 859 } 860} 861 862bool Printer::doInitialization(Module &M) { 863 // Tell gas we are outputting Intel syntax (not AT&T syntax) assembly. 864 // 865 // Bug: gas in `intel_syntax noprefix' mode interprets the symbol `Sp' in an 866 // instruction as a reference to the register named sp, and if you try to 867 // reference a symbol `Sp' (e.g. `mov ECX, OFFSET Sp') then it gets lowercased 868 // before being looked up in the symbol table. This creates spurious 869 // `undefined symbol' errors when linking. Workaround: Do not use `noprefix' 870 // mode, and decorate all register names with percent signs. 871 O << "\t.intel_syntax\n"; 872 Mang = new Mangler(M, EmitCygwin); 873 return false; // success 874} 875 876// SwitchSection - Switch to the specified section of the executable if we are 877// not already in it! 878// 879static void SwitchSection(std::ostream &OS, std::string &CurSection, 880 const char *NewSection) { 881 if (CurSection != NewSection) { 882 CurSection = NewSection; 883 if (!CurSection.empty()) 884 OS << "\t" << NewSection << "\n"; 885 } 886} 887 888bool Printer::doFinalization(Module &M) { 889 const TargetData &TD = TM.getTargetData(); 890 std::string CurSection; 891 892 // Print out module-level global variables here. 893 for (Module::const_giterator I = M.gbegin(), E = M.gend(); I != E; ++I) 894 if (I->hasInitializer()) { // External global require no code 895 O << "\n\n"; 896 std::string name = Mang->getValueName(I); 897 Constant *C = I->getInitializer(); 898 unsigned Size = TD.getTypeSize(C->getType()); 899 unsigned Align = TD.getTypeAlignment(C->getType()); 900 901 if (C->isNullValue() && 902 (I->hasLinkOnceLinkage() || I->hasInternalLinkage() || 903 I->hasWeakLinkage() /* FIXME: Verify correct */)) { 904 SwitchSection(O, CurSection, ".data"); 905 if (I->hasInternalLinkage()) 906 O << "\t.local " << name << "\n"; 907 908 O << "\t.comm " << name << "," << TD.getTypeSize(C->getType()) 909 << "," << (unsigned)TD.getTypeAlignment(C->getType()); 910 O << "\t\t# "; 911 WriteAsOperand(O, I, true, true, &M); 912 O << "\n"; 913 } else { 914 switch (I->getLinkage()) { 915 case GlobalValue::LinkOnceLinkage: 916 case GlobalValue::WeakLinkage: // FIXME: Verify correct for weak. 917 // Nonnull linkonce -> weak 918 O << "\t.weak " << name << "\n"; 919 SwitchSection(O, CurSection, ""); 920 O << "\t.section\t.llvm.linkonce.d." << name << ",\"aw\",@progbits\n"; 921 break; 922 923 case GlobalValue::AppendingLinkage: 924 // FIXME: appending linkage variables should go into a section of 925 // their name or something. For now, just emit them as external. 926 case GlobalValue::ExternalLinkage: 927 // If external or appending, declare as a global symbol 928 O << "\t.globl " << name << "\n"; 929 // FALL THROUGH 930 case GlobalValue::InternalLinkage: 931 if (C->isNullValue()) 932 SwitchSection(O, CurSection, ".bss"); 933 else 934 SwitchSection(O, CurSection, ".data"); 935 break; 936 } 937 938 O << "\t.align " << Align << "\n"; 939 O << "\t.type " << name << ",@object\n"; 940 O << "\t.size " << name << "," << Size << "\n"; 941 O << name << ":\t\t\t\t# "; 942 WriteAsOperand(O, I, true, true, &M); 943 O << " = "; 944 WriteAsOperand(O, C, false, false, &M); 945 O << "\n"; 946 emitGlobalConstant(C); 947 } 948 } 949 950 delete Mang; 951 return false; // success 952} 953