X86AsmPrinter.cpp revision c07736a397012499e337c994f7f952b07c709544
1//===-- X86/Printer.cpp - Convert X86 code to human readable rep. ---------===// 2// 3// This file contains a printer that converts from our internal representation 4// of LLVM code to a nice human readable form that is suitable for debugging. 5// 6//===----------------------------------------------------------------------===// 7 8#include "X86.h" 9#include "X86InstrInfo.h" 10#include "llvm/Function.h" 11#include "llvm/Constant.h" 12#include "llvm/Target/TargetMachine.h" 13#include "llvm/CodeGen/MachineFunctionPass.h" 14#include "llvm/CodeGen/MachineConstantPool.h" 15#include "llvm/CodeGen/MachineInstr.h" 16#include "Support/Statistic.h" 17#include "Support/hash_map" 18#include "llvm/Type.h" 19#include "llvm/Constants.h" 20#include "llvm/Assembly/Writer.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/SlotCalculator.h" 23#include "Support/StringExtras.h" 24#include "llvm/Module.h" 25 26namespace { 27 std::set<const Value *> MangledGlobals; 28 struct Printer : public MachineFunctionPass { 29 std::ostream &O; 30 typedef std::map<const Value *, unsigned> ValueMapTy; 31 ValueMapTy NumberForBB; 32 Printer(std::ostream &o) : O(o) {} 33 const TargetData *TD; 34 std::string CurrentFnName; 35 virtual const char *getPassName() const { 36 return "X86 Assembly Printer"; 37 } 38 39 void printMachineInstruction(const MachineInstr *MI, std::ostream &O, 40 const TargetMachine &TM) const; 41 void printOp(std::ostream &O, const MachineOperand &MO, 42 const MRegisterInfo &RI, bool elideOffsetKeyword = false) const; 43 void printMemReference(std::ostream &O, const MachineInstr *MI, 44 unsigned Op, 45 const MRegisterInfo &RI) const; 46 void printConstantPool(MachineConstantPool *MCP); 47 bool runOnMachineFunction(MachineFunction &F); 48 std::string ConstantExprToString(const ConstantExpr* CE); 49 std::string valToExprString(const Value* V); 50 bool doInitialization(Module &M); 51 bool doFinalization(Module &M); 52 void PrintZeroBytesToPad(int numBytes); 53 void printConstantValueOnly(const Constant* CV, int numPadBytesAfter = 0); 54 void printSingleConstantValue(const Constant* CV); 55 }; 56} // end of anonymous namespace 57 58/// createX86CodePrinterPass - Print out the specified machine code function to 59/// the specified stream. This function should work regardless of whether or 60/// not the function is in SSA form or not. 61/// 62Pass *createX86CodePrinterPass(std::ostream &O) { 63 return new Printer(O); 64} 65 66// We don't want identifier names with ., space, or - in them, 67// so we replace them with underscores. 68static std::string makeNameProper(std::string x) { 69 std::string tmp; 70 for (std::string::iterator sI = x.begin(), sEnd = x.end(); sI != sEnd; sI++) 71 switch (*sI) { 72 case '.': tmp += "d_"; break; 73 case ' ': tmp += "s_"; break; 74 case '-': tmp += "D_"; break; 75 default: tmp += *sI; 76 } 77 return tmp; 78} 79 80static std::string getValueName(const Value *V) { 81 if (V->hasName()) { // Print out the label if it exists... 82 // Name mangling occurs as follows: 83 // - If V is not a global, mangling always occurs. 84 // - Otherwise, mangling occurs when any of the following are true: 85 // 1) V has internal linkage 86 // 2) V's name would collide if it is not mangled. 87 // 88 if(const GlobalValue* gv = dyn_cast<GlobalValue>(V)) { 89 if(!gv->hasInternalLinkage() && !MangledGlobals.count(gv)) { 90 // No internal linkage, name will not collide -> no mangling. 91 return makeNameProper(gv->getName()); 92 } 93 } 94 // Non-global, or global with internal linkage / colliding name -> mangle. 95 return "l" + utostr(V->getType()->getUniqueID()) + "_" + 96 makeNameProper(V->getName()); 97 } 98 static int Count = 0; 99 Count++; 100 return "ltmp_" + itostr(Count) + "_" + utostr(V->getType()->getUniqueID()); 101} 102 103// valToExprString - Helper function for ConstantExprToString(). 104// Appends result to argument string S. 105// 106std::string Printer::valToExprString(const Value* V) { 107 std::string S; 108 bool failed = false; 109 if (const Constant* CV = dyn_cast<Constant>(V)) { // symbolic or known 110 if (const ConstantBool *CB = dyn_cast<ConstantBool>(CV)) 111 S += std::string(CB == ConstantBool::True ? "1" : "0"); 112 else if (const ConstantSInt *CI = dyn_cast<ConstantSInt>(CV)) 113 S += itostr(CI->getValue()); 114 else if (const ConstantUInt *CI = dyn_cast<ConstantUInt>(CV)) 115 S += utostr(CI->getValue()); 116 else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) 117 S += ftostr(CFP->getValue()); 118 else if (isa<ConstantPointerNull>(CV)) 119 S += "0"; 120 else if (const ConstantPointerRef *CPR = dyn_cast<ConstantPointerRef>(CV)) 121 S += valToExprString(CPR->getValue()); 122 else if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(CV)) 123 S += ConstantExprToString(CE); 124 else 125 failed = true; 126 } else if (const GlobalValue* GV = dyn_cast<GlobalValue>(V)) { 127 S += getValueName(GV); 128 } 129 else 130 failed = true; 131 132 if (failed) { 133 assert(0 && "Cannot convert value to string"); 134 S += "<illegal-value>"; 135 } 136 return S; 137} 138 139// ConstantExprToString() - Convert a ConstantExpr to an asm expression 140// and return this as a string. 141std::string Printer::ConstantExprToString(const ConstantExpr* CE) { 142 std::string S; 143 switch(CE->getOpcode()) { 144 case Instruction::GetElementPtr: 145 { // generate a symbolic expression for the byte address 146 const Value* ptrVal = CE->getOperand(0); 147 std::vector<Value*> idxVec(CE->op_begin()+1, CE->op_end()); 148 S += "(" + valToExprString(ptrVal) + ") + (" 149 + utostr(TD->getIndexedOffset(ptrVal->getType(),idxVec)) + ")"; 150 break; 151 } 152 153 case Instruction::Cast: 154 // Support only non-converting casts for now, i.e., a no-op. 155 // This assertion is not a complete check. 156 assert(TD->getTypeSize(CE->getType()) == 157 TD->getTypeSize(CE->getOperand(0)->getType())); 158 S += "(" + valToExprString(CE->getOperand(0)) + ")"; 159 break; 160 161 case Instruction::Add: 162 S += "(" + valToExprString(CE->getOperand(0)) + ") + (" 163 + valToExprString(CE->getOperand(1)) + ")"; 164 break; 165 166 default: 167 assert(0 && "Unsupported operator in ConstantExprToString()"); 168 break; 169 } 170 171 return S; 172} 173 174// Print a single constant value. 175void 176Printer::printSingleConstantValue(const Constant* CV) 177{ 178 assert(CV->getType() != Type::VoidTy && 179 CV->getType() != Type::TypeTy && 180 CV->getType() != Type::LabelTy && 181 "Unexpected type for Constant"); 182 183 assert((!isa<ConstantArray>(CV) && ! isa<ConstantStruct>(CV)) 184 && "Aggregate types should be handled outside this function"); 185 186 const Type *type = CV->getType(); 187 O << "\t"; 188 switch(type->getPrimitiveID()) 189 { 190 case Type::BoolTyID: case Type::UByteTyID: case Type::SByteTyID: 191 O << ".byte"; 192 break; 193 case Type::UShortTyID: case Type::ShortTyID: 194 O << ".word"; 195 break; 196 case Type::UIntTyID: case Type::IntTyID: case Type::PointerTyID: 197 O << ".long"; 198 break; 199 case Type::ULongTyID: case Type::LongTyID: 200 O << ".quad"; 201 break; 202 case Type::FloatTyID: 203 O << ".long"; 204 break; 205 case Type::DoubleTyID: 206 O << ".quad"; 207 break; 208 case Type::ArrayTyID: 209 if ((cast<ArrayType>(type)->getElementType() == Type::UByteTy) || 210 (cast<ArrayType>(type)->getElementType() == Type::SByteTy)) 211 O << ".string"; 212 else 213 assert (0 && "Can't handle printing this type of array"); 214 break; 215 default: 216 assert (0 && "Can't handle printing this type of thing"); 217 break; 218 } 219 O << "\t"; 220 221 if (type->isPrimitiveType()) 222 { 223 if (type->isFloatingPoint()) { 224 // FP Constants are printed as integer constants to avoid losing 225 // precision... 226 double Val = cast<ConstantFP>(CV)->getValue(); 227 if (type == Type::FloatTy) { 228 float FVal = (float)Val; 229 char *ProxyPtr = (char*)&FVal; // Abide by C TBAA rules 230 O << *(unsigned int*)ProxyPtr; 231 } else if (type == Type::DoubleTy) { 232 char *ProxyPtr = (char*)&Val; // Abide by C TBAA rules 233 O << *(uint64_t*)ProxyPtr; 234 } else { 235 assert(0 && "Unknown floating point type!"); 236 } 237 238 O << "\t# " << type->getDescription() << " value: " << Val << "\n"; 239 } else { 240 WriteAsOperand(O, CV, false, false) << "\n"; 241 } 242 } 243 else if (const ConstantPointerRef* CPR = dyn_cast<ConstantPointerRef>(CV)) 244 { 245 // This is a constant address for a global variable or method. 246 // Use the name of the variable or method as the address value. 247 O << getValueName(CPR->getValue()) << "\n"; 248 } 249 else if (isa<ConstantPointerNull>(CV)) 250 { 251 // Null pointer value 252 O << "0\n"; 253 } 254 else if (const ConstantExpr* CE = dyn_cast<ConstantExpr>(CV)) 255 { 256 // Constant expression built from operators, constants, and 257 // symbolic addrs 258 O << ConstantExprToString(CE) << "\n"; 259 } 260 else 261 { 262 assert(0 && "Unknown elementary type for constant"); 263 } 264} 265 266// Can we treat the specified array as a string? Only if it is an array of 267// ubytes or non-negative sbytes. 268// 269static bool isStringCompatible(const ConstantArray *CVA) { 270 const Type *ETy = cast<ArrayType>(CVA->getType())->getElementType(); 271 if (ETy == Type::UByteTy) return true; 272 if (ETy != Type::SByteTy) return false; 273 274 for (unsigned i = 0; i < CVA->getNumOperands(); ++i) 275 if (cast<ConstantSInt>(CVA->getOperand(i))->getValue() < 0) 276 return false; 277 278 return true; 279} 280 281// toOctal - Convert the low order bits of X into an octal letter 282static inline char toOctal(int X) { 283 return (X&7)+'0'; 284} 285 286// getAsCString - Return the specified array as a C compatible string, only if 287// the predicate isStringCompatible is true. 288// 289static std::string getAsCString(const ConstantArray *CVA) { 290 assert(isStringCompatible(CVA) && "Array is not string compatible!"); 291 292 std::string Result; 293 const Type *ETy = cast<ArrayType>(CVA->getType())->getElementType(); 294 Result = "\""; 295 for (unsigned i = 0; i < CVA->getNumOperands(); ++i) { 296 unsigned char C = cast<ConstantInt>(CVA->getOperand(i))->getRawValue(); 297 298 if (C == '"') { 299 Result += "\\\""; 300 } else if (C == '\\') { 301 Result += "\\\\"; 302 } else if (isprint(C)) { 303 Result += C; 304 } else { 305 switch(C) { 306 case '\a': Result += "\\a"; break; 307 case '\b': Result += "\\b"; break; 308 case '\f': Result += "\\f"; break; 309 case '\n': Result += "\\n"; break; 310 case '\r': Result += "\\r"; break; 311 case '\t': Result += "\\t"; break; 312 case '\v': Result += "\\v"; break; 313 default: 314 Result += '\\'; 315 Result += toOctal(C >> 6); 316 Result += toOctal(C >> 3); 317 Result += toOctal(C >> 0); 318 break; 319 } 320 } 321 } 322 Result += "\""; 323 return Result; 324} 325 326// Print a constant value or values (it may be an aggregate). 327// Uses printSingleConstantValue() to print each individual value. 328void 329Printer::printConstantValueOnly(const Constant* CV, 330 int numPadBytesAfter /* = 0 */) 331{ 332 const ConstantArray *CVA = dyn_cast<ConstantArray>(CV); 333 334 if (CVA && isStringCompatible(CVA)) 335 { // print the string alone and return 336 O << "\t" << ".string" << "\t" << getAsCString(CVA) << "\n"; 337 } 338 else if (CVA) 339 { // Not a string. Print the values in successive locations 340 const std::vector<Use> &constValues = CVA->getValues(); 341 for (unsigned i=0; i < constValues.size(); i++) 342 printConstantValueOnly(cast<Constant>(constValues[i].get())); 343 } 344 else if (const ConstantStruct *CVS = dyn_cast<ConstantStruct>(CV)) 345 { // Print the fields in successive locations. Pad to align if needed! 346 const StructLayout *cvsLayout = 347 TD->getStructLayout(CVS->getType()); 348 const std::vector<Use>& constValues = CVS->getValues(); 349 unsigned sizeSoFar = 0; 350 for (unsigned i=0, N = constValues.size(); i < N; i++) 351 { 352 const Constant* field = cast<Constant>(constValues[i].get()); 353 354 // Check if padding is needed and insert one or more 0s. 355 unsigned fieldSize = TD->getTypeSize(field->getType()); 356 int padSize = ((i == N-1? cvsLayout->StructSize 357 : cvsLayout->MemberOffsets[i+1]) 358 - cvsLayout->MemberOffsets[i]) - fieldSize; 359 sizeSoFar += (fieldSize + padSize); 360 361 // Now print the actual field value 362 printConstantValueOnly(field, padSize); 363 } 364 assert(sizeSoFar == cvsLayout->StructSize && 365 "Layout of constant struct may be incorrect!"); 366 } 367 else 368 printSingleConstantValue(CV); 369 370 if (numPadBytesAfter) { 371 unsigned numBytes = numPadBytesAfter; 372 for ( ; numBytes >= 8; numBytes -= 8) 373 printSingleConstantValue(Constant::getNullValue(Type::ULongTy)); 374 if (numBytes >= 4) 375 { 376 printSingleConstantValue(Constant::getNullValue(Type::UIntTy)); 377 numBytes -= 4; 378 } 379 while (numBytes--) 380 printSingleConstantValue(Constant::getNullValue(Type::UByteTy)); 381 } 382} 383 384// printConstantPool - Print out any constants which have been spilled to 385// memory... 386void Printer::printConstantPool(MachineConstantPool *MCP){ 387 const std::vector<Constant*> &CP = MCP->getConstants(); 388 if (CP.empty()) return; 389 390 for (unsigned i = 0, e = CP.size(); i != e; ++i) { 391 O << "\t.section .rodata\n"; 392 O << "\t.align " << (unsigned)TD->getTypeAlignment(CP[i]->getType()) 393 << "\n"; 394 O << ".CPI" << CurrentFnName << "_" << i << ":\t\t\t\t\t#" 395 << *CP[i] << "\n"; 396 printConstantValueOnly (CP[i]); 397 } 398} 399 400/// runOnMachineFunction - This uses the X86InstructionInfo::print method 401/// to print assembly for each instruction. 402bool Printer::runOnMachineFunction(MachineFunction &MF) { 403 static unsigned BBNumber = 0; 404 const TargetMachine &TM = MF.getTarget(); 405 const TargetInstrInfo &TII = TM.getInstrInfo(); 406 TD = &TM.getTargetData(); 407 408 // What's my mangled name? 409 CurrentFnName = getValueName(MF.getFunction()); 410 411 // Print out constants referenced by the function 412 printConstantPool(MF.getConstantPool()); 413 414 // Print out labels for the function. 415 O << "\t.text\n"; 416 O << "\t.align 16\n"; 417 O << "\t.globl\t" << CurrentFnName << "\n"; 418 O << "\t.type\t" << CurrentFnName << ", @function\n"; 419 O << CurrentFnName << ":\n"; 420 421 // Number each basic block so that we can consistently refer to them 422 // in PC-relative references. 423 NumberForBB.clear(); 424 for (MachineFunction::const_iterator I = MF.begin(), E = MF.end(); 425 I != E; ++I) { 426 NumberForBB[I->getBasicBlock()] = BBNumber++; 427 } 428 429 // Print out code for the function. 430 for (MachineFunction::const_iterator I = MF.begin(), E = MF.end(); 431 I != E; ++I) { 432 // Print a label for the basic block. 433 O << ".BB" << NumberForBB[I->getBasicBlock()] << ":\t# " 434 << I->getBasicBlock()->getName() << "\n"; 435 for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end(); 436 II != E; ++II) { 437 // Print the assembly for the instruction. 438 O << "\t"; 439 printMachineInstruction(*II, O, TM); 440 } 441 } 442 443 // We didn't modify anything. 444 return false; 445} 446 447static bool isScale(const MachineOperand &MO) { 448 return MO.isImmediate() && 449 (MO.getImmedValue() == 1 || MO.getImmedValue() == 2 || 450 MO.getImmedValue() == 4 || MO.getImmedValue() == 8); 451} 452 453static bool isMem(const MachineInstr *MI, unsigned Op) { 454 if (MI->getOperand(Op).isFrameIndex()) return true; 455 if (MI->getOperand(Op).isConstantPoolIndex()) return true; 456 return Op+4 <= MI->getNumOperands() && 457 MI->getOperand(Op ).isRegister() &&isScale(MI->getOperand(Op+1)) && 458 MI->getOperand(Op+2).isRegister() &&MI->getOperand(Op+3).isImmediate(); 459} 460 461void Printer::printOp(std::ostream &O, const MachineOperand &MO, 462 const MRegisterInfo &RI, 463 bool elideOffsetKeyword /* = false */) const { 464 switch (MO.getType()) { 465 case MachineOperand::MO_VirtualRegister: 466 if (Value *V = MO.getVRegValueOrNull()) { 467 O << "<" << V->getName() << ">"; 468 return; 469 } 470 // FALLTHROUGH 471 case MachineOperand::MO_MachineRegister: 472 if (MO.getReg() < MRegisterInfo::FirstVirtualRegister) 473 O << RI.get(MO.getReg()).Name; 474 else 475 O << "%reg" << MO.getReg(); 476 return; 477 478 case MachineOperand::MO_SignExtendedImmed: 479 case MachineOperand::MO_UnextendedImmed: 480 O << (int)MO.getImmedValue(); 481 return; 482 case MachineOperand::MO_PCRelativeDisp: 483 { 484 ValueMapTy::const_iterator i = NumberForBB.find(MO.getVRegValue()); 485 assert (i != NumberForBB.end() 486 && "Could not find a BB I previously put in the NumberForBB map!"); 487 O << ".BB" << i->second << " # PC rel: " << MO.getVRegValue()->getName(); 488 } 489 return; 490 case MachineOperand::MO_GlobalAddress: 491 if (!elideOffsetKeyword) O << "OFFSET "; O << getValueName(MO.getGlobal()); 492 return; 493 case MachineOperand::MO_ExternalSymbol: 494 O << MO.getSymbolName(); 495 return; 496 default: 497 O << "<unknown operand type>"; return; 498 } 499} 500 501static const std::string sizePtr(const TargetInstrDescriptor &Desc) { 502 switch (Desc.TSFlags & X86II::ArgMask) { 503 default: assert(0 && "Unknown arg size!"); 504 case X86II::Arg8: return "BYTE PTR"; 505 case X86II::Arg16: return "WORD PTR"; 506 case X86II::Arg32: return "DWORD PTR"; 507 case X86II::Arg64: return "QWORD PTR"; 508 case X86II::ArgF32: return "DWORD PTR"; 509 case X86II::ArgF64: return "QWORD PTR"; 510 case X86II::ArgF80: return "XWORD PTR"; 511 } 512} 513 514void Printer::printMemReference(std::ostream &O, const MachineInstr *MI, 515 unsigned Op, 516 const MRegisterInfo &RI) const { 517 assert(isMem(MI, Op) && "Invalid memory reference!"); 518 519 if (MI->getOperand(Op).isFrameIndex()) { 520 O << "[frame slot #" << MI->getOperand(Op).getFrameIndex(); 521 if (MI->getOperand(Op+3).getImmedValue()) 522 O << " + " << MI->getOperand(Op+3).getImmedValue(); 523 O << "]"; 524 return; 525 } else if (MI->getOperand(Op).isConstantPoolIndex()) { 526 O << "[.CPI" << CurrentFnName << "_" 527 << MI->getOperand(Op).getConstantPoolIndex(); 528 if (MI->getOperand(Op+3).getImmedValue()) 529 O << " + " << MI->getOperand(Op+3).getImmedValue(); 530 O << "]"; 531 return; 532 } 533 534 const MachineOperand &BaseReg = MI->getOperand(Op); 535 int ScaleVal = MI->getOperand(Op+1).getImmedValue(); 536 const MachineOperand &IndexReg = MI->getOperand(Op+2); 537 int DispVal = MI->getOperand(Op+3).getImmedValue(); 538 539 O << "["; 540 bool NeedPlus = false; 541 if (BaseReg.getReg()) { 542 printOp(O, BaseReg, RI); 543 NeedPlus = true; 544 } 545 546 if (IndexReg.getReg()) { 547 if (NeedPlus) O << " + "; 548 if (ScaleVal != 1) 549 O << ScaleVal << "*"; 550 printOp(O, IndexReg, RI); 551 NeedPlus = true; 552 } 553 554 if (DispVal) { 555 if (NeedPlus) 556 if (DispVal > 0) 557 O << " + "; 558 else { 559 O << " - "; 560 DispVal = -DispVal; 561 } 562 O << DispVal; 563 } 564 O << "]"; 565} 566 567/// printMachineInstruction -- Print out an x86 instruction in intel syntax 568/// 569void Printer::printMachineInstruction(const MachineInstr *MI, std::ostream &O, 570 const TargetMachine &TM) const { 571 unsigned Opcode = MI->getOpcode(); 572 const TargetInstrInfo &TII = TM.getInstrInfo(); 573 const TargetInstrDescriptor &Desc = TII.get(Opcode); 574 const MRegisterInfo &RI = *TM.getRegisterInfo(); 575 576 switch (Desc.TSFlags & X86II::FormMask) { 577 case X86II::Pseudo: 578 // Print pseudo-instructions as comments; either they should have been 579 // turned into real instructions by now, or they don't need to be 580 // seen by the assembler (e.g., IMPLICIT_USEs.) 581 O << "# "; 582 if (Opcode == X86::PHI) { 583 printOp(O, MI->getOperand(0), RI); 584 O << " = phi "; 585 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) { 586 if (i != 1) O << ", "; 587 O << "["; 588 printOp(O, MI->getOperand(i), RI); 589 O << ", "; 590 printOp(O, MI->getOperand(i+1), RI); 591 O << "]"; 592 } 593 } else { 594 unsigned i = 0; 595 if (MI->getNumOperands() && (MI->getOperand(0).opIsDefOnly() || 596 MI->getOperand(0).opIsDefAndUse())) { 597 printOp(O, MI->getOperand(0), RI); 598 O << " = "; 599 ++i; 600 } 601 O << TII.getName(MI->getOpcode()); 602 603 for (unsigned e = MI->getNumOperands(); i != e; ++i) { 604 O << " "; 605 if (MI->getOperand(i).opIsDefOnly() || 606 MI->getOperand(i).opIsDefAndUse()) O << "*"; 607 printOp(O, MI->getOperand(i), RI); 608 if (MI->getOperand(i).opIsDefOnly() || 609 MI->getOperand(i).opIsDefAndUse()) O << "*"; 610 } 611 } 612 O << "\n"; 613 return; 614 615 case X86II::RawFrm: 616 // The accepted forms of Raw instructions are: 617 // 1. nop - No operand required 618 // 2. jmp foo - PC relative displacement operand 619 // 3. call bar - GlobalAddress Operand or External Symbol Operand 620 // 621 assert(MI->getNumOperands() == 0 || 622 (MI->getNumOperands() == 1 && 623 (MI->getOperand(0).isPCRelativeDisp() || 624 MI->getOperand(0).isGlobalAddress() || 625 MI->getOperand(0).isExternalSymbol())) && 626 "Illegal raw instruction!"); 627 O << TII.getName(MI->getOpcode()) << " "; 628 629 if (MI->getNumOperands() == 1) { 630 printOp(O, MI->getOperand(0), RI, true); // Don't print "OFFSET"... 631 } 632 O << "\n"; 633 return; 634 635 case X86II::AddRegFrm: { 636 // There are currently two forms of acceptable AddRegFrm instructions. 637 // Either the instruction JUST takes a single register (like inc, dec, etc), 638 // or it takes a register and an immediate of the same size as the register 639 // (move immediate f.e.). Note that this immediate value might be stored as 640 // an LLVM value, to represent, for example, loading the address of a global 641 // into a register. The initial register might be duplicated if this is a 642 // M_2_ADDR_REG instruction 643 // 644 assert(MI->getOperand(0).isRegister() && 645 (MI->getNumOperands() == 1 || 646 (MI->getNumOperands() == 2 && 647 (MI->getOperand(1).getVRegValueOrNull() || 648 MI->getOperand(1).isImmediate() || 649 MI->getOperand(1).isRegister() || 650 MI->getOperand(1).isGlobalAddress() || 651 MI->getOperand(1).isExternalSymbol()))) && 652 "Illegal form for AddRegFrm instruction!"); 653 654 unsigned Reg = MI->getOperand(0).getReg(); 655 656 O << TII.getName(MI->getOpCode()) << " "; 657 printOp(O, MI->getOperand(0), RI); 658 if (MI->getNumOperands() == 2 && 659 (!MI->getOperand(1).isRegister() || 660 MI->getOperand(1).getVRegValueOrNull() || 661 MI->getOperand(1).isGlobalAddress() || 662 MI->getOperand(1).isExternalSymbol())) { 663 O << ", "; 664 printOp(O, MI->getOperand(1), RI); 665 } 666 if (Desc.TSFlags & X86II::PrintImplUses) { 667 for (const unsigned *p = Desc.ImplicitUses; *p; ++p) { 668 O << ", " << RI.get(*p).Name; 669 } 670 } 671 O << "\n"; 672 return; 673 } 674 case X86II::MRMDestReg: { 675 // There are two acceptable forms of MRMDestReg instructions, those with 2, 676 // 3 and 4 operands: 677 // 678 // 2 Operands: this is for things like mov that do not read a second input 679 // 680 // 3 Operands: in this form, the first two registers (the destination, and 681 // the first operand) should be the same, post register allocation. The 3rd 682 // operand is an additional input. This should be for things like add 683 // instructions. 684 // 685 // 4 Operands: This form is for instructions which are 3 operands forms, but 686 // have a constant argument as well. 687 // 688 bool isTwoAddr = TII.isTwoAddrInstr(Opcode); 689 assert(MI->getOperand(0).isRegister() && 690 (MI->getNumOperands() == 2 || 691 (isTwoAddr && MI->getOperand(1).isRegister() && 692 MI->getOperand(0).getReg() == MI->getOperand(1).getReg() && 693 (MI->getNumOperands() == 3 || 694 (MI->getNumOperands() == 4 && MI->getOperand(3).isImmediate())))) 695 && "Bad format for MRMDestReg!"); 696 697 O << TII.getName(MI->getOpCode()) << " "; 698 printOp(O, MI->getOperand(0), RI); 699 O << ", "; 700 printOp(O, MI->getOperand(1+isTwoAddr), RI); 701 if (MI->getNumOperands() == 4) { 702 O << ", "; 703 printOp(O, MI->getOperand(3), RI); 704 } 705 O << "\n"; 706 return; 707 } 708 709 case X86II::MRMDestMem: { 710 // These instructions are the same as MRMDestReg, but instead of having a 711 // register reference for the mod/rm field, it's a memory reference. 712 // 713 assert(isMem(MI, 0) && MI->getNumOperands() == 4+1 && 714 MI->getOperand(4).isRegister() && "Bad format for MRMDestMem!"); 715 716 O << TII.getName(MI->getOpCode()) << " " << sizePtr(Desc) << " "; 717 printMemReference(O, MI, 0, RI); 718 O << ", "; 719 printOp(O, MI->getOperand(4), RI); 720 O << "\n"; 721 return; 722 } 723 724 case X86II::MRMSrcReg: { 725 // There is a two forms that are acceptable for MRMSrcReg instructions, 726 // those with 3 and 2 operands: 727 // 728 // 3 Operands: in this form, the last register (the second input) is the 729 // ModR/M input. The first two operands should be the same, post register 730 // allocation. This is for things like: add r32, r/m32 731 // 732 // 2 Operands: this is for things like mov that do not read a second input 733 // 734 assert(MI->getOperand(0).isRegister() && 735 MI->getOperand(1).isRegister() && 736 (MI->getNumOperands() == 2 || 737 (MI->getNumOperands() == 3 && MI->getOperand(2).isRegister())) 738 && "Bad format for MRMSrcReg!"); 739 if (MI->getNumOperands() == 3 && 740 MI->getOperand(0).getReg() != MI->getOperand(1).getReg()) 741 O << "**"; 742 743 O << TII.getName(MI->getOpCode()) << " "; 744 printOp(O, MI->getOperand(0), RI); 745 O << ", "; 746 printOp(O, MI->getOperand(MI->getNumOperands()-1), RI); 747 O << "\n"; 748 return; 749 } 750 751 case X86II::MRMSrcMem: { 752 // These instructions are the same as MRMSrcReg, but instead of having a 753 // register reference for the mod/rm field, it's a memory reference. 754 // 755 assert(MI->getOperand(0).isRegister() && 756 (MI->getNumOperands() == 1+4 && isMem(MI, 1)) || 757 (MI->getNumOperands() == 2+4 && MI->getOperand(1).isRegister() && 758 isMem(MI, 2)) 759 && "Bad format for MRMDestReg!"); 760 if (MI->getNumOperands() == 2+4 && 761 MI->getOperand(0).getReg() != MI->getOperand(1).getReg()) 762 O << "**"; 763 764 O << TII.getName(MI->getOpCode()) << " "; 765 printOp(O, MI->getOperand(0), RI); 766 O << ", " << sizePtr(Desc) << " "; 767 printMemReference(O, MI, MI->getNumOperands()-4, RI); 768 O << "\n"; 769 return; 770 } 771 772 case X86II::MRMS0r: case X86II::MRMS1r: 773 case X86II::MRMS2r: case X86II::MRMS3r: 774 case X86II::MRMS4r: case X86II::MRMS5r: 775 case X86II::MRMS6r: case X86II::MRMS7r: { 776 // In this form, the following are valid formats: 777 // 1. sete r 778 // 2. cmp reg, immediate 779 // 2. shl rdest, rinput <implicit CL or 1> 780 // 3. sbb rdest, rinput, immediate [rdest = rinput] 781 // 782 assert(MI->getNumOperands() > 0 && MI->getNumOperands() < 4 && 783 MI->getOperand(0).isRegister() && "Bad MRMSxR format!"); 784 assert((MI->getNumOperands() != 2 || 785 MI->getOperand(1).isRegister() || MI->getOperand(1).isImmediate())&& 786 "Bad MRMSxR format!"); 787 assert((MI->getNumOperands() < 3 || 788 (MI->getOperand(1).isRegister() && MI->getOperand(2).isImmediate())) && 789 "Bad MRMSxR format!"); 790 791 if (MI->getNumOperands() > 1 && MI->getOperand(1).isRegister() && 792 MI->getOperand(0).getReg() != MI->getOperand(1).getReg()) 793 O << "**"; 794 795 O << TII.getName(MI->getOpCode()) << " "; 796 printOp(O, MI->getOperand(0), RI); 797 if (MI->getOperand(MI->getNumOperands()-1).isImmediate()) { 798 O << ", "; 799 printOp(O, MI->getOperand(MI->getNumOperands()-1), RI); 800 } 801 if (Desc.TSFlags & X86II::PrintImplUses) { 802 for (const unsigned *p = Desc.ImplicitUses; *p; ++p) { 803 O << ", " << RI.get(*p).Name; 804 } 805 } 806 O << "\n"; 807 808 return; 809 } 810 811 case X86II::MRMS0m: case X86II::MRMS1m: 812 case X86II::MRMS2m: case X86II::MRMS3m: 813 case X86II::MRMS4m: case X86II::MRMS5m: 814 case X86II::MRMS6m: case X86II::MRMS7m: { 815 // In this form, the following are valid formats: 816 // 1. sete [m] 817 // 2. cmp [m], immediate 818 // 2. shl [m], rinput <implicit CL or 1> 819 // 3. sbb [m], immediate 820 // 821 assert(MI->getNumOperands() >= 4 && MI->getNumOperands() <= 5 && 822 isMem(MI, 0) && "Bad MRMSxM format!"); 823 assert((MI->getNumOperands() != 5 || MI->getOperand(4).isImmediate()) && 824 "Bad MRMSxM format!"); 825 // Bug: The 80-bit FP store-pop instruction "fstp XWORD PTR [...]" 826 // is misassembled by gas in intel_syntax mode as its 32-bit 827 // equivalent "fstp DWORD PTR [...]". Workaround: Output the raw 828 // opcode bytes instead of the instruction. 829 if (MI->getOpCode() == X86::FSTPr80) { 830 if ((MI->getOperand(0).getReg() == X86::ESP) 831 && (MI->getOperand(1).getImmedValue() == 1)) { 832 int DispVal = MI->getOperand(3).getImmedValue(); 833 if ((DispVal < -128) || (DispVal > 127)) { // 4 byte disp. 834 unsigned int val = (unsigned int) DispVal; 835 O << ".byte 0xdb, 0xbc, 0x24\n\t"; 836 O << ".long 0x" << std::hex << (unsigned) val << std::dec << "\t# "; 837 } else { // 1 byte disp. 838 unsigned char val = (unsigned char) DispVal; 839 O << ".byte 0xdb, 0x7c, 0x24, 0x" << std::hex << (unsigned) val 840 << std::dec << "\t# "; 841 } 842 } 843 } 844 // Bug: The 80-bit FP load instruction "fld XWORD PTR [...]" is 845 // misassembled by gas in intel_syntax mode as its 32-bit 846 // equivalent "fld DWORD PTR [...]". Workaround: Output the raw 847 // opcode bytes instead of the instruction. 848 if (MI->getOpCode() == X86::FLDr80) { 849 if ((MI->getOperand(0).getReg() == X86::ESP) 850 && (MI->getOperand(1).getImmedValue() == 1)) { 851 int DispVal = MI->getOperand(3).getImmedValue(); 852 if ((DispVal < -128) || (DispVal > 127)) { // 4 byte disp. 853 unsigned int val = (unsigned int) DispVal; 854 O << ".byte 0xdb, 0xac, 0x24\n\t"; 855 O << ".long 0x" << std::hex << (unsigned) val << std::dec << "\t# "; 856 } else { // 1 byte disp. 857 unsigned char val = (unsigned char) DispVal; 858 O << ".byte 0xdb, 0x6c, 0x24, 0x" << std::hex << (unsigned) val 859 << std::dec << "\t# "; 860 } 861 } 862 } 863 // Bug: gas intel_syntax mode treats "fild QWORD PTR [...]" as an 864 // invalid opcode, saying "64 bit operations are only supported in 865 // 64 bit modes." libopcodes disassembles it as "fild DWORD PTR 866 // [...]", which is wrong. Workaround: Output the raw opcode bytes 867 // instead of the instruction. 868 if (MI->getOpCode() == X86::FILDr64) { 869 if ((MI->getOperand(0).getReg() == X86::ESP) 870 && (MI->getOperand(1).getImmedValue() == 1)) { 871 int DispVal = MI->getOperand(3).getImmedValue(); 872 if ((DispVal < -128) || (DispVal > 127)) { // 4 byte disp. 873 unsigned int val = (unsigned int) DispVal; 874 O << ".byte 0xdf, 0xac, 0x24\n\t"; 875 O << ".long 0x" << std::hex << (unsigned) val << std::dec << "\t# "; 876 } else { // 1 byte disp. 877 unsigned char val = (unsigned char) DispVal; 878 O << ".byte 0xdf, 0x6c, 0x24, 0x" << std::hex << (unsigned) val 879 << std::dec << "\t# "; 880 } 881 } 882 } 883 // Bug: gas intel_syntax mode treats "fistp QWORD PTR [...]" as 884 // an invalid opcode, saying "64 bit operations are only 885 // supported in 64 bit modes." libopcodes disassembles it as 886 // "fistpll DWORD PTR [...]", which is wrong. Workaround: Output 887 // "fistpll DWORD PTR " instead, which is what libopcodes is 888 // expecting to see. 889 if (MI->getOpCode() == X86::FISTPr64) { 890 O << "fistpll DWORD PTR "; 891 printMemReference(O, MI, 0, RI); 892 if (MI->getNumOperands() == 5) { 893 O << ", "; 894 printOp(O, MI->getOperand(4), RI); 895 } 896 O << "\t# "; 897 } 898 899 O << TII.getName(MI->getOpCode()) << " "; 900 O << sizePtr(Desc) << " "; 901 printMemReference(O, MI, 0, RI); 902 if (MI->getNumOperands() == 5) { 903 O << ", "; 904 printOp(O, MI->getOperand(4), RI); 905 } 906 O << "\n"; 907 return; 908 } 909 910 default: 911 O << "\tUNKNOWN FORM:\t\t-"; MI->print(O, TM); break; 912 } 913} 914 915bool Printer::doInitialization(Module &M) 916{ 917 // Tell gas we are outputting Intel syntax (not AT&T syntax) assembly, 918 // with no % decorations on register names. 919 O << "\t.intel_syntax noprefix\n"; 920 921 // Ripped from CWriter: 922 // Calculate which global values have names that will collide when we throw 923 // away type information. 924 { // Scope to delete the FoundNames set when we are done with it... 925 std::set<std::string> FoundNames; 926 for (Module::iterator I = M.begin(), E = M.end(); I != E; ++I) 927 if (I->hasName()) // If the global has a name... 928 if (FoundNames.count(I->getName())) // And the name is already used 929 MangledGlobals.insert(I); // Mangle the name 930 else 931 FoundNames.insert(I->getName()); // Otherwise, keep track of name 932 933 for (Module::giterator I = M.gbegin(), E = M.gend(); I != E; ++I) 934 if (I->hasName()) // If the global has a name... 935 if (FoundNames.count(I->getName())) // And the name is already used 936 MangledGlobals.insert(I); // Mangle the name 937 else 938 FoundNames.insert(I->getName()); // Otherwise, keep track of name 939 } 940 941 return false; // success 942} 943 944static const Function *isConstantFunctionPointerRef(const Constant *C) { 945 if (const ConstantPointerRef *R = dyn_cast<ConstantPointerRef>(C)) 946 if (const Function *F = dyn_cast<Function>(R->getValue())) 947 return F; 948 return 0; 949} 950 951bool Printer::doFinalization(Module &M) { 952 // Print out module-level global variables here. 953 for (Module::const_giterator I = M.gbegin(), E = M.gend(); I != E; ++I) { 954 std::string name(getValueName(I)); 955 if (I->hasInitializer()) { 956 Constant *C = I->getInitializer(); 957 O << "\t.data\n"; 958 O << "\t.globl " << name << "\n"; 959 O << "\t.type " << name << ",@object\n"; 960 O << "\t.size " << name << "," 961 << (unsigned)TD->getTypeSize(I->getType()) << "\n"; 962 O << "\t.align " << (unsigned)TD->getTypeAlignment(C->getType()) << "\n"; 963 O << name << ":\t\t\t\t\t#"; 964 // If this is a constant function pointer, we only print out the 965 // name of the function in the comment (because printing the 966 // function means calling AsmWriter to print the whole LLVM 967 // assembly, which would corrupt the X86 assembly output.) 968 // Otherwise we print out the whole llvm value as a comment. 969 if (const Function *F = isConstantFunctionPointerRef (C)) { 970 O << " %" << F->getName() << "()\n"; 971 } else { 972 O << *C << "\n"; 973 } 974 printConstantValueOnly (C); 975 } else { 976 O << "\t.globl " << name << "\n"; 977 O << "\t.comm " << name << ", " 978 << (unsigned)TD->getTypeSize(I->getType()) << ", " 979 << (unsigned)TD->getTypeAlignment(I->getType()) << "\n"; 980 } 981 } 982 MangledGlobals.clear(); 983 return false; // success 984} 985