int-conv-08.ll revision 88a9e6a0b313164009a32d7712c4dc95beb4bead 
1; Test zero extensions from a halfword to an i64.
2;
3; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
4
5; Test register extension, starting with an i32.
6define i64 @f1(i32 %a) {
7; CHECK: f1:
8; CHECK: llghr %r2, %r2
9; CHECK: br %r14
10  %half = trunc i32 %a to i16
11  %ext = zext i16 %half to i64
12  ret i64 %ext
13}
14
15; ...and again with an i64.
16define i64 @f2(i64 %a) {
17; CHECK: f2:
18; CHECK: llghr %r2, %r2
19; CHECK: br %r14
20  %half = trunc i64 %a to i16
21  %ext = zext i16 %half to i64
22  ret i64 %ext
23}
24
25; Check ANDs that are equivalent to zero extension.
26define i64 @f3(i64 %a) {
27; CHECK: f3:
28; CHECK: llghr %r2, %r2
29; CHECK: br %r14
30  %ext = and i64 %a, 65535
31  ret i64 %ext
32}
33
34; Check LLGH with no displacement.
35define i64 @f4(i16 *%src) {
36; CHECK: f4:
37; CHECK: llgh %r2, 0(%r2)
38; CHECK: br %r14
39  %half = load i16 *%src
40  %ext = zext i16 %half to i64
41  ret i64 %ext
42}
43
44; Check the high end of the LLGH range.
45define i64 @f5(i16 *%src) {
46; CHECK: f5:
47; CHECK: llgh %r2, 524286(%r2)
48; CHECK: br %r14
49  %ptr = getelementptr i16 *%src, i64 262143
50  %half = load i16 *%ptr
51  %ext = zext i16 %half to i64
52  ret i64 %ext
53}
54
55; Check the next halfword up, which needs separate address logic.
56; Other sequences besides this one would be OK.
57define i64 @f6(i16 *%src) {
58; CHECK: f6:
59; CHECK: agfi %r2, 524288
60; CHECK: llgh %r2, 0(%r2)
61; CHECK: br %r14
62  %ptr = getelementptr i16 *%src, i64 262144
63  %half = load i16 *%ptr
64  %ext = zext i16 %half to i64
65  ret i64 %ext
66}
67
68; Check the high end of the negative LLGH range.
69define i64 @f7(i16 *%src) {
70; CHECK: f7:
71; CHECK: llgh %r2, -2(%r2)
72; CHECK: br %r14
73  %ptr = getelementptr i16 *%src, i64 -1
74  %half = load i16 *%ptr
75  %ext = zext i16 %half to i64
76  ret i64 %ext
77}
78
79; Check the low end of the LLGH range.
80define i64 @f8(i16 *%src) {
81; CHECK: f8:
82; CHECK: llgh %r2, -524288(%r2)
83; CHECK: br %r14
84  %ptr = getelementptr i16 *%src, i64 -262144
85  %half = load i16 *%ptr
86  %ext = zext i16 %half to i64
87  ret i64 %ext
88}
89
90; Check the next halfword down, which needs separate address logic.
91; Other sequences besides this one would be OK.
92define i64 @f9(i16 *%src) {
93; CHECK: f9:
94; CHECK: agfi %r2, -524290
95; CHECK: llgh %r2, 0(%r2)
96; CHECK: br %r14
97  %ptr = getelementptr i16 *%src, i64 -262145
98  %half = load i16 *%ptr
99  %ext = zext i16 %half to i64
100  ret i64 %ext
101}
102
103; Check that LLGH allows an index
104define i64 @f10(i64 %src, i64 %index) {
105; CHECK: f10:
106; CHECK: llgh %r2, 524287(%r3,%r2)
107; CHECK: br %r14
108  %add1 = add i64 %src, %index
109  %add2 = add i64 %add1, 524287
110  %ptr = inttoptr i64 %add2 to i16 *
111  %half = load i16 *%ptr
112  %ext = zext i16 %half to i64
113  ret i64 %ext
114}
115