1; RUN: not llvm-mc -triple arm64-apple-darwin -show-encoding < %s 2> %t | FileCheck %s 2; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s 3 4foo: 5 6; The first should encode as an expression. The second should error expecting 7; a register. 8 ldr x3, (foo + 4) 9 ldr x3, [foo + 4] 10; CHECK: ldr x3, foo+4 ; encoding: [0bAAA00011,A,A,0x58] 11; CHECK: ; fixup A - offset: 0, value: foo+4, kind: fixup_aarch64_ldr_pcrel_imm19 12; CHECK-ERRORS: error: invalid operand for instruction 13 14; The last argument should be flagged as an error. rdar://9576009 15 ld4.8b {v0, v1, v2, v3}, [x0], #33 16; CHECK-ERRORS: error: invalid operand for instruction 17; CHECK-ERRORS: ld4.8b {v0, v1, v2, v3}, [x0], #33 18 19 20 ldr x0, [x0, #804] 21 ldr w0, [x0, #802] 22 ldr x0, [x0, #804]! 23 ldr w0, [w0, #301]! 24 ldr x0, [x0], #804 25 ldr w0, [w0], #301 26 27 ldp w3, w4, [x5, #11]! 28 ldp x3, x4, [x5, #12]! 29 ldp q3, q4, [x5, #12]! 30 ldp w3, w4, [x5], #11 31 ldp x3, x4, [x5], #12 32 ldp q3, q4, [x5], #12 33 34 ldur x0, [x1, #-257] 35 36; CHECK-ERRORS: error: index must be an integer in range [-256, 255]. 37; CHECK-ERRORS: ldr x0, [x0, #804] 38; CHECK-ERRORS: ^ 39; CHECK-ERRORS: error: index must be an integer in range [-256, 255]. 40; CHECK-ERRORS: ldr w0, [x0, #802] 41; CHECK-ERRORS: ^ 42; CHECK-ERRORS: error: index must be an integer in range [-256, 255]. 43; CHECK-ERRORS: ldr x0, [x0, #804]! 44; CHECK-ERRORS: ^ 45; CHECK-ERRORS: error: invalid operand for instruction 46; CHECK-ERRORS: ldr w0, [w0, #301]! 47; CHECK-ERRORS: ^ 48; CHECK-ERRORS: error: index must be an integer in range [-256, 255]. 49; CHECK-ERRORS: ldr x0, [x0], #804 50; CHECK-ERRORS: ^ 51; CHECK-ERRORS: error: invalid operand for instruction 52; CHECK-ERRORS: ldr w0, [w0], #301 53; CHECK-ERRORS: ^ 54; CHECK-ERRORS: error: index must be a multiple of 4 in range [-256, 252]. 55; CHECK-ERRORS: ldp w3, w4, [x5, #11]! 56; CHECK-ERRORS: ^ 57; CHECK-ERRORS: error: index must be a multiple of 8 in range [-512, 504]. 58; CHECK-ERRORS: ldp x3, x4, [x5, #12]! 59; CHECK-ERRORS: ^ 60; CHECK-ERRORS: error: index must be a multiple of 16 in range [-1024, 1008]. 61; CHECK-ERRORS: ldp q3, q4, [x5, #12]! 62; CHECK-ERRORS: ^ 63; CHECK-ERRORS: error: index must be a multiple of 4 in range [-256, 252]. 64; CHECK-ERRORS: ldp w3, w4, [x5], #11 65; CHECK-ERRORS: ^ 66; CHECK-ERRORS: error: index must be a multiple of 8 in range [-512, 504]. 67; CHECK-ERRORS: ldp x3, x4, [x5], #12 68; CHECK-ERRORS: ^ 69; CHECK-ERRORS: error: index must be a multiple of 16 in range [-1024, 1008]. 70; CHECK-ERRORS: ldp q3, q4, [x5], #12 71; CHECK-ERRORS: ^ 72; CHECK-ERRORS: error: index must be an integer in range [-256, 255]. 73; CHECK-ERRORS: ldur x0, [x1, #-257] 74; CHECK-ERRORS: ^ 75 76 77ldrb w1, [x3, w3, sxtw #4] 78ldrh w1, [x3, w3, sxtw #4] 79ldr w1, [x3, w3, sxtw #4] 80ldr x1, [x3, w3, sxtw #4] 81ldr b1, [x3, w3, sxtw #4] 82ldr h1, [x3, w3, sxtw #4] 83ldr s1, [x3, w3, sxtw #4] 84ldr d1, [x3, w3, sxtw #4] 85ldr q1, [x3, w3, sxtw #1] 86 87; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 88; CHECK-ERRORS:ldrb w1, [x3, w3, sxtw #4] 89; CHECK-ERRORS: ^ 90; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #1 91; CHECK-ERRORS:ldrh w1, [x3, w3, sxtw #4] 92; CHECK-ERRORS: ^ 93; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #2 94; CHECK-ERRORS:ldr w1, [x3, w3, sxtw #4] 95; CHECK-ERRORS: ^ 96; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #3 97; CHECK-ERRORS:ldr x1, [x3, w3, sxtw #4] 98; CHECK-ERRORS: ^ 99; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 100; CHECK-ERRORS:ldr b1, [x3, w3, sxtw #4] 101; CHECK-ERRORS: ^ 102; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #1 103; CHECK-ERRORS:ldr h1, [x3, w3, sxtw #4] 104; CHECK-ERRORS: ^ 105; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #2 106; CHECK-ERRORS:ldr s1, [x3, w3, sxtw #4] 107; CHECK-ERRORS: ^ 108; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #3 109; CHECK-ERRORS:ldr d1, [x3, w3, sxtw #4] 110; CHECK-ERRORS: ^ 111; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #4 112; CHECK-ERRORS:ldr q1, [x3, w3, sxtw #1] 113; CHECK-ERRORS: ^ 114 115; Check that register offset addressing modes only accept 32-bit offset 116; registers when using uxtw/sxtw extends. Everything else requires a 64-bit 117; register. 118 str d1, [x3, w3, sxtx #3] 119 ldr s1, [x3, d3, sxtx #2] 120 121; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #3 122; CHECK-ERRORS: str d1, [x3, w3, sxtx #3] 123; CHECK-ERRORS: ^ 124; CHECK-ERRORS: error: index must be an integer in range [-256, 255]. 125; CHECK-ERRORS: ldr s1, [x3, d3, sxtx #2] 126; CHECK-ERRORS: ^ 127 128; Shift immediates range checking. 129 sqrshrn b4, h9, #10 130 rshrn v9.8b, v11.8h, #17 131 sqrshrn v7.4h, v8.4s, #39 132 uqshrn2 v4.4s, v5.2d, #67 133 134; CHECK-ERRORS: error: immediate must be an integer in range [1, 8]. 135; CHECK-ERRORS: sqrshrn b4, h9, #10 136; CHECK-ERRORS: ^ 137; CHECK-ERRORS: error: immediate must be an integer in range [1, 8]. 138; CHECK-ERRORS: rshrn v9.8b, v11.8h, #17 139; CHECK-ERRORS: ^ 140; CHECK-ERRORS: error: immediate must be an integer in range [1, 16]. 141; CHECK-ERRORS: sqrshrn v7.4h, v8.4s, #39 142; CHECK-ERRORS: ^ 143; CHECK-ERRORS: error: immediate must be an integer in range [1, 32]. 144; CHECK-ERRORS: uqshrn2 v4.4s, v5.2d, #67 145; CHECK-ERRORS: ^ 146 147 148 st1.s4 {v14, v15}, [x2], #32 149; CHECK-ERRORS: error: invalid type suffix for instruction 150; CHECK-ERRORS: st1.s4 {v14, v15}, [x2], #32 151; CHECK-ERRORS: ^ 152 153 154 155; Load pair instructions where Rt==Rt2 and writeback load/store instructions 156; where Rt==Rn or Rt2==Rn are unpredicatable. 157 ldp x1, x2, [x2], #16 158 ldp x2, x2, [x2], #16 159 ldp w1, w2, [x2], #16 160 ldp w2, w2, [x2], #16 161 ldp x1, x1, [x2] 162 ldp s1, s1, [x1], #8 163 ldp s1, s1, [x1, #8]! 164 ldp s1, s1, [x1, #8] 165 ldp d1, d1, [x1], #16 166 ldp d1, d1, [x1, #16]! 167 ldp d1, d1, [x1, #16] 168 ldp q1, q1, [x1], #32 169 ldp q1, q1, [x1, #32]! 170 ldp q1, q1, [x1, #32] 171 172 ldr x2, [x2], #8 173 ldr x2, [x2, #8]! 174 ldr w2, [x2], #8 175 ldr w2, [x2, #8]! 176 177 str x2, [x2], #8 178 str x2, [x2, #8]! 179 str w2, [x2], #8 180 str w2, [x2, #8]! 181 182; CHECK-ERRORS: error: unpredictable LDP instruction, writeback base is also a destination 183; CHECK-ERRORS: ldp x1, x2, [x2], #16 184; CHECK-ERRORS: ^ 185; CHECK-ERRORS: error: unpredictable LDP instruction, writeback base is also a destination 186; CHECK-ERRORS: ldp x2, x2, [x2], #16 187; CHECK-ERRORS: ^ 188; CHECK-ERRORS: error: unpredictable LDP instruction, writeback base is also a destination 189; CHECK-ERRORS: ldp w1, w2, [x2], #16 190; CHECK-ERRORS: ^ 191; CHECK-ERRORS: error: unpredictable LDP instruction, writeback base is also a destination 192; CHECK-ERRORS: ldp w2, w2, [x2], #16 193; CHECK-ERRORS: ^ 194; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt 195; CHECK-ERRORS: ldp x1, x1, [x2] 196; CHECK-ERRORS: ^ 197; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt 198; CHECK-ERRORS: ldp s1, s1, [x1], #8 199; CHECK-ERRORS: ^ 200; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt 201; CHECK-ERRORS: ldp s1, s1, [x1, #8]! 202; CHECK-ERRORS: ^ 203; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt 204; CHECK-ERRORS: ldp s1, s1, [x1, #8] 205; CHECK-ERRORS: ^ 206; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt 207; CHECK-ERRORS: ldp d1, d1, [x1], #16 208; CHECK-ERRORS: ^ 209; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt 210; CHECK-ERRORS: ldp d1, d1, [x1, #16]! 211; CHECK-ERRORS: ^ 212; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt 213; CHECK-ERRORS: ldp d1, d1, [x1, #16] 214; CHECK-ERRORS: ^ 215; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt 216; CHECK-ERRORS: ldp q1, q1, [x1], #32 217; CHECK-ERRORS: ^ 218; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt 219; CHECK-ERRORS: ldp q1, q1, [x1, #32]! 220; CHECK-ERRORS: ^ 221; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt 222; CHECK-ERRORS: ldp q1, q1, [x1, #32] 223; CHECK-ERRORS: ^ 224; CHECK-ERRORS: error: unpredictable LDR instruction, writeback base is also a source 225; CHECK-ERRORS: ldr x2, [x2], #8 226; CHECK-ERRORS: ^ 227; CHECK-ERRORS: error: unpredictable LDR instruction, writeback base is also a source 228; CHECK-ERRORS: ldr x2, [x2, #8]! 229; CHECK-ERRORS: ^ 230; CHECK-ERRORS: error: unpredictable LDR instruction, writeback base is also a source 231; CHECK-ERRORS: ldr w2, [x2], #8 232; CHECK-ERRORS: ^ 233; CHECK-ERRORS: error: unpredictable LDR instruction, writeback base is also a source 234; CHECK-ERRORS: ldr w2, [x2, #8]! 235; CHECK-ERRORS: ^ 236; CHECK-ERRORS: error: unpredictable STR instruction, writeback base is also a source 237; CHECK-ERRORS: str x2, [x2], #8 238; CHECK-ERRORS: ^ 239; CHECK-ERRORS: error: unpredictable STR instruction, writeback base is also a source 240; CHECK-ERRORS: str x2, [x2, #8]! 241; CHECK-ERRORS: ^ 242; CHECK-ERRORS: error: unpredictable STR instruction, writeback base is also a source 243; CHECK-ERRORS: str w2, [x2], #8 244; CHECK-ERRORS: ^ 245; CHECK-ERRORS: error: unpredictable STR instruction, writeback base is also a source 246; CHECK-ERRORS: str w2, [x2, #8]! 247; CHECK-ERRORS: ^ 248 249; The validity checking for shifted-immediate operands. rdar://13174476 250; Where the immediate is out of range. 251 add w1, w2, w3, lsr #75 252 253; CHECK-ERRORS: error: expected 'sxtx' 'uxtx' or 'lsl' with optional integer in range [0, 4] 254; CHECK-ERRORS: add w1, w2, w3, lsr #75 255; CHECK-ERRORS: ^ 256 257; logical instructions on 32-bit regs with shift > 31 is not legal 258orr w0, w0, w0, lsl #32 259; CHECK-ERRORS: error: expected 'lsl', 'lsr' or 'asr' with optional integer in range [0, 31] 260; CHECK-ERRORS: orr w0, w0, w0, lsl #32 261; CHECK-ERRORS: ^ 262eor w0, w0, w0, lsl #32 263; CHECK-ERRORS: error: expected 'lsl', 'lsr' or 'asr' with optional integer in range [0, 31] 264; CHECK-ERRORS: eor w0, w0, w0, lsl #32 265; CHECK-ERRORS: ^ 266and w0, w0, w0, lsl #32 267; CHECK-ERRORS: error: expected 'lsl', 'lsr' or 'asr' with optional integer in range [0, 31] 268; CHECK-ERRORS: and w0, w0, w0, lsl #32 269; CHECK-ERRORS: ^ 270ands w0, w0, w0, lsl #32 271; CHECK-ERRORS: error: expected 'lsl', 'lsr' or 'asr' with optional integer in range [0, 31] 272; CHECK-ERRORS: ands w0, w0, w0, lsl #32 273; CHECK-ERRORS: ^ 274 275; Relocated expressions should not be accepted for 32-bit adds or sub (imm) 276add w3, w5, sym@PAGEOFF 277; CHECK-ERRORS: error: invalid immediate expression 278; CHECK-ERRORS: add w3, w5, sym@PAGEOFF 279; CHECK-ERRORS: ^ 280 281adds w3, w5, sym@PAGEOFF 282adds x9, x12, sym@PAGEOFF 283; CHECK-ERRORS: error: invalid immediate expression 284; CHECK-ERRORS: adds w3, w5, sym@PAGEOFF 285; CHECK-ERRORS: ^ 286; CHECK-ERRORS: error: invalid immediate expression 287; CHECK-ERRORS: adds x9, x12, sym@PAGEOFF 288; CHECK-ERRORS: ^ 289 290sub x3, x5, sym@PAGEOFF 291sub w20, w30, sym@PAGEOFF 292; CHECK-ERRORS: error: invalid immediate expression 293; CHECK-ERRORS: sub x3, x5, sym@PAGEOFF 294; CHECK-ERRORS: ^ 295; CHECK-ERRORS: error: invalid immediate expression 296; CHECK-ERRORS: sub w20, w30, sym@PAGEOFF 297; CHECK-ERRORS: ^ 298 299subs w9, w10, sym@PAGEOFF 300subs x20, x30, sym@PAGEOFF 301; CHECK-ERRORS: error: invalid immediate expression 302; CHECK-ERRORS: subs w9, w10, sym@PAGEOFF 303; CHECK-ERRORS: ^ 304; CHECK-ERRORS: error: invalid immediate expression 305; CHECK-ERRORS: subs x20, x30, sym@PAGEOFF 306; CHECK-ERRORS: ^ 307 308tbl v0.8b, { v1 }, v0.8b 309tbl v0.16b, { v1.8b, v2.8b, v3.8b }, v0.16b 310tbx v3.16b, { v12.8b, v13.8b, v14.8b }, v6.8b 311tbx v2.8b, { v0 }, v6.8b 312; CHECK-ERRORS: error: invalid operand for instruction 313; CHECK-ERRORS: tbl v0.8b, { v1 }, v0.8b 314; CHECK-ERRORS: ^ 315; CHECK-ERRORS: error: invalid operand for instruction 316; CHECK-ERRORS: tbl v0.16b, { v1.8b, v2.8b, v3.8b }, v0.16b 317; CHECK-ERRORS: ^ 318; CHECK-ERRORS: error: invalid operand for instruction 319; CHECK-ERRORS: tbx v3.16b, { v12.8b, v13.8b, v14.8b }, v6.8b 320; CHECK-ERRORS: ^ 321; CHECK-ERRORS: error: invalid operand for instruction 322; CHECK-ERRORS: tbx v2.8b, { v0 }, v6.8b 323; CHECK-ERRORS: ^ 324 325b.c #0x4 326; CHECK-ERRORS: error: invalid condition code 327; CHECK-ERRORS: b.c #0x4 328; CHECK-ERRORS: ^ 329 330ic ialluis, x0 331; CHECK-ERRORS: error: specified ic op does not use a register 332ic iallu, x0 333; CHECK-ERRORS: error: specified ic op does not use a register 334ic ivau 335; CHECK-ERRORS: error: specified ic op requires a register 336 337dc zva 338; CHECK-ERRORS: error: specified dc op requires a register 339dc ivac 340; CHECK-ERRORS: error: specified dc op requires a register 341dc isw 342; CHECK-ERRORS: error: specified dc op requires a register 343dc cvac 344; CHECK-ERRORS: error: specified dc op requires a register 345dc csw 346; CHECK-ERRORS: error: specified dc op requires a register 347dc cvau 348; CHECK-ERRORS: error: specified dc op requires a register 349dc civac 350; CHECK-ERRORS: error: specified dc op requires a register 351dc cisw 352; CHECK-ERRORS: error: specified dc op requires a register 353 354at s1e1r 355; CHECK-ERRORS: error: specified at op requires a register 356at s1e2r 357; CHECK-ERRORS: error: specified at op requires a register 358at s1e3r 359; CHECK-ERRORS: error: specified at op requires a register 360at s1e1w 361; CHECK-ERRORS: error: specified at op requires a register 362at s1e2w 363; CHECK-ERRORS: error: specified at op requires a register 364at s1e3w 365; CHECK-ERRORS: error: specified at op requires a register 366at s1e0r 367; CHECK-ERRORS: error: specified at op requires a register 368at s1e0w 369; CHECK-ERRORS: error: specified at op requires a register 370at s12e1r 371; CHECK-ERRORS: error: specified at op requires a register 372at s12e1w 373; CHECK-ERRORS: error: specified at op requires a register 374at s12e0r 375; CHECK-ERRORS: error: specified at op requires a register 376at s12e0w 377; CHECK-ERRORS: error: specified at op requires a register 378 379tlbi vmalle1is, x0 380; CHECK-ERRORS: error: specified tlbi op does not use a register 381tlbi vmalle1, x0 382; CHECK-ERRORS: error: specified tlbi op does not use a register 383tlbi alle1is, x0 384; CHECK-ERRORS: error: specified tlbi op does not use a register 385tlbi alle2is, x0 386; CHECK-ERRORS: error: specified tlbi op does not use a register 387tlbi alle3is, x0 388; CHECK-ERRORS: error: specified tlbi op does not use a register 389tlbi alle1, x0 390; CHECK-ERRORS: error: specified tlbi op does not use a register 391tlbi alle2, x0 392; CHECK-ERRORS: error: specified tlbi op does not use a register 393tlbi alle3, x0 394; CHECK-ERRORS: error: specified tlbi op does not use a register 395tlbi vae1is 396; CHECK-ERRORS: error: specified tlbi op requires a register 397tlbi vae2is 398; CHECK-ERRORS: error: specified tlbi op requires a register 399tlbi vae3is 400; CHECK-ERRORS: error: specified tlbi op requires a register 401tlbi aside1is 402; CHECK-ERRORS: error: specified tlbi op requires a register 403tlbi vaae1is 404; CHECK-ERRORS: error: specified tlbi op requires a register 405tlbi vale1is 406; CHECK-ERRORS: error: specified tlbi op requires a register 407tlbi vaale1is 408; CHECK-ERRORS: error: specified tlbi op requires a register 409tlbi vale2is 410; CHECK-ERRORS: error: specified tlbi op requires a register 411tlbi vale3is 412; CHECK-ERRORS: error: specified tlbi op requires a register 413tlbi vae1 414; CHECK-ERRORS: error: specified tlbi op requires a register 415tlbi vae2 416; CHECK-ERRORS: error: specified tlbi op requires a register 417tlbi vae3 418; CHECK-ERRORS: error: specified tlbi op requires a register 419tlbi aside1 420; CHECK-ERRORS: error: specified tlbi op requires a register 421tlbi vaae1 422; CHECK-ERRORS: error: specified tlbi op requires a register 423tlbi vale1 424; CHECK-ERRORS: error: specified tlbi op requires a register 425tlbi vale2 426; CHECK-ERRORS: error: specified tlbi op requires a register 427tlbi vale3 428; CHECK-ERRORS: error: specified tlbi op requires a register 429 430 431; Check that we give the proper "too few operands" diagnostic even when 432; using short-form NEON. 433 434 add.16b v0, v1, v2, v3 435 add.8b v0, v1 436 sub.8h v0, v1 437 fadd.4s v0 438 fmul.2s 439 440; CHECK-ERRORS: error: invalid operand for instruction 441; CHECK-ERRORS: add.16b v0, v1, v2, v3 442; CHECK-ERRORS: ^ 443; CHECK-ERRORS: error: too few operands for instruction 444; CHECK-ERRORS: add.8b v0, v1 445; CHECK-ERRORS: ^ 446; CHECK-ERRORS: error: too few operands for instruction 447; CHECK-ERRORS: sub.8h v0, v1 448; CHECK-ERRORS: ^ 449; CHECK-ERRORS: error: too few operands for instruction 450; CHECK-ERRORS: fadd.4s v0 451; CHECK-ERRORS: ^ 452; CHECK-ERRORS: error: too few operands for instruction 453; CHECK-ERRORS: fmul.2s 454; CHECK-ERRORS: ^ 455 456; Also for 2-operand instructions. 457 458 frsqrte.4s v0, v1, v2 459 frsqrte.2s v0 460 frecpe.2d 461 462; CHECK-ERRORS: error: invalid operand for instruction 463; CHECK-ERRORS: frsqrte.4s v0, v1, v2 464; CHECK-ERRORS: ^ 465; CHECK-ERRORS: error: too few operands for instruction 466; CHECK-ERRORS: frsqrte.2s v0 467; CHECK-ERRORS: ^ 468; CHECK-ERRORS: error: too few operands for instruction 469; CHECK-ERRORS: frecpe.2d 470; CHECK-ERRORS: ^ 471 472; And check that we do the same for non-NEON instructions. 473 474 b.ne 475 b.eq 0, 0 476 477; CHECK-ERRORS: error: too few operands for instruction 478; CHECK-ERRORS: b.ne 479; CHECK-ERRORS: ^ 480; CHECK-ERRORS: error: invalid operand for instruction 481; CHECK-ERRORS: b.eq 0, 0 482; CHECK-ERRORS: ^ 483 484; Check that we give the proper "too few operands" diagnostic instead of 485; asserting. 486 487 ldr 488 489; CHECK-ERRORS: error: too few operands for instruction 490; CHECK-ERRORS: ldr 491; CHECK-ERRORS: ^ 492