ilo_state_shader.c revision 0b6f6ee50f3b25c21dd8c9ca339d006141340666
1/* 2 * Mesa 3-D graphics library 3 * 4 * Copyright (C) 2012-2015 LunarG, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Chia-I Wu <olv@lunarg.com> 26 */ 27 28#include "ilo_debug.h" 29#include "ilo_state_shader.h" 30 31enum vertex_stage { 32 STAGE_VS, 33 STAGE_HS, 34 STAGE_DS, 35 STAGE_GS, 36}; 37 38struct vertex_ff { 39 uint8_t grf_start; 40 uint8_t scratch_space; 41 42 uint8_t sampler_count; 43 uint8_t surface_count; 44 bool has_uav; 45 46 uint8_t vue_read_offset; 47 uint8_t vue_read_len; 48 49 uint8_t user_clip_enables; 50}; 51 52static bool 53vertex_validate_gen6_kernel(const struct ilo_dev *dev, 54 enum vertex_stage stage, 55 const struct ilo_state_shader_kernel_info *kernel) 56{ 57 /* 58 * "Dispatch GRF Start Register for URB Data" is U4 for GS and U5 for 59 * others. 60 */ 61 const uint8_t max_grf_start = (stage == STAGE_GS) ? 16 : 32; 62 /* 63 * From the Sandy Bridge PRM, volume 2 part 1, page 134: 64 * 65 * "(Per-Thread Scratch Space) 66 * Range [0,11] indicating [1K Bytes, 2M Bytes]" 67 */ 68 const uint32_t max_scratch_size = 2 * 1024 * 1024; 69 70 ILO_DEV_ASSERT(dev, 6, 8); 71 72 /* we do not want to save it */ 73 assert(!kernel->offset); 74 75 assert(kernel->grf_start < max_grf_start); 76 assert(kernel->scratch_size <= max_scratch_size); 77 78 return true; 79} 80 81static bool 82vertex_validate_gen6_urb(const struct ilo_dev *dev, 83 enum vertex_stage stage, 84 const struct ilo_state_shader_urb_info *urb) 85{ 86 /* "Vertex/Patch URB Entry Read Offset" is U6, in pairs */ 87 const uint8_t max_read_base = 63 * 2; 88 /* 89 * "Vertex/Patch URB Entry Read Length" is limited to 64 for DS and U6 for 90 * others, in pairs 91 */ 92 const uint8_t max_read_count = ((stage == STAGE_DS) ? 64 : 63) * 2; 93 94 ILO_DEV_ASSERT(dev, 6, 8); 95 96 assert(urb->read_base + urb->read_count <= urb->cv_input_attr_count); 97 98 assert(urb->read_base % 2 == 0 && urb->read_base <= max_read_base); 99 100 /* 101 * There is no need to worry about reading past entries, as URB entries are 102 * aligned to 1024-bits (Gen6) or 512-bits (Gen7+). 103 */ 104 assert(urb->read_count <= max_read_count); 105 106 return true; 107} 108 109static bool 110vertex_get_gen6_ff(const struct ilo_dev *dev, 111 enum vertex_stage stage, 112 const struct ilo_state_shader_kernel_info *kernel, 113 const struct ilo_state_shader_resource_info *resource, 114 const struct ilo_state_shader_urb_info *urb, 115 struct vertex_ff *ff) 116{ 117 ILO_DEV_ASSERT(dev, 6, 8); 118 119 if (!vertex_validate_gen6_kernel(dev, stage, kernel) || 120 !vertex_validate_gen6_urb(dev, stage, urb)) 121 return false; 122 123 ff->grf_start = kernel->grf_start; 124 /* next power of two, starting from 1KB */ 125 ff->scratch_space = (kernel->scratch_size > 1024) ? 126 (util_last_bit(kernel->scratch_size - 1) - 10): 0; 127 128 ff->sampler_count = (resource->sampler_count <= 12) ? 129 (resource->sampler_count + 3) / 4 : 4; 130 ff->surface_count = resource->surface_count; 131 ff->has_uav = resource->has_uav; 132 133 ff->vue_read_offset = urb->read_base / 2; 134 ff->vue_read_len = (urb->read_count + 1) / 2; 135 136 /* need to read something unless VUE handles are included */ 137 switch (stage) { 138 case STAGE_VS: 139 if (!ff->vue_read_len) 140 ff->vue_read_len = 1; 141 142 /* one GRF per attribute */ 143 assert(kernel->grf_start + urb->read_count * 2 <= 128); 144 break; 145 case STAGE_GS: 146 if (ilo_dev_gen(dev) == ILO_GEN(6) && !ff->vue_read_len) 147 ff->vue_read_len = 1; 148 break; 149 default: 150 break; 151 } 152 153 ff->user_clip_enables = urb->user_clip_enables; 154 155 return true; 156} 157 158static uint16_t 159vs_get_gen6_thread_count(const struct ilo_dev *dev, 160 const struct ilo_state_vs_info *info) 161{ 162 uint16_t thread_count; 163 164 ILO_DEV_ASSERT(dev, 6, 8); 165 166 /* Maximum Number of Threads of 3DSTATE_VS */ 167 switch (ilo_dev_gen(dev)) { 168 case ILO_GEN(8): 169 thread_count = 504; 170 break; 171 case ILO_GEN(7.5): 172 thread_count = (dev->gt >= 2) ? 280 : 70; 173 break; 174 case ILO_GEN(7): 175 case ILO_GEN(6): 176 default: 177 thread_count = dev->thread_count; 178 break; 179 } 180 181 return thread_count - 1; 182} 183 184static bool 185vs_set_gen6_3DSTATE_VS(struct ilo_state_vs *vs, 186 const struct ilo_dev *dev, 187 const struct ilo_state_vs_info *info) 188{ 189 struct vertex_ff ff; 190 uint16_t thread_count; 191 uint32_t dw2, dw3, dw4, dw5; 192 193 ILO_DEV_ASSERT(dev, 6, 8); 194 195 if (!vertex_get_gen6_ff(dev, STAGE_VS, &info->kernel, 196 &info->resource, &info->urb, &ff)) 197 return false; 198 199 thread_count = vs_get_gen6_thread_count(dev, info); 200 201 dw2 = ff.sampler_count << GEN6_THREADDISP_SAMPLER_COUNT__SHIFT | 202 ff.surface_count << GEN6_THREADDISP_BINDING_TABLE_SIZE__SHIFT; 203 204 if (false) 205 dw2 |= GEN6_THREADDISP_FP_MODE_ALT; 206 207 if (ilo_dev_gen(dev) >= ILO_GEN(7.5) && ff.has_uav) 208 dw2 |= GEN75_THREADDISP_ACCESS_UAV; 209 210 dw3 = ff.scratch_space << GEN6_THREADSCRATCH_SPACE_PER_THREAD__SHIFT; 211 212 dw4 = ff.grf_start << GEN6_VS_DW4_URB_GRF_START__SHIFT | 213 ff.vue_read_len << GEN6_VS_DW4_URB_READ_LEN__SHIFT | 214 ff.vue_read_offset << GEN6_VS_DW4_URB_READ_OFFSET__SHIFT; 215 216 dw5 = 0; 217 218 if (ilo_dev_gen(dev) >= ILO_GEN(7.5)) 219 dw5 |= thread_count << GEN75_VS_DW5_MAX_THREADS__SHIFT; 220 else 221 dw5 |= thread_count << GEN6_VS_DW5_MAX_THREADS__SHIFT; 222 223 if (info->stats_enable) 224 dw5 |= GEN6_VS_DW5_STATISTICS; 225 if (info->dispatch_enable) 226 dw5 |= GEN6_VS_DW5_VS_ENABLE; 227 228 STATIC_ASSERT(ARRAY_SIZE(vs->vs) >= 5); 229 vs->vs[0] = dw2; 230 vs->vs[1] = dw3; 231 vs->vs[2] = dw4; 232 vs->vs[3] = dw5; 233 234 if (ilo_dev_gen(dev) >= ILO_GEN(8)) 235 vs->vs[4] = ff.user_clip_enables << GEN8_VS_DW8_UCP_CLIP_ENABLES__SHIFT; 236 237 return true; 238} 239 240static uint16_t 241hs_get_gen7_thread_count(const struct ilo_dev *dev, 242 const struct ilo_state_hs_info *info) 243{ 244 uint16_t thread_count; 245 246 ILO_DEV_ASSERT(dev, 7, 8); 247 248 /* Maximum Number of Threads of 3DSTATE_HS */ 249 switch (ilo_dev_gen(dev)) { 250 case ILO_GEN(8): 251 thread_count = 504; 252 break; 253 case ILO_GEN(7.5): 254 thread_count = (dev->gt >= 2) ? 256 : 70; 255 break; 256 case ILO_GEN(7): 257 default: 258 thread_count = dev->thread_count; 259 break; 260 } 261 262 return thread_count - 1; 263} 264 265static bool 266hs_set_gen7_3DSTATE_HS(struct ilo_state_hs *hs, 267 const struct ilo_dev *dev, 268 const struct ilo_state_hs_info *info) 269{ 270 struct vertex_ff ff; 271 uint16_t thread_count; 272 uint32_t dw1, dw2, dw4, dw5; 273 274 ILO_DEV_ASSERT(dev, 7, 8); 275 276 if (!vertex_get_gen6_ff(dev, STAGE_HS, &info->kernel, 277 &info->resource, &info->urb, &ff)) 278 return false; 279 280 thread_count = hs_get_gen7_thread_count(dev, info); 281 282 dw1 = ff.sampler_count << GEN6_THREADDISP_SAMPLER_COUNT__SHIFT | 283 ff.surface_count << GEN6_THREADDISP_BINDING_TABLE_SIZE__SHIFT; 284 285 dw2 = 0 << GEN7_HS_DW2_INSTANCE_COUNT__SHIFT; 286 287 if (ilo_dev_gen(dev) >= ILO_GEN(8)) 288 dw2 |= thread_count << GEN8_HS_DW2_MAX_THREADS__SHIFT; 289 else if (ilo_dev_gen(dev) >= ILO_GEN(7.5)) 290 dw1 |= thread_count << GEN75_HS_DW1_DISPATCH_MAX_THREADS__SHIFT; 291 else 292 dw1 |= thread_count << GEN7_HS_DW1_DISPATCH_MAX_THREADS__SHIFT; 293 294 if (info->dispatch_enable) 295 dw2 |= GEN7_HS_DW2_HS_ENABLE; 296 if (info->stats_enable) 297 dw2 |= GEN7_HS_DW2_STATISTICS; 298 299 dw4 = ff.scratch_space << GEN6_THREADSCRATCH_SPACE_PER_THREAD__SHIFT; 300 301 dw5 = GEN7_HS_DW5_INCLUDE_VERTEX_HANDLES | 302 ff.grf_start << GEN7_HS_DW5_URB_GRF_START__SHIFT | 303 ff.vue_read_len << GEN7_HS_DW5_URB_READ_LEN__SHIFT | 304 ff.vue_read_offset << GEN7_HS_DW5_URB_READ_OFFSET__SHIFT; 305 306 if (ilo_dev_gen(dev) >= ILO_GEN(7.5) && ff.has_uav) 307 dw5 |= GEN75_HS_DW5_ACCESS_UAV; 308 309 STATIC_ASSERT(ARRAY_SIZE(hs->hs) >= 4); 310 hs->hs[0] = dw1; 311 hs->hs[1] = dw2; 312 hs->hs[2] = dw4; 313 hs->hs[3] = dw5; 314 315 return true; 316} 317 318static bool 319ds_set_gen7_3DSTATE_TE(struct ilo_state_ds *ds, 320 const struct ilo_dev *dev, 321 const struct ilo_state_ds_info *info) 322{ 323 uint32_t dw1; 324 325 ILO_DEV_ASSERT(dev, 7, 8); 326 327 dw1 = 0; 328 329 if (info->dispatch_enable) { 330 dw1 |= GEN7_TE_DW1_MODE_HW | 331 GEN7_TE_DW1_TE_ENABLE; 332 } 333 334 STATIC_ASSERT(ARRAY_SIZE(ds->te) >= 3); 335 ds->te[0] = dw1; 336 ds->te[1] = fui(63.0f); 337 ds->te[2] = fui(64.0f); 338 339 return true; 340} 341 342static uint16_t 343ds_get_gen7_thread_count(const struct ilo_dev *dev, 344 const struct ilo_state_ds_info *info) 345{ 346 uint16_t thread_count; 347 348 ILO_DEV_ASSERT(dev, 7, 8); 349 350 /* Maximum Number of Threads of 3DSTATE_DS */ 351 switch (ilo_dev_gen(dev)) { 352 case ILO_GEN(8): 353 thread_count = 504; 354 break; 355 case ILO_GEN(7.5): 356 thread_count = (dev->gt >= 2) ? 280 : 70; 357 break; 358 case ILO_GEN(7): 359 default: 360 thread_count = dev->thread_count; 361 break; 362 } 363 364 return thread_count - 1; 365} 366 367static bool 368ds_set_gen7_3DSTATE_DS(struct ilo_state_ds *ds, 369 const struct ilo_dev *dev, 370 const struct ilo_state_ds_info *info) 371{ 372 struct vertex_ff ff; 373 uint16_t thread_count; 374 uint32_t dw2, dw3, dw4, dw5; 375 376 ILO_DEV_ASSERT(dev, 7, 8); 377 378 if (!vertex_get_gen6_ff(dev, STAGE_DS, &info->kernel, 379 &info->resource, &info->urb, &ff)) 380 return false; 381 382 thread_count = ds_get_gen7_thread_count(dev, info); 383 384 dw2 = ff.sampler_count << GEN6_THREADDISP_SAMPLER_COUNT__SHIFT | 385 ff.surface_count << GEN6_THREADDISP_BINDING_TABLE_SIZE__SHIFT; 386 387 if (ilo_dev_gen(dev) >= ILO_GEN(7.5) && ff.has_uav) 388 dw2 |= GEN75_THREADDISP_ACCESS_UAV; 389 390 dw3 = ff.scratch_space << GEN6_THREADSCRATCH_SPACE_PER_THREAD__SHIFT; 391 392 dw4 = ff.grf_start << GEN7_DS_DW4_URB_GRF_START__SHIFT | 393 ff.vue_read_len << GEN7_DS_DW4_URB_READ_LEN__SHIFT | 394 ff.vue_read_offset << GEN7_DS_DW4_URB_READ_OFFSET__SHIFT; 395 396 dw5 = 0; 397 398 if (ilo_dev_gen(dev) >= ILO_GEN(7.5)) 399 dw5 |= thread_count << GEN75_DS_DW5_MAX_THREADS__SHIFT; 400 else 401 dw5 |= thread_count << GEN7_DS_DW5_MAX_THREADS__SHIFT; 402 403 if (info->stats_enable) 404 dw5 |= GEN7_DS_DW5_STATISTICS; 405 if (info->dispatch_enable) 406 dw5 |= GEN7_DS_DW5_DS_ENABLE; 407 408 STATIC_ASSERT(ARRAY_SIZE(ds->ds) >= 5); 409 ds->ds[0] = dw2; 410 ds->ds[1] = dw3; 411 ds->ds[2] = dw4; 412 ds->ds[3] = dw5; 413 414 if (ilo_dev_gen(dev) >= ILO_GEN(8)) 415 ds->ds[4] = ff.user_clip_enables << GEN8_DS_DW8_UCP_CLIP_ENABLES__SHIFT; 416 417 return true; 418} 419 420static bool 421gs_get_gen6_ff(const struct ilo_dev *dev, 422 const struct ilo_state_gs_info *info, 423 struct vertex_ff *ff) 424{ 425 const struct ilo_state_shader_urb_info *urb = &info->urb; 426 const struct ilo_state_gs_sol_info *sol = &info->sol; 427 428 ILO_DEV_ASSERT(dev, 6, 8); 429 430 if (!vertex_get_gen6_ff(dev, STAGE_GS, &info->kernel, 431 &info->resource, &info->urb, ff)) 432 return false; 433 434 /* 435 * From the Ivy Bridge PRM, volume 2 part 1, page 168-169: 436 * 437 * "[0,62] indicating [1,63] 16B units" 438 * 439 * "Programming Restrictions: The vertex size must be programmed as a 440 * multiple of 32B units with the following exception: Rendering is 441 * disabled (as per SOL stage state) and the vertex size output by the 442 * GS thread is 16B. 443 * 444 * If rendering is enabled (as per SOL state) the vertex size must be 445 * programmed as a multiple of 32B units. In other words, the only 446 * time software can program a vertex size with an odd number of 16B 447 * units is when rendering is disabled." 448 */ 449 assert(urb->output_attr_count <= 63); 450 if (!sol->render_disable) 451 assert(urb->output_attr_count % 2 == 0); 452 453 return true; 454} 455 456static uint16_t 457gs_get_gen6_thread_count(const struct ilo_dev *dev, 458 const struct ilo_state_gs_info *info) 459{ 460 const struct ilo_state_gs_sol_info *sol = &info->sol; 461 uint16_t thread_count; 462 463 ILO_DEV_ASSERT(dev, 6, 8); 464 465 /* Maximum Number of Threads of 3DSTATE_GS */ 466 switch (ilo_dev_gen(dev)) { 467 case ILO_GEN(8): 468 thread_count = 504; 469 break; 470 case ILO_GEN(7.5): 471 thread_count = (dev->gt >= 2) ? 256 : 70; 472 break; 473 case ILO_GEN(7): 474 case ILO_GEN(6): 475 default: 476 thread_count = dev->thread_count; 477 478 /* 479 * From the Sandy Bridge PRM, volume 2 part 1, page 154: 480 * 481 * "Maximum Number of Threads valid range is [0,27] when Rendering 482 * Enabled bit is set." 483 * 484 * According to the classic driver, [0, 20] for GT1. 485 */ 486 if (!sol->render_disable) 487 thread_count = (dev->gt == 2) ? 27 : 20; 488 break; 489 } 490 491 return thread_count - 1; 492} 493 494static bool 495gs_set_gen6_3DSTATE_GS(struct ilo_state_gs *gs, 496 const struct ilo_dev *dev, 497 const struct ilo_state_gs_info *info) 498{ 499 const struct ilo_state_gs_sol_info *sol = &info->sol; 500 struct vertex_ff ff; 501 uint16_t thread_count; 502 uint32_t dw2, dw3, dw4, dw5, dw6; 503 504 ILO_DEV_ASSERT(dev, 6, 6); 505 506 if (!gs_get_gen6_ff(dev, info, &ff)) 507 return false; 508 509 thread_count = gs_get_gen6_thread_count(dev, info); 510 511 dw2 = GEN6_THREADDISP_SPF | 512 ff.sampler_count << GEN6_THREADDISP_SAMPLER_COUNT__SHIFT | 513 ff.surface_count << GEN6_THREADDISP_BINDING_TABLE_SIZE__SHIFT; 514 515 dw3 = ff.scratch_space << GEN6_THREADSCRATCH_SPACE_PER_THREAD__SHIFT; 516 517 dw4 = ff.vue_read_len << GEN6_GS_DW4_URB_READ_LEN__SHIFT | 518 ff.vue_read_offset << GEN6_GS_DW4_URB_READ_OFFSET__SHIFT | 519 ff.grf_start << GEN6_GS_DW4_URB_GRF_START__SHIFT; 520 521 dw5 = thread_count << GEN6_GS_DW5_MAX_THREADS__SHIFT; 522 523 if (info->stats_enable) 524 dw5 |= GEN6_GS_DW5_STATISTICS; 525 if (sol->stats_enable) 526 dw5 |= GEN6_GS_DW5_SO_STATISTICS; 527 if (!sol->render_disable) 528 dw5 |= GEN6_GS_DW5_RENDER_ENABLE; 529 530 dw6 = 0; 531 532 /* GEN7_REORDER_TRAILING is handled by the kernel */ 533 if (sol->tristrip_reorder == GEN7_REORDER_LEADING) 534 dw6 |= GEN6_GS_DW6_REORDER_LEADING_ENABLE; 535 536 if (sol->sol_enable) { 537 dw6 |= GEN6_GS_DW6_SVBI_PAYLOAD_ENABLE; 538 539 if (sol->svbi_post_inc) { 540 dw6 |= GEN6_GS_DW6_SVBI_POST_INC_ENABLE | 541 sol->svbi_post_inc << GEN6_GS_DW6_SVBI_POST_INC_VAL__SHIFT; 542 } 543 } 544 545 if (info->dispatch_enable) 546 dw6 |= GEN6_GS_DW6_GS_ENABLE; 547 548 STATIC_ASSERT(ARRAY_SIZE(gs->gs) >= 5); 549 gs->gs[0] = dw2; 550 gs->gs[1] = dw3; 551 gs->gs[2] = dw4; 552 gs->gs[3] = dw5; 553 gs->gs[4] = dw6; 554 555 return true; 556} 557 558static uint8_t 559gs_get_gen7_vertex_size(const struct ilo_dev *dev, 560 const struct ilo_state_gs_info *info) 561{ 562 const struct ilo_state_shader_urb_info *urb = &info->urb; 563 564 ILO_DEV_ASSERT(dev, 7, 8); 565 566 return (urb->output_attr_count) ? urb->output_attr_count - 1 : 0; 567} 568 569static bool 570gs_set_gen7_3DSTATE_GS(struct ilo_state_gs *gs, 571 const struct ilo_dev *dev, 572 const struct ilo_state_gs_info *info) 573{ 574 struct vertex_ff ff; 575 uint16_t thread_count; 576 uint8_t vertex_size; 577 uint32_t dw2, dw3, dw4, dw5; 578 579 ILO_DEV_ASSERT(dev, 7, 8); 580 581 if (!gs_get_gen6_ff(dev, info, &ff)) 582 return false; 583 584 thread_count = gs_get_gen6_thread_count(dev, info); 585 vertex_size = gs_get_gen7_vertex_size(dev, info); 586 587 dw2 = ff.sampler_count << GEN6_THREADDISP_SAMPLER_COUNT__SHIFT | 588 ff.surface_count << GEN6_THREADDISP_BINDING_TABLE_SIZE__SHIFT; 589 590 if (ilo_dev_gen(dev) >= ILO_GEN(7.5) && ff.has_uav) 591 dw2 |= GEN75_THREADDISP_ACCESS_UAV; 592 593 dw3 = ff.scratch_space << GEN6_THREADSCRATCH_SPACE_PER_THREAD__SHIFT; 594 595 dw4 = vertex_size << GEN7_GS_DW4_OUTPUT_SIZE__SHIFT | 596 0 << GEN7_GS_DW4_OUTPUT_TOPO__SHIFT | 597 ff.vue_read_len << GEN7_GS_DW4_URB_READ_LEN__SHIFT | 598 GEN7_GS_DW4_INCLUDE_VERTEX_HANDLES | 599 ff.vue_read_offset << GEN7_GS_DW4_URB_READ_OFFSET__SHIFT | 600 ff.grf_start << GEN7_GS_DW4_URB_GRF_START__SHIFT; 601 602 dw5 = 0; 603 604 if (ilo_dev_gen(dev) >= ILO_GEN(7.5)) 605 dw5 = thread_count << GEN75_GS_DW5_MAX_THREADS__SHIFT; 606 else 607 dw5 = thread_count << GEN7_GS_DW5_MAX_THREADS__SHIFT; 608 609 if (info->stats_enable) 610 dw5 |= GEN7_GS_DW5_STATISTICS; 611 if (info->dispatch_enable) 612 dw5 |= GEN7_GS_DW5_GS_ENABLE; 613 614 STATIC_ASSERT(ARRAY_SIZE(gs->gs) >= 5); 615 gs->gs[0] = dw2; 616 gs->gs[1] = dw3; 617 gs->gs[2] = dw4; 618 gs->gs[3] = dw5; 619 620 if (ilo_dev_gen(dev) >= ILO_GEN(8)) 621 gs->gs[4] = ff.user_clip_enables << GEN8_GS_DW9_UCP_CLIP_ENABLES__SHIFT; 622 623 return true; 624} 625 626bool 627ilo_state_vs_init(struct ilo_state_vs *vs, 628 const struct ilo_dev *dev, 629 const struct ilo_state_vs_info *info) 630{ 631 bool ret = true; 632 633 assert(ilo_is_zeroed(vs, sizeof(*vs))); 634 635 ret &= vs_set_gen6_3DSTATE_VS(vs, dev, info); 636 637 assert(ret); 638 639 return ret; 640} 641 642bool 643ilo_state_vs_init_disabled(struct ilo_state_vs *vs, 644 const struct ilo_dev *dev) 645{ 646 struct ilo_state_vs_info info; 647 648 memset(&info, 0, sizeof(info)); 649 650 return ilo_state_vs_init(vs, dev, &info); 651} 652 653bool 654ilo_state_hs_init(struct ilo_state_hs *hs, 655 const struct ilo_dev *dev, 656 const struct ilo_state_hs_info *info) 657{ 658 bool ret = true; 659 660 assert(ilo_is_zeroed(hs, sizeof(*hs))); 661 662 if (ilo_dev_gen(dev) >= ILO_GEN(7)) 663 ret &= hs_set_gen7_3DSTATE_HS(hs, dev, info); 664 665 assert(ret); 666 667 return ret; 668} 669 670bool 671ilo_state_hs_init_disabled(struct ilo_state_hs *hs, 672 const struct ilo_dev *dev) 673{ 674 struct ilo_state_hs_info info; 675 676 memset(&info, 0, sizeof(info)); 677 678 return ilo_state_hs_init(hs, dev, &info); 679} 680 681bool 682ilo_state_ds_init(struct ilo_state_ds *ds, 683 const struct ilo_dev *dev, 684 const struct ilo_state_ds_info *info) 685{ 686 bool ret = true; 687 688 assert(ilo_is_zeroed(ds, sizeof(*ds))); 689 690 if (ilo_dev_gen(dev) >= ILO_GEN(7)) { 691 ret &= ds_set_gen7_3DSTATE_TE(ds, dev, info); 692 ret &= ds_set_gen7_3DSTATE_DS(ds, dev, info); 693 } 694 695 assert(ret); 696 697 return ret; 698} 699 700bool 701ilo_state_ds_init_disabled(struct ilo_state_ds *ds, 702 const struct ilo_dev *dev) 703{ 704 struct ilo_state_ds_info info; 705 706 memset(&info, 0, sizeof(info)); 707 708 return ilo_state_ds_init(ds, dev, &info); 709} 710 711bool 712ilo_state_gs_init(struct ilo_state_gs *gs, 713 const struct ilo_dev *dev, 714 const struct ilo_state_gs_info *info) 715{ 716 bool ret = true; 717 718 assert(ilo_is_zeroed(gs, sizeof(*gs))); 719 720 if (ilo_dev_gen(dev) >= ILO_GEN(7)) 721 ret &= gs_set_gen7_3DSTATE_GS(gs, dev, info); 722 else 723 ret &= gs_set_gen6_3DSTATE_GS(gs, dev, info); 724 725 assert(ret); 726 727 return ret; 728} 729 730bool 731ilo_state_gs_init_disabled(struct ilo_state_gs *gs, 732 const struct ilo_dev *dev) 733{ 734 struct ilo_state_gs_info info; 735 736 memset(&info, 0, sizeof(info)); 737 738 return ilo_state_gs_init(gs, dev, &info); 739} 740