13ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu/* 23ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu * Mesa 3-D graphics library 33ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu * 43ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu * Copyright (C) 2012-2015 LunarG, Inc. 53ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu * 63ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu * Permission is hereby granted, free of charge, to any person obtaining a 73ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu * copy of this software and associated documentation files (the "Software"), 83ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu * to deal in the Software without restriction, including without limitation 93ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu * the rights to use, copy, modify, merge, publish, distribute, sublicense, 103ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu * and/or sell copies of the Software, and to permit persons to whom the 113ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu * Software is furnished to do so, subject to the following conditions: 123ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu * 133ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu * The above copyright notice and this permission notice shall be included 143ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu * in all copies or substantial portions of the Software. 153ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu * 163ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 173ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 183ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 193ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 203ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 213ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 223ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu * DEALINGS IN THE SOFTWARE. 233ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu * 243ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu * Authors: 253ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu * Chia-I Wu <olv@lunarg.com> 263ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu */ 273ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu 283ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu#include "ilo_debug.h" 2936d107e92cc4c1d2b60e0017dbe998af3a2e8b75Chia-I Wu#include "ilo_vma.h" 303ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu#include "ilo_state_sol.h" 313ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu 323ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wustatic bool 333ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wusol_stream_validate_gen7(const struct ilo_dev *dev, 343ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu const struct ilo_state_sol_stream_info *stream) 353ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu{ 363ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu uint8_t i; 373ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu 383ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu ILO_DEV_ASSERT(dev, 7, 8); 393ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu 403ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu assert(stream->vue_read_base + stream->vue_read_count <= 413ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu stream->cv_vue_attr_count); 423ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu 433ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu /* 443ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu * From the Ivy Bridge PRM, volume 2 part 1, page 200: 453ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu * 463ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu * "(Stream 0 Vertex Read Offset) 473ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu * Format: U1 count of 256-bit units 483ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu * 493ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu * Specifies amount of data to skip over before reading back Stream 0 503ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu * vertex data. Must be zero if the GS is enabled and the Output 513ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu * Vertex Size field in 3DSTATE_GS is programmed to 0 (i.e., one 16B 523ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu * unit)." 533ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu * 543ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu * "(Stream 0 Vertex Read Length) 553ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu * Format: U5-1 count of 256-bit units 563ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu * 573ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu * Specifies amount of vertex data to read back for Stream 0 vertices, 583ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu * starting at the Stream 0 Vertex Read Offset location. Maximum 593ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu * readback is 17 256-bit units (34 128-bit vertex attributes). Read 603ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu * data past the end of the valid vertex data has undefined contents, 613ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu * and therefore shouldn't be used to source stream out data. Must be 623ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu * zero (i.e., read length = 256b) if the GS is enabled and the Output 633ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu * Vertex Size field in 3DSTATE_GS is programmed to 0 (i.e., one 16B 643ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu * unit)." 653ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu */ 663ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu assert(stream->vue_read_base == 0 || stream->vue_read_base == 2); 673ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu assert(stream->vue_read_count <= 34); 683ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu 693ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu assert(stream->decl_count <= ILO_STATE_SOL_MAX_DECL_COUNT); 703ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu 713ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu for (i = 0; i < stream->decl_count; i++) { 723ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu const struct ilo_state_sol_decl_info *decl = &stream->decls[i]; 733ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu 743ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu assert(decl->is_hole || decl->attr < stream->vue_read_count); 753ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu 763ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu /* 773ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu * From the Ivy Bridge PRM, volume 2 part 1, page 205: 783ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu * 793ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu * "There is only enough internal storage for the 128-bit vertex 803ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu * header and 32 128-bit vertex attributes." 813ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu */ 823ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu assert(decl->attr < 33); 833ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu 843ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu assert(decl->component_base < 4 && 853ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu decl->component_base + decl->component_count <= 4); 863ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu assert(decl->buffer < ILO_STATE_SOL_MAX_BUFFER_COUNT); 873ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu } 883ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu 893ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu return true; 903ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu} 913ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu 923ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wustatic bool 933ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wusol_validate_gen7(const struct ilo_dev *dev, 943ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu const struct ilo_state_sol_info *info) 953ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu{ 963ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu uint8_t i; 973ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu 983ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu ILO_DEV_ASSERT(dev, 7, 8); 993ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu 1003ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu /* 1013ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu * From the Ivy Bridge PRM, volume 2 part 1, page 198: 1023ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu * 1033ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu * "This bit (Render Stream Select) is used even if SO Function Enable 1043ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu * is DISABLED." 1053ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu * 1063ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu * From the Haswell PRM, volume 2b, page 796: 1073ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu * 1083ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu * "SO Function Enable must also be ENABLED in order for thiis field 1093ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu * (Render Stream Select) to select a stream for rendering. When SO 1103ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu * Function Enable is DISABLED and Rendering Disable is cleared (i.e., 1113ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu * rendering is enabled), StreamID is ignored downstream of the SO 1123ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu * stage, allowing any stream to be rendered." 1133ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu * 1143ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu * We want Gen7 behavior, but we have to require users to follow Gen7.5 1153ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu * behavior: info->sol_enable must be set for info->render_stream to work. 1163ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu */ 1173ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu 1183ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu for (i = 0; i < ARRAY_SIZE(info->streams); i++) { 1193ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu if (!sol_stream_validate_gen7(dev, &info->streams[i])) 1203ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu return false; 1213ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu } 1223ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu 1233ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu /* 1243ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu * From the Ivy Bridge PRM, volume 2 part 1, page 208: 1253ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu * 1263ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu * "(Surface Pitch) 1273ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu * [0,2048] Must be 0 or a multiple of 4 Bytes." 1283ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu */ 1293ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu for (i = 0; i < ARRAY_SIZE(info->buffer_strides); i++) { 1303ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu assert(info->buffer_strides[i] <= 2048 && 1313ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu info->buffer_strides[i] % 4 == 0); 1323ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu } 1333ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu 1343ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu return true; 1353ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu} 1363ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu 1373ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wustatic bool 138e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wusol_set_gen7_3DSTATE_STREAMOUT(struct ilo_state_sol *sol, 1393ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu const struct ilo_dev *dev, 1403ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu const struct ilo_state_sol_info *info) 1413ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu{ 1423ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu struct { 1433ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu uint8_t offset; 1443ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu uint8_t len; 1453ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu } vue_read[ILO_STATE_SOL_MAX_STREAM_COUNT]; 1463ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu uint8_t i; 1473ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu uint32_t dw1, dw2; 1483ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu 1493ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu ILO_DEV_ASSERT(dev, 7, 8); 1503ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu 1513ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu if (!sol_validate_gen7(dev, info)) 1523ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu return false; 1533ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu 1543ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu for (i = 0; i < ARRAY_SIZE(info->streams); i++) { 1553ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu const struct ilo_state_sol_stream_info *stream = &info->streams[i]; 1563ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu 1573ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu vue_read[i].offset = stream->vue_read_base / 2; 1583ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu /* 1593ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu * In pairs minus 1. URB entries are aligned to 512-bits. There is no 1603ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu * need to worry about reading past entries. 1613ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu */ 1623ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu vue_read[i].len = (stream->vue_read_count + 1) / 2; 1633ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu if (vue_read[i].len) 1643ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu vue_read[i].len--; 1653ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu } 1663ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu 1673ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu dw1 = info->render_stream << GEN7_SO_DW1_RENDER_STREAM_SELECT__SHIFT | 1683ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu info->tristrip_reorder << GEN7_SO_DW1_REORDER_MODE__SHIFT; 1693ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu 1703ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu if (info->sol_enable) 1713ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu dw1 |= GEN7_SO_DW1_SO_ENABLE; 1723ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu 1733ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu if (info->render_disable) 1743ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu dw1 |= GEN7_SO_DW1_RENDER_DISABLE; 1753ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu 1763ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu if (info->stats_enable) 1773ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu dw1 |= GEN7_SO_DW1_STATISTICS; 1783ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu 1793ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu if (ilo_dev_gen(dev) < ILO_GEN(8)) { 180e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu const uint8_t buffer_enables = ((bool) info->buffer_strides[3]) << 3 | 181e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu ((bool) info->buffer_strides[2]) << 2 | 182e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu ((bool) info->buffer_strides[1]) << 1 | 183e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu ((bool) info->buffer_strides[0]); 1843ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu dw1 |= buffer_enables << GEN7_SO_DW1_BUFFER_ENABLES__SHIFT; 1853ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu } 1863ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu 1873ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu dw2 = vue_read[3].offset << GEN7_SO_DW2_STREAM3_READ_OFFSET__SHIFT | 1883ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu vue_read[3].len << GEN7_SO_DW2_STREAM3_READ_LEN__SHIFT | 1893ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu vue_read[2].offset << GEN7_SO_DW2_STREAM2_READ_OFFSET__SHIFT | 1903ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu vue_read[2].len << GEN7_SO_DW2_STREAM2_READ_LEN__SHIFT | 1913ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu vue_read[1].offset << GEN7_SO_DW2_STREAM1_READ_OFFSET__SHIFT | 1923ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu vue_read[1].len << GEN7_SO_DW2_STREAM1_READ_LEN__SHIFT | 1933ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu vue_read[0].offset << GEN7_SO_DW2_STREAM0_READ_OFFSET__SHIFT | 1943ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu vue_read[0].len << GEN7_SO_DW2_STREAM0_READ_LEN__SHIFT; 1953ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu 196e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu STATIC_ASSERT(ARRAY_SIZE(sol->streamout) >= 2); 197e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu sol->streamout[0] = dw1; 198e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu sol->streamout[1] = dw2; 1993ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu 200e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu memcpy(sol->strides, info->buffer_strides, sizeof(sol->strides)); 2013ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu 2023ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu return true; 2033ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu} 2043ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu 2053ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wustatic bool 206e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wusol_set_gen7_3DSTATE_SO_DECL_LIST(struct ilo_state_sol *sol, 2073ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu const struct ilo_dev *dev, 2083ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu const struct ilo_state_sol_info *info, 2093ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu uint8_t max_decl_count) 2103ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu{ 2113ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu uint64_t decl_list[ILO_STATE_SOL_MAX_DECL_COUNT]; 2123ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu uint8_t decl_counts[ILO_STATE_SOL_MAX_STREAM_COUNT]; 2133ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu uint8_t buffer_selects[ILO_STATE_SOL_MAX_STREAM_COUNT]; 2143ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu uint32_t dw1, dw2; 2153ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu uint8_t i, j; 2163ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu 2173ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu ILO_DEV_ASSERT(dev, 7, 8); 2183ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu 2193ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu memset(decl_list, 0, sizeof(decl_list[0]) * max_decl_count); 2203ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu 2213ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu for (i = 0; i < ARRAY_SIZE(info->streams); i++) { 2223ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu const struct ilo_state_sol_stream_info *stream = &info->streams[i]; 2233ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu 2243ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu assert(stream->decl_count <= max_decl_count); 2253ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu decl_counts[i] = stream->decl_count; 2263ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu buffer_selects[i] = 0; 2273ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu 2283ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu for (j = 0; j < stream->decl_count; j++) { 2293ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu const struct ilo_state_sol_decl_info *decl = &stream->decls[j]; 2303ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu const uint8_t mask = ((1 << decl->component_count) - 1) << 2313ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu decl->component_base; 2323ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu uint16_t val; 2333ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu 2343ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu val = decl->buffer << GEN7_SO_DECL_OUTPUT_SLOT__SHIFT | 2353ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu mask << GEN7_SO_DECL_COMPONENT_MASK__SHIFT; 2363ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu 2373ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu if (decl->is_hole) 2383ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu val |= GEN7_SO_DECL_HOLE_FLAG; 2393ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu else 2403ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu val |= decl->attr << GEN7_SO_DECL_REG_INDEX__SHIFT; 2413ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu 2423ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu decl_list[j] |= (uint64_t) val << (16 * i); 2433ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu buffer_selects[i] |= 1 << decl->buffer; 2443ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu } 2453ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu } 2463ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu 2473ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu dw1 = buffer_selects[3] << GEN7_SO_DECL_DW1_STREAM3_BUFFER_SELECTS__SHIFT | 2483ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu buffer_selects[2] << GEN7_SO_DECL_DW1_STREAM2_BUFFER_SELECTS__SHIFT | 2493ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu buffer_selects[1] << GEN7_SO_DECL_DW1_STREAM1_BUFFER_SELECTS__SHIFT | 2503ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu buffer_selects[0] << GEN7_SO_DECL_DW1_STREAM0_BUFFER_SELECTS__SHIFT; 2513ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu dw2 = decl_counts[3] << GEN7_SO_DECL_DW2_STREAM3_ENTRY_COUNT__SHIFT | 2523ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu decl_counts[2] << GEN7_SO_DECL_DW2_STREAM2_ENTRY_COUNT__SHIFT | 2533ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu decl_counts[1] << GEN7_SO_DECL_DW2_STREAM1_ENTRY_COUNT__SHIFT | 2543ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu decl_counts[0] << GEN7_SO_DECL_DW2_STREAM0_ENTRY_COUNT__SHIFT; 2553ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu 256e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu STATIC_ASSERT(ARRAY_SIZE(sol->so_decl) >= 2); 257e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu sol->so_decl[0] = dw1; 258e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu sol->so_decl[1] = dw2; 2593ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu 260e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu STATIC_ASSERT(ARRAY_SIZE(sol->decl[0]) == 2); 261e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu memcpy(sol->decl, decl_list, sizeof(sol->decl[0]) * max_decl_count); 262e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu sol->decl_count = max_decl_count; 263e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu 264e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu return true; 265e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu} 266e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu 267e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wustatic bool 268e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wusol_buffer_validate_gen7(const struct ilo_dev *dev, 269e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu const struct ilo_state_sol_buffer_info *info) 270e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu{ 271e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu ILO_DEV_ASSERT(dev, 7, 8); 272e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu 273e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu /* 274e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu * From the Ivy Bridge PRM, volume 2 part 1, page 208: 275e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu * 276e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu * "(Surface Base Address) This field specifies the starting DWord 277e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu * address..." 278e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu */ 279e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu assert(info->offset % 4 == 0); 280e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu 28136d107e92cc4c1d2b60e0017dbe998af3a2e8b75Chia-I Wu if (info->vma) { 28236d107e92cc4c1d2b60e0017dbe998af3a2e8b75Chia-I Wu assert(info->vma->vm_alignment % 4 == 0); 28336d107e92cc4c1d2b60e0017dbe998af3a2e8b75Chia-I Wu assert(info->size && info->offset + info->size <= info->vma->vm_size); 28436d107e92cc4c1d2b60e0017dbe998af3a2e8b75Chia-I Wu } 28536d107e92cc4c1d2b60e0017dbe998af3a2e8b75Chia-I Wu 286e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu /* Gen8+ only */ 28736d107e92cc4c1d2b60e0017dbe998af3a2e8b75Chia-I Wu if (info->write_offset_load || info->write_offset_save) { 28836d107e92cc4c1d2b60e0017dbe998af3a2e8b75Chia-I Wu assert(ilo_dev_gen(dev) >= ILO_GEN(8) && info->write_offset_vma); 28936d107e92cc4c1d2b60e0017dbe998af3a2e8b75Chia-I Wu assert(info->write_offset_offset + sizeof(uint32_t) <= 29036d107e92cc4c1d2b60e0017dbe998af3a2e8b75Chia-I Wu info->write_offset_vma->vm_size); 29136d107e92cc4c1d2b60e0017dbe998af3a2e8b75Chia-I Wu } 292e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu 293e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu /* 294e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu * From the Broadwell PRM, volume 2b, page 206: 295e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu * 296e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu * "This field (Stream Offset) specifies the Offset in stream output 297e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu * buffer to start at, or whether to append to the end of an existing 298e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu * buffer. The Offset must be DWORD aligned." 299e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu */ 300e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu if (info->write_offset_imm_enable) { 301e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu assert(info->write_offset_load); 302e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu assert(info->write_offset_imm % 4 == 0); 303e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu } 304e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu 305e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu return true; 306e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu} 307e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu 308e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wustatic uint32_t 309e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wusol_buffer_get_gen6_size(const struct ilo_dev *dev, 310e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu const struct ilo_state_sol_buffer_info *info) 311e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu{ 312e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu ILO_DEV_ASSERT(dev, 6, 8); 313e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu 314e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu /* 315e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu * From the Ivy Bridge PRM, volume 2 part 1, page 208: 316e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu * 317e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu * "(Surface End Address) This field specifies the ending DWord 318e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu * address..." 319e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu */ 32036d107e92cc4c1d2b60e0017dbe998af3a2e8b75Chia-I Wu return (info->vma) ? info->size & ~3 : 0; 321e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu} 322e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu 323e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wustatic bool 324e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wusol_buffer_set_gen7_3dstate_so_buffer(struct ilo_state_sol_buffer *sb, 325e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu const struct ilo_dev *dev, 326e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu const struct ilo_state_sol_buffer_info *info) 327e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu{ 328e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu const uint32_t size = sol_buffer_get_gen6_size(dev, info); 329e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu 330e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu ILO_DEV_ASSERT(dev, 7, 7.5); 331e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu 332e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu if (!sol_buffer_validate_gen7(dev, info)) 333e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu return false; 334e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu 335e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu STATIC_ASSERT(ARRAY_SIZE(sb->so_buf) >= 2); 336e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu sb->so_buf[0] = info->offset; 337e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu sb->so_buf[1] = (size) ? info->offset + size : 0; 338e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu 339e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu return true; 340e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu} 341e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu 342e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wustatic bool 343e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wusol_buffer_set_gen8_3dstate_so_buffer(struct ilo_state_sol_buffer *sb, 344e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu const struct ilo_dev *dev, 345e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu const struct ilo_state_sol_buffer_info *info) 346e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu{ 347e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu const uint32_t size = sol_buffer_get_gen6_size(dev, info); 348e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu uint32_t dw1; 349e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu 350e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu ILO_DEV_ASSERT(dev, 8, 8); 351e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu 352e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu if (!sol_buffer_validate_gen7(dev, info)) 353e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu return false; 354e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu 355e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu dw1 = 0; 356e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu 35736d107e92cc4c1d2b60e0017dbe998af3a2e8b75Chia-I Wu if (info->vma) 358e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu dw1 |= GEN8_SO_BUF_DW1_ENABLE; 359e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu if (info->write_offset_load) 360e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu dw1 |= GEN8_SO_BUF_DW1_OFFSET_WRITE_ENABLE; 361e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu if (info->write_offset_save) 362e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu dw1 |= GEN8_SO_BUF_DW1_OFFSET_ENABLE; 363e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu 364e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu STATIC_ASSERT(ARRAY_SIZE(sb->so_buf) >= 4); 365e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu sb->so_buf[0] = dw1; 366e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu sb->so_buf[1] = info->offset; 367e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu 368e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu /* 369e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu * From the Broadwell PRM, volume 2b, page 205: 370e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu * 371e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu * "This field (Surface Size) specifies the size of buffer in number 372e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu * DWords minus 1 of the buffer in Graphics Memory." 373e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu */ 374e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu sb->so_buf[2] = (size) ? size / 4 - 1 : 0; 375e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu 376e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu /* load from imm or sb->write_offset_bo */ 377e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu sb->so_buf[3] = (info->write_offset_imm_enable) ? 378e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu info->write_offset_imm : ~0u; 3793ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu 3803ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu return true; 3813ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu} 3823ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu 3833ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wubool 384e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wuilo_state_sol_init(struct ilo_state_sol *sol, 3853ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu const struct ilo_dev *dev, 3863ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu const struct ilo_state_sol_info *info) 3873ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu{ 3883ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu bool ret = true; 3893ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu 390e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu assert(ilo_is_zeroed(sol, sizeof(*sol))); 3913ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu assert(ilo_is_zeroed(info->data, info->data_size)); 3923ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu 3933ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu if (ilo_dev_gen(dev) >= ILO_GEN(7)) { 3943ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu uint8_t max_decl_count, i; 3953ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu 3963ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu max_decl_count = info->streams[0].decl_count; 3973ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu for (i = 1; i < ARRAY_SIZE(info->streams); i++) { 3983ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu if (max_decl_count < info->streams[i].decl_count) 3993ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu max_decl_count = info->streams[i].decl_count; 4003ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu } 4013ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu 4023ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu assert(ilo_state_sol_data_size(dev, max_decl_count) <= info->data_size); 403e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu sol->decl = (uint32_t (*)[2]) info->data; 4043ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu 405e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu ret &= sol_set_gen7_3DSTATE_STREAMOUT(sol, dev, info); 406e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu ret &= sol_set_gen7_3DSTATE_SO_DECL_LIST(sol, dev, info, max_decl_count); 4073ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu } 4083ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu 4093ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu assert(ret); 4103ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu 4113ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu return ret; 4123ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu} 4133ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu 4143ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wubool 4153ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wuilo_state_sol_init_disabled(struct ilo_state_sol *sol, 4163ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu const struct ilo_dev *dev, 4173ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu bool render_disable) 4183ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu{ 4193ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu struct ilo_state_sol_info info; 4203ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu 4213ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu memset(&info, 0, sizeof(info)); 4223ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu info.render_disable = render_disable; 4233ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu 4243ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu return ilo_state_sol_init(sol, dev, &info); 4253ff40be0eecfd6bbcc17471590e44042b3ffa5d3Chia-I Wu} 426e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu 4279871646c132ba137709b0bfebfe285985dc351e6Chia-I Wuuint32_t 4289871646c132ba137709b0bfebfe285985dc351e6Chia-I Wuilo_state_sol_buffer_size(const struct ilo_dev *dev, uint32_t size, 4299871646c132ba137709b0bfebfe285985dc351e6Chia-I Wu uint32_t *alignment) 4309871646c132ba137709b0bfebfe285985dc351e6Chia-I Wu{ 4319871646c132ba137709b0bfebfe285985dc351e6Chia-I Wu /* DWord aligned without padding */ 4329871646c132ba137709b0bfebfe285985dc351e6Chia-I Wu *alignment = 4; 4339871646c132ba137709b0bfebfe285985dc351e6Chia-I Wu return size; 4349871646c132ba137709b0bfebfe285985dc351e6Chia-I Wu} 4359871646c132ba137709b0bfebfe285985dc351e6Chia-I Wu 436e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wubool 437e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wuilo_state_sol_buffer_init(struct ilo_state_sol_buffer *sb, 438e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu const struct ilo_dev *dev, 439e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu const struct ilo_state_sol_buffer_info *info) 440e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu{ 441e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu bool ret = true; 442e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu 443e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu assert(ilo_is_zeroed(sb, sizeof(*sb))); 444e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu 445e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu if (ilo_dev_gen(dev) >= ILO_GEN(8)) 446e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu ret &= sol_buffer_set_gen8_3dstate_so_buffer(sb, dev, info); 447e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu else 448e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu ret &= sol_buffer_set_gen7_3dstate_so_buffer(sb, dev, info); 449e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu 45036d107e92cc4c1d2b60e0017dbe998af3a2e8b75Chia-I Wu sb->vma = info->vma; 45136d107e92cc4c1d2b60e0017dbe998af3a2e8b75Chia-I Wu sb->write_offset_vma = info->write_offset_vma; 452e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu 453e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu assert(ret); 454e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu 455e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu return ret; 456e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu} 457e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu 458e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wubool 459e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wuilo_state_sol_buffer_init_disabled(struct ilo_state_sol_buffer *sb, 460e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu const struct ilo_dev *dev) 461e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu{ 462e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu struct ilo_state_sol_buffer_info info; 463e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu 464e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu memset(&info, 0, sizeof(info)); 465e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu 466e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu return ilo_state_sol_buffer_init(sb, dev, &info); 467e3372c4bfb8d5960714651ca7d3f1acc0018a8faChia-I Wu} 468