1/* 2 * Copyright 2011 Christoph Bumiller 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23#include "codegen/nv50_ir_target_nvc0.h" 24 25namespace nv50_ir { 26 27Target *getTargetNVC0(unsigned int chipset) 28{ 29 return new TargetNVC0(chipset); 30} 31 32TargetNVC0::TargetNVC0(unsigned int card) : 33 Target(card < 0x110, false, card >= 0xe4) 34{ 35 chipset = card; 36 initOpInfo(); 37} 38 39// BULTINS / LIBRARY FUNCTIONS: 40 41// lazyness -> will just hardcode everything for the time being 42 43#include "lib/gf100.asm.h" 44#include "lib/gk104.asm.h" 45#include "lib/gk110.asm.h" 46 47void 48TargetNVC0::getBuiltinCode(const uint32_t **code, uint32_t *size) const 49{ 50 switch (chipset & ~0xf) { 51 case 0xe0: 52 if (chipset < NVISA_GK20A_CHIPSET) { 53 *code = (const uint32_t *)&gk104_builtin_code[0]; 54 *size = sizeof(gk104_builtin_code); 55 break; 56 } 57 /* fall-through for GK20A */ 58 case 0xf0: 59 case 0x100: 60 *code = (const uint32_t *)&gk110_builtin_code[0]; 61 *size = sizeof(gk110_builtin_code); 62 break; 63 default: 64 *code = (const uint32_t *)&gf100_builtin_code[0]; 65 *size = sizeof(gf100_builtin_code); 66 break; 67 } 68} 69 70uint32_t 71TargetNVC0::getBuiltinOffset(int builtin) const 72{ 73 assert(builtin < NVC0_BUILTIN_COUNT); 74 75 switch (chipset & ~0xf) { 76 case 0xe0: 77 if (chipset < NVISA_GK20A_CHIPSET) 78 return gk104_builtin_offsets[builtin]; 79 /* fall-through for GK20A */ 80 case 0xf0: 81 case 0x100: 82 return gk110_builtin_offsets[builtin]; 83 default: 84 return gf100_builtin_offsets[builtin]; 85 } 86} 87 88struct opProperties 89{ 90 operation op; 91 unsigned int mNeg : 4; 92 unsigned int mAbs : 4; 93 unsigned int mNot : 4; 94 unsigned int mSat : 4; 95 unsigned int fConst : 3; 96 unsigned int fImmd : 4; // last bit indicates if full immediate is suppoted 97}; 98 99static const struct opProperties _initProps[] = 100{ 101 // neg abs not sat c[] imm 102 { OP_ADD, 0x3, 0x3, 0x0, 0x8, 0x2, 0x2 | 0x8 }, 103 { OP_SUB, 0x3, 0x3, 0x0, 0x0, 0x2, 0x2 | 0x8 }, 104 { OP_MUL, 0x3, 0x0, 0x0, 0x8, 0x2, 0x2 | 0x8 }, 105 { OP_MAX, 0x3, 0x3, 0x0, 0x0, 0x2, 0x2 }, 106 { OP_MIN, 0x3, 0x3, 0x0, 0x0, 0x2, 0x2 }, 107 { OP_MAD, 0x7, 0x0, 0x0, 0x8, 0x6, 0x2 | 0x8 }, // special c[] constraint 108 { OP_FMA, 0x7, 0x0, 0x0, 0x8, 0x6, 0x2 | 0x8 }, // keep the same as OP_MAD 109 { OP_SHLADD, 0x5, 0x0, 0x0, 0x0, 0x4, 0x6 }, 110 { OP_MADSP, 0x0, 0x0, 0x0, 0x0, 0x6, 0x2 }, 111 { OP_ABS, 0x0, 0x0, 0x0, 0x0, 0x1, 0x0 }, 112 { OP_NEG, 0x0, 0x1, 0x0, 0x0, 0x1, 0x0 }, 113 { OP_CVT, 0x1, 0x1, 0x0, 0x8, 0x1, 0x0 }, 114 { OP_CEIL, 0x1, 0x1, 0x0, 0x8, 0x1, 0x0 }, 115 { OP_FLOOR, 0x1, 0x1, 0x0, 0x8, 0x1, 0x0 }, 116 { OP_TRUNC, 0x1, 0x1, 0x0, 0x8, 0x1, 0x0 }, 117 { OP_AND, 0x0, 0x0, 0x3, 0x0, 0x2, 0x2 | 0x8 }, 118 { OP_OR, 0x0, 0x0, 0x3, 0x0, 0x2, 0x2 | 0x8 }, 119 { OP_XOR, 0x0, 0x0, 0x3, 0x0, 0x2, 0x2 | 0x8 }, 120 { OP_SHL, 0x0, 0x0, 0x0, 0x0, 0x2, 0x2 }, 121 { OP_SHR, 0x0, 0x0, 0x0, 0x0, 0x2, 0x2 }, 122 { OP_SET, 0x3, 0x3, 0x0, 0x0, 0x2, 0x2 }, 123 { OP_SLCT, 0x4, 0x0, 0x0, 0x0, 0x6, 0x2 }, // special c[] constraint 124 { OP_PREEX2, 0x1, 0x1, 0x0, 0x0, 0x1, 0x1 }, 125 { OP_PRESIN, 0x1, 0x1, 0x0, 0x0, 0x1, 0x1 }, 126 { OP_COS, 0x1, 0x1, 0x0, 0x8, 0x0, 0x0 }, 127 { OP_SIN, 0x1, 0x1, 0x0, 0x8, 0x0, 0x0 }, 128 { OP_EX2, 0x1, 0x1, 0x0, 0x8, 0x0, 0x0 }, 129 { OP_LG2, 0x1, 0x1, 0x0, 0x8, 0x0, 0x0 }, 130 { OP_RCP, 0x1, 0x1, 0x0, 0x8, 0x0, 0x0 }, 131 { OP_RSQ, 0x1, 0x1, 0x0, 0x8, 0x0, 0x0 }, 132 { OP_DFDX, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0 }, 133 { OP_DFDY, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0 }, 134 { OP_CALL, 0x0, 0x0, 0x0, 0x0, 0x1, 0x0 }, 135 { OP_POPCNT, 0x0, 0x0, 0x3, 0x0, 0x2, 0x2 }, 136 { OP_INSBF, 0x0, 0x0, 0x0, 0x0, 0x6, 0x2 }, 137 { OP_EXTBF, 0x0, 0x0, 0x0, 0x0, 0x2, 0x2 }, 138 { OP_BFIND, 0x0, 0x0, 0x1, 0x0, 0x1, 0x1 }, 139 { OP_PERMT, 0x0, 0x0, 0x0, 0x0, 0x6, 0x2 }, 140 { OP_SET_AND, 0x3, 0x3, 0x0, 0x0, 0x2, 0x2 }, 141 { OP_SET_OR, 0x3, 0x3, 0x0, 0x0, 0x2, 0x2 }, 142 { OP_SET_XOR, 0x3, 0x3, 0x0, 0x0, 0x2, 0x2 }, 143 // saturate only: 144 { OP_LINTERP, 0x0, 0x0, 0x0, 0x8, 0x0, 0x0 }, 145 { OP_PINTERP, 0x0, 0x0, 0x0, 0x8, 0x0, 0x0 }, 146 // nve4 ops: 147 { OP_SULDB, 0x0, 0x0, 0x0, 0x0, 0x2, 0x0 }, 148 { OP_SUSTB, 0x0, 0x0, 0x0, 0x0, 0x2, 0x0 }, 149 { OP_SUSTP, 0x0, 0x0, 0x0, 0x0, 0x2, 0x0 }, 150 { OP_SUCLAMP, 0x0, 0x0, 0x0, 0x0, 0x2, 0x2 }, 151 { OP_SUBFM, 0x0, 0x0, 0x0, 0x0, 0x6, 0x2 }, 152 { OP_SUEAU, 0x0, 0x0, 0x0, 0x0, 0x6, 0x2 } 153}; 154 155void TargetNVC0::initOpInfo() 156{ 157 unsigned int i, j; 158 159 static const uint32_t commutative[(OP_LAST + 31) / 32] = 160 { 161 // ADD, MUL, MAD, FMA, AND, OR, XOR, MAX, MIN, SET_AND, SET_OR, SET_XOR, 162 // SET, SELP, SLCT 163 0x0ce0ca00, 0x0000007e, 0x00000000, 0x00000000 164 }; 165 166 static const uint32_t shortForm[(OP_LAST + 31) / 32] = 167 { 168 // ADD, MUL, MAD, FMA, AND, OR, XOR, MAX, MIN 169 0x0ce0ca00, 0x00000000, 0x00000000, 0x00000000 170 }; 171 172 static const operation noDest[] = 173 { 174 OP_STORE, OP_WRSV, OP_EXPORT, OP_BRA, OP_CALL, OP_RET, OP_EXIT, 175 OP_DISCARD, OP_CONT, OP_BREAK, OP_PRECONT, OP_PREBREAK, OP_PRERET, 176 OP_JOIN, OP_JOINAT, OP_BRKPT, OP_MEMBAR, OP_EMIT, OP_RESTART, 177 OP_QUADON, OP_QUADPOP, OP_TEXBAR, OP_SUSTB, OP_SUSTP, OP_SUREDP, 178 OP_SUREDB, OP_BAR 179 }; 180 181 static const operation noPred[] = 182 { 183 OP_CALL, OP_PRERET, OP_QUADON, OP_QUADPOP, 184 OP_JOINAT, OP_PREBREAK, OP_PRECONT, OP_BRKPT 185 }; 186 187 for (i = 0; i < DATA_FILE_COUNT; ++i) 188 nativeFileMap[i] = (DataFile)i; 189 nativeFileMap[FILE_ADDRESS] = FILE_GPR; 190 191 for (i = 0; i < OP_LAST; ++i) { 192 opInfo[i].variants = NULL; 193 opInfo[i].op = (operation)i; 194 opInfo[i].srcTypes = 1 << (int)TYPE_F32; 195 opInfo[i].dstTypes = 1 << (int)TYPE_F32; 196 opInfo[i].immdBits = 0; 197 opInfo[i].srcNr = operationSrcNr[i]; 198 199 for (j = 0; j < opInfo[i].srcNr; ++j) { 200 opInfo[i].srcMods[j] = 0; 201 opInfo[i].srcFiles[j] = 1 << (int)FILE_GPR; 202 } 203 opInfo[i].dstMods = 0; 204 opInfo[i].dstFiles = 1 << (int)FILE_GPR; 205 206 opInfo[i].hasDest = 1; 207 opInfo[i].vector = (i >= OP_TEX && i <= OP_TEXCSAA); 208 opInfo[i].commutative = (commutative[i / 32] >> (i % 32)) & 1; 209 opInfo[i].pseudo = (i < OP_MOV); 210 opInfo[i].predicate = !opInfo[i].pseudo; 211 opInfo[i].flow = (i >= OP_BRA && i <= OP_JOIN); 212 opInfo[i].minEncSize = (shortForm[i / 32] & (1 << (i % 32))) ? 4 : 8; 213 } 214 for (i = 0; i < sizeof(noDest) / sizeof(noDest[0]); ++i) 215 opInfo[noDest[i]].hasDest = 0; 216 for (i = 0; i < sizeof(noPred) / sizeof(noPred[0]); ++i) 217 opInfo[noPred[i]].predicate = 0; 218 219 for (i = 0; i < sizeof(_initProps) / sizeof(_initProps[0]); ++i) { 220 const struct opProperties *prop = &_initProps[i]; 221 222 for (int s = 0; s < 3; ++s) { 223 if (prop->mNeg & (1 << s)) 224 opInfo[prop->op].srcMods[s] |= NV50_IR_MOD_NEG; 225 if (prop->mAbs & (1 << s)) 226 opInfo[prop->op].srcMods[s] |= NV50_IR_MOD_ABS; 227 if (prop->mNot & (1 << s)) 228 opInfo[prop->op].srcMods[s] |= NV50_IR_MOD_NOT; 229 if (prop->fConst & (1 << s)) 230 opInfo[prop->op].srcFiles[s] |= 1 << (int)FILE_MEMORY_CONST; 231 if (prop->fImmd & (1 << s)) 232 opInfo[prop->op].srcFiles[s] |= 1 << (int)FILE_IMMEDIATE; 233 if (prop->fImmd & 8) 234 opInfo[prop->op].immdBits = 0xffffffff; 235 } 236 if (prop->mSat & 8) 237 opInfo[prop->op].dstMods = NV50_IR_MOD_SAT; 238 } 239} 240 241unsigned int 242TargetNVC0::getFileSize(DataFile file) const 243{ 244 const unsigned int gprs = (chipset >= NVISA_GK20A_CHIPSET) ? 255 : 63; 245 const unsigned int smregs = (chipset >= NVISA_GK104_CHIPSET) ? 65536 : 32768; 246 switch (file) { 247 case FILE_NULL: return 0; 248 case FILE_GPR: return MIN2(gprs, smregs / threads); 249 case FILE_PREDICATE: return 7; 250 case FILE_FLAGS: return 1; 251 case FILE_ADDRESS: return 0; 252 case FILE_IMMEDIATE: return 0; 253 case FILE_MEMORY_CONST: return 65536; 254 case FILE_SHADER_INPUT: return 0x400; 255 case FILE_SHADER_OUTPUT: return 0x400; 256 case FILE_MEMORY_BUFFER: return 0xffffffff; 257 case FILE_MEMORY_GLOBAL: return 0xffffffff; 258 case FILE_MEMORY_SHARED: return 16 << 10; 259 case FILE_MEMORY_LOCAL: return 48 << 10; 260 case FILE_SYSTEM_VALUE: return 32; 261 default: 262 assert(!"invalid file"); 263 return 0; 264 } 265} 266 267unsigned int 268TargetNVC0::getFileUnit(DataFile file) const 269{ 270 if (file == FILE_GPR || file == FILE_ADDRESS || file == FILE_SYSTEM_VALUE) 271 return 2; 272 return 0; 273} 274 275uint32_t 276TargetNVC0::getSVAddress(DataFile shaderFile, const Symbol *sym) const 277{ 278 const int idx = sym->reg.data.sv.index; 279 const SVSemantic sv = sym->reg.data.sv.sv; 280 281 const bool isInput = shaderFile == FILE_SHADER_INPUT; 282 const bool kepler = getChipset() >= NVISA_GK104_CHIPSET; 283 284 switch (sv) { 285 case SV_POSITION: return 0x070 + idx * 4; 286 case SV_INSTANCE_ID: return 0x2f8; 287 case SV_VERTEX_ID: return 0x2fc; 288 case SV_PRIMITIVE_ID: return isInput ? 0x060 : 0x040; 289 case SV_LAYER: return 0x064; 290 case SV_VIEWPORT_INDEX: return 0x068; 291 case SV_POINT_SIZE: return 0x06c; 292 case SV_CLIP_DISTANCE: return 0x2c0 + idx * 4; 293 case SV_POINT_COORD: return 0x2e0 + idx * 4; 294 case SV_FACE: return 0x3fc; 295 case SV_TESS_OUTER: return 0x000 + idx * 4; 296 case SV_TESS_INNER: return 0x010 + idx * 4; 297 case SV_TESS_COORD: return 0x2f0 + idx * 4; 298 case SV_NTID: return kepler ? (0x00 + idx * 4) : ~0; 299 case SV_NCTAID: return kepler ? (0x0c + idx * 4) : ~0; 300 case SV_GRIDID: return kepler ? 0x18 : ~0; 301 case SV_WORK_DIM: return 0x1c; 302 case SV_SAMPLE_INDEX: return 0; 303 case SV_SAMPLE_POS: return 0; 304 case SV_SAMPLE_MASK: return 0; 305 case SV_BASEVERTEX: return 0; 306 case SV_BASEINSTANCE: return 0; 307 case SV_DRAWID: return 0; 308 default: 309 return 0xffffffff; 310 } 311} 312 313bool 314TargetNVC0::insnCanLoad(const Instruction *i, int s, 315 const Instruction *ld) const 316{ 317 DataFile sf = ld->src(0).getFile(); 318 319 // immediate 0 can be represented by GPR $r63/$r255 320 if (sf == FILE_IMMEDIATE && ld->getSrc(0)->reg.data.u64 == 0) 321 return (!i->isPseudo() && 322 !i->asTex() && 323 i->op != OP_EXPORT && i->op != OP_STORE); 324 325 if (s >= opInfo[i->op].srcNr) 326 return false; 327 if (!(opInfo[i->op].srcFiles[s] & (1 << (int)sf))) 328 return false; 329 330 // indirect loads can only be done by OP_LOAD/VFETCH/INTERP on nvc0 331 if (ld->src(0).isIndirect(0)) 332 return false; 333 334 for (int k = 0; i->srcExists(k); ++k) { 335 if (i->src(k).getFile() == FILE_IMMEDIATE) { 336 if (k == 2 && i->op == OP_SUCLAMP) // special case 337 continue; 338 if (k == 1 && i->op == OP_SHLADD) // special case 339 continue; 340 if (i->getSrc(k)->reg.data.u64 != 0) 341 return false; 342 } else 343 if (i->src(k).getFile() != FILE_GPR && 344 i->src(k).getFile() != FILE_PREDICATE) { 345 return false; 346 } 347 } 348 349 // not all instructions support full 32 bit immediates 350 if (sf == FILE_IMMEDIATE) { 351 Storage ® = ld->getSrc(0)->asImm()->reg; 352 353 if (opInfo[i->op].immdBits != 0xffffffff || typeSizeof(i->sType) > 4) { 354 switch (i->sType) { 355 case TYPE_F64: 356 if (reg.data.u64 & 0x00000fffffffffffULL) 357 return false; 358 break; 359 case TYPE_F32: 360 if (reg.data.u32 & 0xfff) 361 return false; 362 break; 363 case TYPE_S32: 364 case TYPE_U32: 365 // with u32, 0xfffff counts as 0xffffffff as well 366 if (reg.data.s32 > 0x7ffff || reg.data.s32 < -0x80000) 367 return false; 368 break; 369 case TYPE_U8: 370 case TYPE_S8: 371 case TYPE_U16: 372 case TYPE_S16: 373 case TYPE_F16: 374 break; 375 default: 376 return false; 377 } 378 } else 379 if (i->op == OP_MAD || i->op == OP_FMA) { 380 // requires src == dst, cannot decide before RA 381 // (except if we implement more constraints) 382 if (ld->getSrc(0)->asImm()->reg.data.u32 & 0xfff) 383 return false; 384 } else 385 if (i->op == OP_ADD && i->sType == TYPE_F32) { 386 // add f32 LIMM cannot saturate 387 if (i->saturate && (reg.data.u32 & 0xfff)) 388 return false; 389 } 390 } 391 392 return true; 393} 394 395bool 396TargetNVC0::insnCanLoadOffset(const Instruction *insn, int s, int offset) const 397{ 398 const ValueRef& ref = insn->src(s); 399 if (ref.getFile() == FILE_MEMORY_CONST && 400 (insn->op != OP_LOAD || insn->subOp != NV50_IR_SUBOP_LDC_IS)) 401 return offset >= -0x8000 && offset < 0x8000; 402 return true; 403} 404 405bool 406TargetNVC0::isAccessSupported(DataFile file, DataType ty) const 407{ 408 if (ty == TYPE_NONE) 409 return false; 410 if (file == FILE_MEMORY_CONST) { 411 if (getChipset() >= NVISA_GM107_CHIPSET) 412 return typeSizeof(ty) <= 4; 413 else 414 if (getChipset() >= NVISA_GK104_CHIPSET) // wrong encoding ? 415 return typeSizeof(ty) <= 8; 416 } 417 if (ty == TYPE_B96) 418 return false; 419 return true; 420} 421 422bool 423TargetNVC0::isOpSupported(operation op, DataType ty) const 424{ 425 if (op == OP_SAD && ty != TYPE_S32 && ty != TYPE_U32) 426 return false; 427 if (op == OP_POW || op == OP_SQRT || op == OP_DIV || op == OP_MOD) 428 return false; 429 return true; 430} 431 432bool 433TargetNVC0::isModSupported(const Instruction *insn, int s, Modifier mod) const 434{ 435 if (!isFloatType(insn->dType)) { 436 switch (insn->op) { 437 case OP_ABS: 438 case OP_NEG: 439 case OP_CVT: 440 case OP_CEIL: 441 case OP_FLOOR: 442 case OP_TRUNC: 443 case OP_AND: 444 case OP_OR: 445 case OP_XOR: 446 case OP_POPCNT: 447 case OP_BFIND: 448 break; 449 case OP_SET: 450 if (insn->sType != TYPE_F32) 451 return false; 452 break; 453 case OP_ADD: 454 if (mod.abs()) 455 return false; 456 if (insn->src(s ? 0 : 1).mod.neg()) 457 return false; 458 break; 459 case OP_SUB: 460 if (s == 0) 461 return insn->src(1).mod.neg() ? false : true; 462 break; 463 case OP_SHLADD: 464 if (s == 1) 465 return false; 466 if (insn->src(s ? 0 : 2).mod.neg()) 467 return false; 468 break; 469 default: 470 return false; 471 } 472 } 473 if (s >= opInfo[insn->op].srcNr || s >= 3) 474 return false; 475 return (mod & Modifier(opInfo[insn->op].srcMods[s])) == mod; 476} 477 478bool 479TargetNVC0::mayPredicate(const Instruction *insn, const Value *pred) const 480{ 481 if (insn->getPredicate()) 482 return false; 483 return opInfo[insn->op].predicate; 484} 485 486bool 487TargetNVC0::isSatSupported(const Instruction *insn) const 488{ 489 if (insn->op == OP_CVT) 490 return true; 491 if (!(opInfo[insn->op].dstMods & NV50_IR_MOD_SAT)) 492 return false; 493 494 if (insn->dType == TYPE_U32) 495 return (insn->op == OP_ADD) || (insn->op == OP_MAD); 496 497 // add f32 LIMM cannot saturate 498 if (insn->op == OP_ADD && insn->sType == TYPE_F32) { 499 if (insn->getSrc(1)->asImm() && 500 insn->getSrc(1)->reg.data.u32 & 0xfff) 501 return false; 502 } 503 504 return insn->dType == TYPE_F32; 505} 506 507bool 508TargetNVC0::isPostMultiplySupported(operation op, float f, int& e) const 509{ 510 if (op != OP_MUL) 511 return false; 512 f = fabsf(f); 513 e = static_cast<int>(log2f(f)); 514 if (e < -3 || e > 3) 515 return false; 516 return f == exp2f(static_cast<float>(e)); 517} 518 519// TODO: better values 520// this could be more precise, e.g. depending on the issue-to-read/write delay 521// of the depending instruction, but it's good enough 522int TargetNVC0::getLatency(const Instruction *i) const 523{ 524 if (chipset >= 0xe4) { 525 if (i->dType == TYPE_F64 || i->sType == TYPE_F64) 526 return 20; 527 switch (i->op) { 528 case OP_LINTERP: 529 case OP_PINTERP: 530 return 15; 531 case OP_LOAD: 532 if (i->src(0).getFile() == FILE_MEMORY_CONST) 533 return 9; 534 // fall through 535 case OP_VFETCH: 536 return 24; 537 default: 538 if (Target::getOpClass(i->op) == OPCLASS_TEXTURE) 539 return 17; 540 if (i->op == OP_MUL && i->dType != TYPE_F32) 541 return 15; 542 return 9; 543 } 544 } else { 545 if (i->op == OP_LOAD) { 546 if (i->cache == CACHE_CV) 547 return 700; 548 return 48; 549 } 550 return 24; 551 } 552 return 32; 553} 554 555// These are "inverse" throughput values, i.e. the number of cycles required 556// to issue a specific instruction for a full warp (32 threads). 557// 558// Assuming we have more than 1 warp in flight, a higher issue latency results 559// in a lower result latency since the MP will have spent more time with other 560// warps. 561// This also helps to determine the number of cycles between instructions in 562// a single warp. 563// 564int TargetNVC0::getThroughput(const Instruction *i) const 565{ 566 // TODO: better values 567 if (i->dType == TYPE_F32) { 568 switch (i->op) { 569 case OP_ADD: 570 case OP_MUL: 571 case OP_MAD: 572 case OP_FMA: 573 return 1; 574 case OP_CVT: 575 case OP_CEIL: 576 case OP_FLOOR: 577 case OP_TRUNC: 578 case OP_SET: 579 case OP_SLCT: 580 case OP_MIN: 581 case OP_MAX: 582 return 2; 583 case OP_RCP: 584 case OP_RSQ: 585 case OP_LG2: 586 case OP_SIN: 587 case OP_COS: 588 case OP_PRESIN: 589 case OP_PREEX2: 590 default: 591 return 8; 592 } 593 } else 594 if (i->dType == TYPE_U32 || i->dType == TYPE_S32) { 595 switch (i->op) { 596 case OP_ADD: 597 case OP_AND: 598 case OP_OR: 599 case OP_XOR: 600 case OP_NOT: 601 return 1; 602 case OP_MUL: 603 case OP_MAD: 604 case OP_CVT: 605 case OP_SET: 606 case OP_SLCT: 607 case OP_SHL: 608 case OP_SHR: 609 case OP_NEG: 610 case OP_ABS: 611 case OP_MIN: 612 case OP_MAX: 613 default: 614 return 2; 615 } 616 } else 617 if (i->dType == TYPE_F64) { 618 return 2; 619 } else { 620 return 1; 621 } 622} 623 624bool TargetNVC0::canDualIssue(const Instruction *a, const Instruction *b) const 625{ 626 const OpClass clA = operationClass[a->op]; 627 const OpClass clB = operationClass[b->op]; 628 629 if (getChipset() >= 0xe4) { 630 // not texturing 631 // not if the 2nd instruction isn't necessarily executed 632 if (clA == OPCLASS_TEXTURE || clA == OPCLASS_FLOW) 633 return false; 634 635 // Check that a and b don't write to the same sources, nor that b reads 636 // anything that a writes. 637 if (!a->canCommuteDefDef(b) || !a->canCommuteDefSrc(b)) 638 return false; 639 640 // anything with MOV 641 if (a->op == OP_MOV || b->op == OP_MOV) 642 return true; 643 if (clA == clB) { 644 switch (clA) { 645 // there might be more 646 case OPCLASS_COMPARE: 647 if ((a->op == OP_MIN || a->op == OP_MAX) && 648 (b->op == OP_MIN || b->op == OP_MAX)) 649 break; 650 return false; 651 case OPCLASS_ARITH: 652 break; 653 default: 654 return false; 655 } 656 // only F32 arith or integer additions 657 return (a->dType == TYPE_F32 || a->op == OP_ADD || 658 b->dType == TYPE_F32 || b->op == OP_ADD); 659 } 660 // nothing with TEXBAR 661 if (a->op == OP_TEXBAR || b->op == OP_TEXBAR) 662 return false; 663 // no loads and stores accessing the same space 664 if ((clA == OPCLASS_LOAD && clB == OPCLASS_STORE) || 665 (clB == OPCLASS_LOAD && clA == OPCLASS_STORE)) 666 if (a->src(0).getFile() == b->src(0).getFile()) 667 return false; 668 // no > 32-bit ops 669 if (typeSizeof(a->dType) > 4 || typeSizeof(b->dType) > 4 || 670 typeSizeof(a->sType) > 4 || typeSizeof(b->sType) > 4) 671 return false; 672 return true; 673 } else { 674 return false; // info not needed (yet) 675 } 676} 677 678} // namespace nv50_ir 679