1/************************************************************************** 2 * 3 * Copyright 2013 Advanced Micro Devices, Inc. 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 21 * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR 22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 **************************************************************************/ 27 28/* 29 * Authors: 30 * Christian König <christian.koenig@amd.com> 31 * 32 */ 33 34#include <stdio.h> 35 36#include "pipe/p_video_codec.h" 37 38#include "util/u_video.h" 39#include "util/u_memory.h" 40 41#include "vl/vl_video_buffer.h" 42 43#include "r600_pipe_common.h" 44#include "radeon_video.h" 45#include "radeon_vce.h" 46 47static void rate_control(struct rvce_encoder *enc) 48{ 49 RVCE_BEGIN(0x04000005); // rate control 50 RVCE_CS(enc->pic.rate_ctrl.rate_ctrl_method); // encRateControlMethod 51 RVCE_CS(enc->pic.rate_ctrl.target_bitrate); // encRateControlTargetBitRate 52 RVCE_CS(enc->pic.rate_ctrl.peak_bitrate); // encRateControlPeakBitRate 53 RVCE_CS(enc->pic.rate_ctrl.frame_rate_num); // encRateControlFrameRateNum 54 RVCE_CS(0x00000000); // encGOPSize 55 RVCE_CS(enc->pic.quant_i_frames); // encQP_I 56 RVCE_CS(enc->pic.quant_p_frames); // encQP_P 57 RVCE_CS(enc->pic.quant_b_frames); // encQP_B 58 RVCE_CS(enc->pic.rate_ctrl.vbv_buffer_size); // encVBVBufferSize 59 RVCE_CS(enc->pic.rate_ctrl.frame_rate_den); // encRateControlFrameRateDen 60 RVCE_CS(0x00000000); // encVBVBufferLevel 61 RVCE_CS(0x00000000); // encMaxAUSize 62 RVCE_CS(0x00000000); // encQPInitialMode 63 RVCE_CS(enc->pic.rate_ctrl.target_bits_picture); // encTargetBitsPerPicture 64 RVCE_CS(enc->pic.rate_ctrl.peak_bits_picture_integer); // encPeakBitsPerPictureInteger 65 RVCE_CS(enc->pic.rate_ctrl.peak_bits_picture_fraction); // encPeakBitsPerPictureFractional 66 RVCE_CS(0x00000000); // encMinQP 67 RVCE_CS(0x00000033); // encMaxQP 68 RVCE_CS(0x00000000); // encSkipFrameEnable 69 RVCE_CS(0x00000000); // encFillerDataEnable 70 RVCE_CS(0x00000000); // encEnforceHRD 71 RVCE_CS(0x00000000); // encBPicsDeltaQP 72 RVCE_CS(0x00000000); // encReferenceBPicsDeltaQP 73 RVCE_CS(0x00000000); // encRateControlReInitDisable 74 RVCE_CS(0x00000000); // encLCVBRInitQPFlag 75 RVCE_CS(0x00000000); // encLCVBRSATDBasedNonlinearBitBudgetFlag 76 RVCE_END(); 77} 78 79static void encode(struct rvce_encoder *enc) 80{ 81 signed luma_offset, chroma_offset, bs_offset; 82 unsigned dep, bs_idx = enc->bs_idx++; 83 int i; 84 85 if (enc->dual_inst) { 86 if (bs_idx == 0) 87 dep = 1; 88 else if (enc->pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_IDR) 89 dep = 0; 90 else 91 dep = 2; 92 } else 93 dep = 0; 94 95 enc->task_info(enc, 0x00000003, dep, 0, bs_idx); 96 97 RVCE_BEGIN(0x05000001); // context buffer 98 RVCE_READWRITE(enc->cpb.res->buf, enc->cpb.res->domains, 0); // encodeContextAddressHi/Lo 99 RVCE_END(); 100 101 bs_offset = -(signed)(bs_idx * enc->bs_size); 102 103 RVCE_BEGIN(0x05000004); // video bitstream buffer 104 RVCE_WRITE(enc->bs_handle, RADEON_DOMAIN_GTT, bs_offset); // videoBitstreamRingAddressHi/Lo 105 RVCE_CS(enc->bs_size); // videoBitstreamRingSize 106 RVCE_END(); 107 108 if (enc->dual_pipe) { 109 unsigned aux_offset = enc->cpb.res->buf->size - 110 RVCE_MAX_AUX_BUFFER_NUM * RVCE_MAX_BITSTREAM_OUTPUT_ROW_SIZE * 2; 111 RVCE_BEGIN(0x05000002); // auxiliary buffer 112 for (i = 0; i < 8; ++i) { 113 RVCE_CS(aux_offset); 114 aux_offset += RVCE_MAX_BITSTREAM_OUTPUT_ROW_SIZE; 115 } 116 for (i = 0; i < 8; ++i) 117 RVCE_CS(RVCE_MAX_BITSTREAM_OUTPUT_ROW_SIZE); 118 RVCE_END(); 119 } 120 121 RVCE_BEGIN(0x03000001); // encode 122 RVCE_CS(enc->pic.frame_num ? 0x0 : 0x11); // insertHeaders 123 RVCE_CS(0x00000000); // pictureStructure 124 RVCE_CS(enc->bs_size); // allowedMaxBitstreamSize 125 RVCE_CS(0x00000000); // forceRefreshMap 126 RVCE_CS(0x00000000); // insertAUD 127 RVCE_CS(0x00000000); // endOfSequence 128 RVCE_CS(0x00000000); // endOfStream 129 RVCE_READ(enc->handle, RADEON_DOMAIN_VRAM, 130 enc->luma->level[0].offset); // inputPictureLumaAddressHi/Lo 131 RVCE_READ(enc->handle, RADEON_DOMAIN_VRAM, 132 enc->chroma->level[0].offset); // inputPictureChromaAddressHi/Lo 133 RVCE_CS(align(enc->luma->level[0].nblk_y, 16)); // encInputFrameYPitch 134 RVCE_CS(enc->luma->level[0].nblk_x * enc->luma->bpe); // encInputPicLumaPitch 135 RVCE_CS(enc->chroma->level[0].nblk_x * enc->chroma->bpe); // encInputPicChromaPitch 136 if (enc->dual_pipe) 137 RVCE_CS(0x00000000); // encInputPic(Addr|Array)Mode,encDisable(TwoPipeMode|MBOffloading) 138 else 139 RVCE_CS(0x00010000); // encInputPic(Addr|Array)Mode,encDisable(TwoPipeMode|MBOffloading) 140 RVCE_CS(0x00000000); // encInputPicTileConfig 141 RVCE_CS(enc->pic.picture_type); // encPicType 142 RVCE_CS(enc->pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_IDR); // encIdrFlag 143 RVCE_CS(0x00000000); // encIdrPicId 144 RVCE_CS(0x00000000); // encMGSKeyPic 145 RVCE_CS(!enc->pic.not_referenced); // encReferenceFlag 146 RVCE_CS(0x00000000); // encTemporalLayerIndex 147 RVCE_CS(0x00000000); // num_ref_idx_active_override_flag 148 RVCE_CS(0x00000000); // num_ref_idx_l0_active_minus1 149 RVCE_CS(0x00000000); // num_ref_idx_l1_active_minus1 150 151 i = enc->pic.frame_num - enc->pic.ref_idx_l0; 152 if (i > 1 && enc->pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_P) { 153 RVCE_CS(0x00000001); // encRefListModificationOp 154 RVCE_CS(i - 1); // encRefListModificationNum 155 } else { 156 RVCE_CS(0x00000000); // encRefListModificationOp 157 RVCE_CS(0x00000000); // encRefListModificationNum 158 } 159 160 for (i = 0; i < 3; ++i) { 161 RVCE_CS(0x00000000); // encRefListModificationOp 162 RVCE_CS(0x00000000); // encRefListModificationNum 163 } 164 for (i = 0; i < 4; ++i) { 165 RVCE_CS(0x00000000); // encDecodedPictureMarkingOp 166 RVCE_CS(0x00000000); // encDecodedPictureMarkingNum 167 RVCE_CS(0x00000000); // encDecodedPictureMarkingIdx 168 RVCE_CS(0x00000000); // encDecodedRefBasePictureMarkingOp 169 RVCE_CS(0x00000000); // encDecodedRefBasePictureMarkingNum 170 } 171 172 // encReferencePictureL0[0] 173 RVCE_CS(0x00000000); // pictureStructure 174 if(enc->pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_P || 175 enc->pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_B) { 176 struct rvce_cpb_slot *l0 = l0_slot(enc); 177 rvce_frame_offset(enc, l0, &luma_offset, &chroma_offset); 178 RVCE_CS(l0->picture_type); // encPicType 179 RVCE_CS(l0->frame_num); // frameNumber 180 RVCE_CS(l0->pic_order_cnt); // pictureOrderCount 181 RVCE_CS(luma_offset); // lumaOffset 182 RVCE_CS(chroma_offset); // chromaOffset 183 } else { 184 RVCE_CS(0x00000000); // encPicType 185 RVCE_CS(0x00000000); // frameNumber 186 RVCE_CS(0x00000000); // pictureOrderCount 187 RVCE_CS(0xffffffff); // lumaOffset 188 RVCE_CS(0xffffffff); // chromaOffset 189 } 190 191 // encReferencePictureL0[1] 192 RVCE_CS(0x00000000); // pictureStructure 193 RVCE_CS(0x00000000); // encPicType 194 RVCE_CS(0x00000000); // frameNumber 195 RVCE_CS(0x00000000); // pictureOrderCount 196 RVCE_CS(0xffffffff); // lumaOffset 197 RVCE_CS(0xffffffff); // chromaOffset 198 199 // encReferencePictureL1[0] 200 RVCE_CS(0x00000000); // pictureStructure 201 if(enc->pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_B) { 202 struct rvce_cpb_slot *l1 = l1_slot(enc); 203 rvce_frame_offset(enc, l1, &luma_offset, &chroma_offset); 204 RVCE_CS(l1->picture_type); // encPicType 205 RVCE_CS(l1->frame_num); // frameNumber 206 RVCE_CS(l1->pic_order_cnt); // pictureOrderCount 207 RVCE_CS(luma_offset); // lumaOffset 208 RVCE_CS(chroma_offset); // chromaOffset 209 } else { 210 RVCE_CS(0x00000000); // encPicType 211 RVCE_CS(0x00000000); // frameNumber 212 RVCE_CS(0x00000000); // pictureOrderCount 213 RVCE_CS(0xffffffff); // lumaOffset 214 RVCE_CS(0xffffffff); // chromaOffset 215 } 216 217 rvce_frame_offset(enc, current_slot(enc), &luma_offset, &chroma_offset); 218 RVCE_CS(luma_offset); // encReconstructedLumaOffset 219 RVCE_CS(chroma_offset); // encReconstructedChromaOffset 220 RVCE_CS(0x00000000); // encColocBufferOffset 221 RVCE_CS(0x00000000); // encReconstructedRefBasePictureLumaOffset 222 RVCE_CS(0x00000000); // encReconstructedRefBasePictureChromaOffset 223 RVCE_CS(0x00000000); // encReferenceRefBasePictureLumaOffset 224 RVCE_CS(0x00000000); // encReferenceRefBasePictureChromaOffset 225 RVCE_CS(0x00000000); // pictureCount 226 RVCE_CS(enc->pic.frame_num); // frameNumber 227 RVCE_CS(enc->pic.pic_order_cnt); // pictureOrderCount 228 RVCE_CS(0x00000000); // numIPicRemainInRCGOP 229 RVCE_CS(0x00000000); // numPPicRemainInRCGOP 230 RVCE_CS(0x00000000); // numBPicRemainInRCGOP 231 RVCE_CS(0x00000000); // numIRPicRemainInRCGOP 232 RVCE_CS(0x00000000); // enableIntraRefresh 233 RVCE_END(); 234} 235 236void radeon_vce_50_get_param(struct rvce_encoder *enc, struct pipe_h264_enc_picture_desc *pic) 237{ 238} 239 240void radeon_vce_50_init(struct rvce_encoder *enc) 241{ 242 radeon_vce_40_2_2_init(enc); 243 244 /* only the two below are different */ 245 enc->rate_control = rate_control; 246 enc->encode = encode; 247} 248