vc4_qir.h revision 2350569a78c60d32e3b751b4386ea7e6d7e2ebe9
1/* 2 * Copyright © 2014 Broadcom 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24#ifndef VC4_QIR_H 25#define VC4_QIR_H 26 27#include <assert.h> 28#include <stdio.h> 29#include <stdlib.h> 30#include <stdbool.h> 31#include <stdint.h> 32#include <string.h> 33 34#include "util/macros.h" 35#include "compiler/nir/nir.h" 36#include "util/list.h" 37#include "util/u_math.h" 38 39#include "vc4_screen.h" 40#include "vc4_qpu_defines.h" 41#include "vc4_qpu.h" 42#include "kernel/vc4_packet.h" 43#include "pipe/p_state.h" 44 45struct nir_builder; 46 47enum qfile { 48 QFILE_NULL, 49 QFILE_TEMP, 50 QFILE_VARY, 51 QFILE_UNIF, 52 QFILE_VPM, 53 QFILE_TLB_COLOR_WRITE, 54 QFILE_TLB_COLOR_WRITE_MS, 55 QFILE_TLB_Z_WRITE, 56 QFILE_TLB_STENCIL_SETUP, 57 58 /* Payload registers that aren't in the physical register file, so we 59 * can just use the corresponding qpu_reg at qpu_emit time. 60 */ 61 QFILE_FRAG_X, 62 QFILE_FRAG_Y, 63 QFILE_FRAG_REV_FLAG, 64 65 /** 66 * Stores an immediate value in the index field that will be used 67 * directly by qpu_load_imm(). 68 */ 69 QFILE_LOAD_IMM, 70 71 /** 72 * Stores an immediate value in the index field that can be turned 73 * into a small immediate field by qpu_encode_small_immediate(). 74 */ 75 QFILE_SMALL_IMM, 76}; 77 78struct qreg { 79 enum qfile file; 80 uint32_t index; 81 int pack; 82}; 83 84static inline struct qreg qir_reg(enum qfile file, uint32_t index) 85{ 86 return (struct qreg){file, index}; 87} 88 89enum qop { 90 QOP_UNDEF, 91 QOP_MOV, 92 QOP_FMOV, 93 QOP_MMOV, 94 QOP_FADD, 95 QOP_FSUB, 96 QOP_FMUL, 97 QOP_V8MULD, 98 QOP_V8MIN, 99 QOP_V8MAX, 100 QOP_V8ADDS, 101 QOP_V8SUBS, 102 QOP_MUL24, 103 QOP_FMIN, 104 QOP_FMAX, 105 QOP_FMINABS, 106 QOP_FMAXABS, 107 QOP_ADD, 108 QOP_SUB, 109 QOP_SHL, 110 QOP_SHR, 111 QOP_ASR, 112 QOP_MIN, 113 QOP_MAX, 114 QOP_AND, 115 QOP_OR, 116 QOP_XOR, 117 QOP_NOT, 118 119 QOP_FTOI, 120 QOP_ITOF, 121 QOP_RCP, 122 QOP_RSQ, 123 QOP_EXP2, 124 QOP_LOG2, 125 QOP_VW_SETUP, 126 QOP_VR_SETUP, 127 QOP_TLB_COLOR_READ, 128 QOP_MS_MASK, 129 QOP_VARY_ADD_C, 130 131 QOP_FRAG_Z, 132 QOP_FRAG_W, 133 134 /** Texture x coordinate parameter write */ 135 QOP_TEX_S, 136 /** Texture y coordinate parameter write */ 137 QOP_TEX_T, 138 /** Texture border color parameter or cube map z coordinate write */ 139 QOP_TEX_R, 140 /** Texture LOD bias parameter write */ 141 QOP_TEX_B, 142 143 /** 144 * Texture-unit 4-byte read with address provided direct in S 145 * cooordinate. 146 * 147 * The first operand is the offset from the start of the UBO, and the 148 * second is the uniform that has the UBO's base pointer. 149 */ 150 QOP_TEX_DIRECT, 151 152 /** 153 * Signal of texture read being necessary and then reading r4 into 154 * the destination 155 */ 156 QOP_TEX_RESULT, 157 158 QOP_LOAD_IMM, 159 160 /* Jumps to block->successor[0] if the qinst->cond (as a 161 * QPU_COND_BRANCH_*) passes, or block->successor[1] if not. Note 162 * that block->successor[1] may be unset if the condition is ALWAYS. 163 */ 164 QOP_BRANCH, 165 166 /* Emits an ADD from src[0] to src[1], where src[0] must be a 167 * QOP_LOAD_IMM result and src[1] is a QUNIFORM_UNIFORMS_ADDRESS, 168 * required by the kernel as part of its branch validation. 169 */ 170 QOP_UNIFORMS_RESET, 171}; 172 173struct queued_qpu_inst { 174 struct list_head link; 175 uint64_t inst; 176}; 177 178struct qinst { 179 struct list_head link; 180 181 enum qop op; 182 struct qreg dst; 183 struct qreg *src; 184 bool sf; 185 uint8_t cond; 186}; 187 188enum qstage { 189 /** 190 * Coordinate shader, runs during binning, before the VS, and just 191 * outputs position. 192 */ 193 QSTAGE_COORD, 194 QSTAGE_VERT, 195 QSTAGE_FRAG, 196}; 197 198enum quniform_contents { 199 /** 200 * Indicates that a constant 32-bit value is copied from the program's 201 * uniform contents. 202 */ 203 QUNIFORM_CONSTANT, 204 /** 205 * Indicates that the program's uniform contents are used as an index 206 * into the GL uniform storage. 207 */ 208 QUNIFORM_UNIFORM, 209 210 /** @{ 211 * Scaling factors from clip coordinates to relative to the viewport 212 * center. 213 * 214 * This is used by the coordinate and vertex shaders to produce the 215 * 32-bit entry consisting of 2 16-bit fields with 12.4 signed fixed 216 * point offsets from the viewport ccenter. 217 */ 218 QUNIFORM_VIEWPORT_X_SCALE, 219 QUNIFORM_VIEWPORT_Y_SCALE, 220 /** @} */ 221 222 QUNIFORM_VIEWPORT_Z_OFFSET, 223 QUNIFORM_VIEWPORT_Z_SCALE, 224 225 QUNIFORM_USER_CLIP_PLANE, 226 227 /** 228 * A reference to a texture config parameter 0 uniform. 229 * 230 * This is a uniform implicitly loaded with a QPU_W_TMU* write, which 231 * defines texture type, miplevels, and such. It will be found as a 232 * parameter to the first QOP_TEX_[STRB] instruction in a sequence. 233 */ 234 QUNIFORM_TEXTURE_CONFIG_P0, 235 236 /** 237 * A reference to a texture config parameter 1 uniform. 238 * 239 * This is a uniform implicitly loaded with a QPU_W_TMU* write, which 240 * defines texture width, height, filters, and wrap modes. It will be 241 * found as a parameter to the second QOP_TEX_[STRB] instruction in a 242 * sequence. 243 */ 244 QUNIFORM_TEXTURE_CONFIG_P1, 245 246 /** A reference to a texture config parameter 2 cubemap stride uniform */ 247 QUNIFORM_TEXTURE_CONFIG_P2, 248 249 QUNIFORM_TEXTURE_FIRST_LEVEL, 250 251 QUNIFORM_TEXTURE_MSAA_ADDR, 252 253 QUNIFORM_UBO_ADDR, 254 255 QUNIFORM_TEXRECT_SCALE_X, 256 QUNIFORM_TEXRECT_SCALE_Y, 257 258 QUNIFORM_TEXTURE_BORDER_COLOR, 259 260 QUNIFORM_BLEND_CONST_COLOR_X, 261 QUNIFORM_BLEND_CONST_COLOR_Y, 262 QUNIFORM_BLEND_CONST_COLOR_Z, 263 QUNIFORM_BLEND_CONST_COLOR_W, 264 QUNIFORM_BLEND_CONST_COLOR_RGBA, 265 QUNIFORM_BLEND_CONST_COLOR_AAAA, 266 267 QUNIFORM_STENCIL, 268 269 QUNIFORM_ALPHA_REF, 270 QUNIFORM_SAMPLE_MASK, 271 272 /* Placeholder uniform that will be updated by the kernel when used by 273 * an instruction writing to QPU_W_UNIFORMS_ADDRESS. 274 */ 275 QUNIFORM_UNIFORMS_ADDRESS, 276}; 277 278struct vc4_varying_slot { 279 uint8_t slot; 280 uint8_t swizzle; 281}; 282 283struct vc4_compiler_ubo_range { 284 /** 285 * offset in bytes from the start of the ubo where this range is 286 * uploaded. 287 * 288 * Only set once used is set. 289 */ 290 uint32_t dst_offset; 291 292 /** 293 * offset in bytes from the start of the gallium uniforms where the 294 * data comes from. 295 */ 296 uint32_t src_offset; 297 298 /** size in bytes of this ubo range */ 299 uint32_t size; 300 301 /** 302 * Set if this range is used by the shader for indirect uniforms 303 * access. 304 */ 305 bool used; 306}; 307 308struct vc4_key { 309 struct vc4_uncompiled_shader *shader_state; 310 struct { 311 enum pipe_format format; 312 uint8_t swizzle[4]; 313 union { 314 struct { 315 unsigned compare_mode:1; 316 unsigned compare_func:3; 317 unsigned wrap_s:3; 318 unsigned wrap_t:3; 319 bool force_first_level:1; 320 }; 321 struct { 322 uint16_t msaa_width, msaa_height; 323 }; 324 }; 325 } tex[VC4_MAX_TEXTURE_SAMPLERS]; 326 uint8_t ucp_enables; 327}; 328 329struct vc4_fs_key { 330 struct vc4_key base; 331 enum pipe_format color_format; 332 bool depth_enabled; 333 bool stencil_enabled; 334 bool stencil_twoside; 335 bool stencil_full_writemasks; 336 bool is_points; 337 bool is_lines; 338 bool alpha_test; 339 bool point_coord_upper_left; 340 bool light_twoside; 341 bool msaa; 342 bool sample_coverage; 343 bool sample_alpha_to_coverage; 344 bool sample_alpha_to_one; 345 uint8_t alpha_test_func; 346 uint8_t logicop_func; 347 uint32_t point_sprite_mask; 348 349 struct pipe_rt_blend_state blend; 350}; 351 352struct vc4_vs_key { 353 struct vc4_key base; 354 355 const struct vc4_fs_inputs *fs_inputs; 356 enum pipe_format attr_formats[8]; 357 bool is_coord; 358 bool per_vertex_point_size; 359 bool clamp_color; 360}; 361 362/** A basic block of QIR intructions. */ 363struct qblock { 364 struct list_head link; 365 366 struct list_head instructions; 367 struct list_head qpu_inst_list; 368 369 struct set *predecessors; 370 struct qblock *successors[2]; 371 372 int index; 373 374 /* Instruction IPs for the first and last instruction of the block. 375 * Set by vc4_qpu_schedule.c. 376 */ 377 uint32_t start_qpu_ip; 378 uint32_t end_qpu_ip; 379 380 /* Instruction IP for the branch instruction of the block. Set by 381 * vc4_qpu_schedule.c. 382 */ 383 uint32_t branch_qpu_ip; 384 385 /** @{ used by vc4_qir_live_variables.c */ 386 BITSET_WORD *def; 387 BITSET_WORD *use; 388 BITSET_WORD *live_in; 389 BITSET_WORD *live_out; 390 int start_ip, end_ip; 391 /** @} */ 392}; 393 394struct vc4_compile { 395 struct vc4_context *vc4; 396 nir_shader *s; 397 nir_function_impl *impl; 398 struct exec_list *cf_node_list; 399 400 /** 401 * Mapping from nir_register * or nir_ssa_def * to array of struct 402 * qreg for the values. 403 */ 404 struct hash_table *def_ht; 405 406 /* For each temp, the instruction generating its value. */ 407 struct qinst **defs; 408 uint32_t defs_array_size; 409 410 /** 411 * Inputs to the shader, arranged by TGSI declaration order. 412 * 413 * Not all fragment shader QFILE_VARY reads are present in this array. 414 */ 415 struct qreg *inputs; 416 struct qreg *outputs; 417 bool msaa_per_sample_output; 418 struct qreg color_reads[VC4_MAX_SAMPLES]; 419 struct qreg sample_colors[VC4_MAX_SAMPLES]; 420 uint32_t inputs_array_size; 421 uint32_t outputs_array_size; 422 uint32_t uniforms_array_size; 423 424 struct vc4_compiler_ubo_range *ubo_ranges; 425 uint32_t ubo_ranges_array_size; 426 /** Number of uniform areas declared in ubo_ranges. */ 427 uint32_t num_uniform_ranges; 428 /** Number of uniform areas used for indirect addressed loads. */ 429 uint32_t num_ubo_ranges; 430 uint32_t next_ubo_dst_offset; 431 432 /* State for whether we're executing on each channel currently. 0 if 433 * yes, otherwise a block number + 1 that the channel jumped to. 434 */ 435 struct qreg execute; 436 437 struct qreg line_x, point_x, point_y; 438 struct qreg discard; 439 struct qreg payload_FRAG_Z; 440 struct qreg payload_FRAG_W; 441 442 uint8_t vattr_sizes[8]; 443 444 /** 445 * Array of the VARYING_SLOT_* of all FS QFILE_VARY reads. 446 * 447 * This includes those that aren't part of the VPM varyings, like 448 * point/line coordinates. 449 */ 450 struct vc4_varying_slot *input_slots; 451 uint32_t num_input_slots; 452 uint32_t input_slots_array_size; 453 454 /** 455 * An entry per outputs[] in the VS indicating what the VARYING_SLOT_* 456 * of the output is. Used to emit from the VS in the order that the 457 * FS needs. 458 */ 459 struct vc4_varying_slot *output_slots; 460 461 struct pipe_shader_state *shader_state; 462 struct vc4_key *key; 463 struct vc4_fs_key *fs_key; 464 struct vc4_vs_key *vs_key; 465 466 /* Live ranges of temps. */ 467 int *temp_start, *temp_end; 468 469 uint32_t *uniform_data; 470 enum quniform_contents *uniform_contents; 471 uint32_t uniform_array_size; 472 uint32_t num_uniforms; 473 uint32_t num_outputs; 474 uint32_t num_texture_samples; 475 uint32_t output_position_index; 476 uint32_t output_color_index; 477 uint32_t output_point_size_index; 478 uint32_t output_sample_mask_index; 479 480 struct qreg undef; 481 enum qstage stage; 482 uint32_t num_temps; 483 484 struct list_head blocks; 485 int next_block_index; 486 struct qblock *cur_block; 487 struct qblock *loop_cont_block; 488 struct qblock *loop_break_block; 489 490 struct list_head qpu_inst_list; 491 492 uint64_t *qpu_insts; 493 uint32_t qpu_inst_count; 494 uint32_t qpu_inst_size; 495 uint32_t num_inputs; 496 497 uint32_t program_id; 498 uint32_t variant_id; 499}; 500 501/* Special nir_load_input intrinsic index for loading the current TLB 502 * destination color. 503 */ 504#define VC4_NIR_TLB_COLOR_READ_INPUT 2000000000 505 506#define VC4_NIR_MS_MASK_OUTPUT 2000000000 507 508/* Special offset for nir_load_uniform values to get a QUNIFORM_* 509 * state-dependent value. 510 */ 511#define VC4_NIR_STATE_UNIFORM_OFFSET 1000000000 512 513struct vc4_compile *qir_compile_init(void); 514void qir_compile_destroy(struct vc4_compile *c); 515struct qblock *qir_new_block(struct vc4_compile *c); 516void qir_set_emit_block(struct vc4_compile *c, struct qblock *block); 517void qir_link_blocks(struct qblock *predecessor, struct qblock *successor); 518struct qblock *qir_entry_block(struct vc4_compile *c); 519struct qblock *qir_exit_block(struct vc4_compile *c); 520struct qinst *qir_inst(enum qop op, struct qreg dst, 521 struct qreg src0, struct qreg src1); 522struct qinst *qir_inst4(enum qop op, struct qreg dst, 523 struct qreg a, 524 struct qreg b, 525 struct qreg c, 526 struct qreg d); 527void qir_remove_instruction(struct vc4_compile *c, struct qinst *qinst); 528struct qreg qir_uniform(struct vc4_compile *c, 529 enum quniform_contents contents, 530 uint32_t data); 531void qir_schedule_instructions(struct vc4_compile *c); 532void qir_reorder_uniforms(struct vc4_compile *c); 533void qir_emit_uniform_stream_resets(struct vc4_compile *c); 534 535struct qreg qir_emit_def(struct vc4_compile *c, struct qinst *inst); 536struct qinst *qir_emit_nondef(struct vc4_compile *c, struct qinst *inst); 537 538struct qreg qir_get_temp(struct vc4_compile *c); 539void qir_calculate_live_intervals(struct vc4_compile *c); 540int qir_get_op_nsrc(enum qop qop); 541bool qir_reg_equals(struct qreg a, struct qreg b); 542bool qir_has_side_effects(struct vc4_compile *c, struct qinst *inst); 543bool qir_has_side_effect_reads(struct vc4_compile *c, struct qinst *inst); 544bool qir_is_mul(struct qinst *inst); 545bool qir_is_raw_mov(struct qinst *inst); 546bool qir_is_tex(struct qinst *inst); 547bool qir_is_float_input(struct qinst *inst); 548bool qir_depends_on_flags(struct qinst *inst); 549bool qir_writes_r4(struct qinst *inst); 550struct qreg qir_follow_movs(struct vc4_compile *c, struct qreg reg); 551uint8_t qir_channels_written(struct qinst *inst); 552 553void qir_dump(struct vc4_compile *c); 554void qir_dump_inst(struct vc4_compile *c, struct qinst *inst); 555const char *qir_get_stage_name(enum qstage stage); 556 557void qir_validate(struct vc4_compile *c); 558 559void qir_optimize(struct vc4_compile *c); 560bool qir_opt_algebraic(struct vc4_compile *c); 561bool qir_opt_constant_folding(struct vc4_compile *c); 562bool qir_opt_copy_propagation(struct vc4_compile *c); 563bool qir_opt_dead_code(struct vc4_compile *c); 564bool qir_opt_peephole_sf(struct vc4_compile *c); 565bool qir_opt_small_immediates(struct vc4_compile *c); 566bool qir_opt_vpm(struct vc4_compile *c); 567void vc4_nir_lower_blend(nir_shader *s, struct vc4_compile *c); 568void vc4_nir_lower_io(nir_shader *s, struct vc4_compile *c); 569nir_ssa_def *vc4_nir_get_state_uniform(struct nir_builder *b, 570 enum quniform_contents contents); 571nir_ssa_def *vc4_nir_get_swizzled_channel(struct nir_builder *b, 572 nir_ssa_def **srcs, int swiz); 573void vc4_nir_lower_txf_ms(nir_shader *s, struct vc4_compile *c); 574void qir_lower_uniforms(struct vc4_compile *c); 575 576uint32_t qpu_schedule_instructions(struct vc4_compile *c); 577 578void qir_SF(struct vc4_compile *c, struct qreg src); 579 580static inline struct qreg 581qir_uniform_ui(struct vc4_compile *c, uint32_t ui) 582{ 583 return qir_uniform(c, QUNIFORM_CONSTANT, ui); 584} 585 586static inline struct qreg 587qir_uniform_f(struct vc4_compile *c, float f) 588{ 589 return qir_uniform(c, QUNIFORM_CONSTANT, fui(f)); 590} 591 592#define QIR_ALU0(name) \ 593static inline struct qreg \ 594qir_##name(struct vc4_compile *c) \ 595{ \ 596 return qir_emit_def(c, qir_inst(QOP_##name, c->undef, \ 597 c->undef, c->undef)); \ 598} \ 599static inline struct qinst * \ 600qir_##name##_dest(struct vc4_compile *c, struct qreg dest) \ 601{ \ 602 return qir_emit_nondef(c, qir_inst(QOP_##name, dest, \ 603 c->undef, c->undef)); \ 604} 605 606#define QIR_ALU1(name) \ 607static inline struct qreg \ 608qir_##name(struct vc4_compile *c, struct qreg a) \ 609{ \ 610 return qir_emit_def(c, qir_inst(QOP_##name, c->undef, \ 611 a, c->undef)); \ 612} \ 613static inline struct qinst * \ 614qir_##name##_dest(struct vc4_compile *c, struct qreg dest, \ 615 struct qreg a) \ 616{ \ 617 return qir_emit_nondef(c, qir_inst(QOP_##name, dest, a, \ 618 c->undef)); \ 619} 620 621#define QIR_ALU2(name) \ 622static inline struct qreg \ 623qir_##name(struct vc4_compile *c, struct qreg a, struct qreg b) \ 624{ \ 625 return qir_emit_def(c, qir_inst(QOP_##name, c->undef, a, b)); \ 626} \ 627static inline struct qinst * \ 628qir_##name##_dest(struct vc4_compile *c, struct qreg dest, \ 629 struct qreg a, struct qreg b) \ 630{ \ 631 return qir_emit_nondef(c, qir_inst(QOP_##name, dest, a, b)); \ 632} 633 634#define QIR_NODST_1(name) \ 635static inline struct qinst * \ 636qir_##name(struct vc4_compile *c, struct qreg a) \ 637{ \ 638 return qir_emit_nondef(c, qir_inst(QOP_##name, c->undef, \ 639 a, c->undef)); \ 640} 641 642#define QIR_NODST_2(name) \ 643static inline struct qinst * \ 644qir_##name(struct vc4_compile *c, struct qreg a, struct qreg b) \ 645{ \ 646 return qir_emit_nondef(c, qir_inst(QOP_##name, c->undef, \ 647 a, b)); \ 648} 649 650#define QIR_PAYLOAD(name) \ 651static inline struct qreg \ 652qir_##name(struct vc4_compile *c) \ 653{ \ 654 struct qreg *payload = &c->payload_##name; \ 655 if (payload->file != QFILE_NULL) \ 656 return *payload; \ 657 *payload = qir_get_temp(c); \ 658 struct qinst *inst = qir_inst(QOP_##name, *payload, \ 659 c->undef, c->undef); \ 660 struct qblock *entry = qir_entry_block(c); \ 661 list_add(&inst->link, &entry->instructions); \ 662 c->defs[payload->index] = inst; \ 663 return *payload; \ 664} 665 666QIR_ALU1(MOV) 667QIR_ALU1(FMOV) 668QIR_ALU1(MMOV) 669QIR_ALU2(FADD) 670QIR_ALU2(FSUB) 671QIR_ALU2(FMUL) 672QIR_ALU2(V8MULD) 673QIR_ALU2(V8MIN) 674QIR_ALU2(V8MAX) 675QIR_ALU2(V8ADDS) 676QIR_ALU2(V8SUBS) 677QIR_ALU2(MUL24) 678QIR_ALU2(FMIN) 679QIR_ALU2(FMAX) 680QIR_ALU2(FMINABS) 681QIR_ALU2(FMAXABS) 682QIR_ALU1(FTOI) 683QIR_ALU1(ITOF) 684 685QIR_ALU2(ADD) 686QIR_ALU2(SUB) 687QIR_ALU2(SHL) 688QIR_ALU2(SHR) 689QIR_ALU2(ASR) 690QIR_ALU2(MIN) 691QIR_ALU2(MAX) 692QIR_ALU2(AND) 693QIR_ALU2(OR) 694QIR_ALU2(XOR) 695QIR_ALU1(NOT) 696 697QIR_ALU1(RCP) 698QIR_ALU1(RSQ) 699QIR_ALU1(EXP2) 700QIR_ALU1(LOG2) 701QIR_ALU1(VARY_ADD_C) 702QIR_NODST_2(TEX_S) 703QIR_NODST_2(TEX_T) 704QIR_NODST_2(TEX_R) 705QIR_NODST_2(TEX_B) 706QIR_NODST_2(TEX_DIRECT) 707QIR_PAYLOAD(FRAG_Z) 708QIR_PAYLOAD(FRAG_W) 709QIR_ALU0(TEX_RESULT) 710QIR_ALU0(TLB_COLOR_READ) 711QIR_NODST_1(MS_MASK) 712 713static inline struct qreg 714qir_SEL(struct vc4_compile *c, uint8_t cond, struct qreg src0, struct qreg src1) 715{ 716 struct qreg t = qir_get_temp(c); 717 struct qinst *a = qir_MOV_dest(c, t, src0); 718 struct qinst *b = qir_MOV_dest(c, t, src1); 719 a->cond = cond; 720 b->cond = qpu_cond_complement(cond); 721 return t; 722} 723 724static inline struct qreg 725qir_UNPACK_8_F(struct vc4_compile *c, struct qreg src, int i) 726{ 727 struct qreg t = qir_FMOV(c, src); 728 c->defs[t.index]->src[0].pack = QPU_UNPACK_8A + i; 729 return t; 730} 731 732static inline struct qreg 733qir_UNPACK_8_I(struct vc4_compile *c, struct qreg src, int i) 734{ 735 struct qreg t = qir_MOV(c, src); 736 c->defs[t.index]->src[0].pack = QPU_UNPACK_8A + i; 737 return t; 738} 739 740static inline struct qreg 741qir_UNPACK_16_F(struct vc4_compile *c, struct qreg src, int i) 742{ 743 struct qreg t = qir_FMOV(c, src); 744 c->defs[t.index]->src[0].pack = QPU_UNPACK_16A + i; 745 return t; 746} 747 748static inline struct qreg 749qir_UNPACK_16_I(struct vc4_compile *c, struct qreg src, int i) 750{ 751 struct qreg t = qir_MOV(c, src); 752 c->defs[t.index]->src[0].pack = QPU_UNPACK_16A + i; 753 return t; 754} 755 756static inline void 757qir_PACK_8_F(struct vc4_compile *c, struct qreg dest, struct qreg val, int chan) 758{ 759 assert(!dest.pack); 760 dest.pack = QPU_PACK_MUL_8A + chan; 761 qir_emit_nondef(c, qir_inst(QOP_MMOV, dest, val, c->undef)); 762} 763 764static inline struct qreg 765qir_PACK_8888_F(struct vc4_compile *c, struct qreg val) 766{ 767 struct qreg dest = qir_MMOV(c, val); 768 c->defs[dest.index]->dst.pack = QPU_PACK_MUL_8888; 769 return dest; 770} 771 772static inline struct qreg 773qir_POW(struct vc4_compile *c, struct qreg x, struct qreg y) 774{ 775 return qir_EXP2(c, qir_FMUL(c, 776 y, 777 qir_LOG2(c, x))); 778} 779 780static inline void 781qir_VPM_WRITE(struct vc4_compile *c, struct qreg val) 782{ 783 qir_MOV_dest(c, qir_reg(QFILE_VPM, 0), val); 784} 785 786static inline struct qreg 787qir_LOAD_IMM(struct vc4_compile *c, uint32_t val) 788{ 789 return qir_emit_def(c, qir_inst(QOP_LOAD_IMM, c->undef, 790 qir_reg(QFILE_LOAD_IMM, val), c->undef)); 791} 792 793static inline void 794qir_MOV_cond(struct vc4_compile *c, uint8_t cond, 795 struct qreg dest, struct qreg src) 796{ 797 qir_MOV_dest(c, dest, src)->cond = cond; 798} 799 800static inline struct qinst * 801qir_BRANCH(struct vc4_compile *c, uint8_t cond) 802{ 803 struct qinst *inst = qir_inst(QOP_BRANCH, c->undef, c->undef, c->undef); 804 inst->cond = cond; 805 qir_emit_nondef(c, inst); 806 return inst; 807} 808 809#define qir_for_each_block(block, c) \ 810 list_for_each_entry(struct qblock, block, &c->blocks, link) 811 812#define qir_for_each_block_rev(block, c) \ 813 list_for_each_entry_rev(struct qblock, block, &c->blocks, link) 814 815/* Loop over the non-NULL members of the successors array. */ 816#define qir_for_each_successor(succ, block) \ 817 for (struct qblock *succ = block->successors[0]; \ 818 succ != NULL; \ 819 succ = (succ == block->successors[1] ? NULL : \ 820 block->successors[1])) 821 822#define qir_for_each_inst(inst, block) \ 823 list_for_each_entry(struct qinst, inst, &block->instructions, link) 824 825#define qir_for_each_inst_rev(inst, block) \ 826 list_for_each_entry_rev(struct qinst, inst, &block->instructions, link) 827 828#define qir_for_each_inst_safe(inst, block) \ 829 list_for_each_entry_safe(struct qinst, inst, &block->instructions, link) 830 831#define qir_for_each_inst_inorder(inst, c) \ 832 qir_for_each_block(_block, c) \ 833 qir_for_each_inst(inst, _block) 834 835#endif /* VC4_QIR_H */ 836