vc4_qir.h revision 2b9f0dffe00bdc556436da02c099b8a50ecc4f49
1/* 2 * Copyright © 2014 Broadcom 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24#ifndef VC4_QIR_H 25#define VC4_QIR_H 26 27#include <assert.h> 28#include <stdio.h> 29#include <stdlib.h> 30#include <stdbool.h> 31#include <stdint.h> 32#include <string.h> 33 34#include "util/macros.h" 35#include "compiler/nir/nir.h" 36#include "util/list.h" 37#include "util/u_math.h" 38 39#include "vc4_screen.h" 40#include "vc4_qpu_defines.h" 41#include "kernel/vc4_packet.h" 42#include "pipe/p_state.h" 43 44struct nir_builder; 45 46enum qfile { 47 QFILE_NULL, 48 QFILE_TEMP, 49 QFILE_VARY, 50 QFILE_UNIF, 51 QFILE_VPM, 52 53 /** 54 * Stores an immediate value in the index field that can be turned 55 * into a small immediate field by qpu_encode_small_immediate(). 56 */ 57 QFILE_SMALL_IMM, 58}; 59 60struct qreg { 61 enum qfile file; 62 uint32_t index; 63 int pack; 64}; 65 66enum qop { 67 QOP_UNDEF, 68 QOP_MOV, 69 QOP_FMOV, 70 QOP_MMOV, 71 QOP_FADD, 72 QOP_FSUB, 73 QOP_FMUL, 74 QOP_V8MULD, 75 QOP_V8MIN, 76 QOP_V8MAX, 77 QOP_V8ADDS, 78 QOP_V8SUBS, 79 QOP_MUL24, 80 QOP_FMIN, 81 QOP_FMAX, 82 QOP_FMINABS, 83 QOP_FMAXABS, 84 QOP_ADD, 85 QOP_SUB, 86 QOP_SHL, 87 QOP_SHR, 88 QOP_ASR, 89 QOP_MIN, 90 QOP_MAX, 91 QOP_AND, 92 QOP_OR, 93 QOP_XOR, 94 QOP_NOT, 95 96 QOP_FTOI, 97 QOP_ITOF, 98 QOP_RCP, 99 QOP_RSQ, 100 QOP_EXP2, 101 QOP_LOG2, 102 QOP_VW_SETUP, 103 QOP_VR_SETUP, 104 QOP_TLB_STENCIL_SETUP, 105 QOP_TLB_Z_WRITE, 106 QOP_TLB_COLOR_WRITE, 107 QOP_TLB_COLOR_WRITE_MS, 108 QOP_TLB_COLOR_READ, 109 QOP_MS_MASK, 110 QOP_VARY_ADD_C, 111 112 QOP_FRAG_X, 113 QOP_FRAG_Y, 114 QOP_FRAG_Z, 115 QOP_FRAG_W, 116 QOP_FRAG_REV_FLAG, 117 118 /** Texture x coordinate parameter write */ 119 QOP_TEX_S, 120 /** Texture y coordinate parameter write */ 121 QOP_TEX_T, 122 /** Texture border color parameter or cube map z coordinate write */ 123 QOP_TEX_R, 124 /** Texture LOD bias parameter write */ 125 QOP_TEX_B, 126 127 /** 128 * Texture-unit 4-byte read with address provided direct in S 129 * cooordinate. 130 * 131 * The first operand is the offset from the start of the UBO, and the 132 * second is the uniform that has the UBO's base pointer. 133 */ 134 QOP_TEX_DIRECT, 135 136 /** 137 * Signal of texture read being necessary and then reading r4 into 138 * the destination 139 */ 140 QOP_TEX_RESULT, 141}; 142 143struct queued_qpu_inst { 144 struct list_head link; 145 uint64_t inst; 146}; 147 148struct qinst { 149 struct list_head link; 150 151 enum qop op; 152 struct qreg dst; 153 struct qreg *src; 154 bool sf; 155 uint8_t cond; 156}; 157 158enum qstage { 159 /** 160 * Coordinate shader, runs during binning, before the VS, and just 161 * outputs position. 162 */ 163 QSTAGE_COORD, 164 QSTAGE_VERT, 165 QSTAGE_FRAG, 166}; 167 168enum quniform_contents { 169 /** 170 * Indicates that a constant 32-bit value is copied from the program's 171 * uniform contents. 172 */ 173 QUNIFORM_CONSTANT, 174 /** 175 * Indicates that the program's uniform contents are used as an index 176 * into the GL uniform storage. 177 */ 178 QUNIFORM_UNIFORM, 179 180 /** @{ 181 * Scaling factors from clip coordinates to relative to the viewport 182 * center. 183 * 184 * This is used by the coordinate and vertex shaders to produce the 185 * 32-bit entry consisting of 2 16-bit fields with 12.4 signed fixed 186 * point offsets from the viewport ccenter. 187 */ 188 QUNIFORM_VIEWPORT_X_SCALE, 189 QUNIFORM_VIEWPORT_Y_SCALE, 190 /** @} */ 191 192 QUNIFORM_VIEWPORT_Z_OFFSET, 193 QUNIFORM_VIEWPORT_Z_SCALE, 194 195 QUNIFORM_USER_CLIP_PLANE, 196 197 /** 198 * A reference to a texture config parameter 0 uniform. 199 * 200 * This is a uniform implicitly loaded with a QPU_W_TMU* write, which 201 * defines texture type, miplevels, and such. It will be found as a 202 * parameter to the first QOP_TEX_[STRB] instruction in a sequence. 203 */ 204 QUNIFORM_TEXTURE_CONFIG_P0, 205 206 /** 207 * A reference to a texture config parameter 1 uniform. 208 * 209 * This is a uniform implicitly loaded with a QPU_W_TMU* write, which 210 * defines texture width, height, filters, and wrap modes. It will be 211 * found as a parameter to the second QOP_TEX_[STRB] instruction in a 212 * sequence. 213 */ 214 QUNIFORM_TEXTURE_CONFIG_P1, 215 216 /** A reference to a texture config parameter 2 cubemap stride uniform */ 217 QUNIFORM_TEXTURE_CONFIG_P2, 218 219 QUNIFORM_TEXTURE_MSAA_ADDR, 220 221 QUNIFORM_UBO_ADDR, 222 223 QUNIFORM_TEXRECT_SCALE_X, 224 QUNIFORM_TEXRECT_SCALE_Y, 225 226 QUNIFORM_TEXTURE_BORDER_COLOR, 227 228 QUNIFORM_BLEND_CONST_COLOR_X, 229 QUNIFORM_BLEND_CONST_COLOR_Y, 230 QUNIFORM_BLEND_CONST_COLOR_Z, 231 QUNIFORM_BLEND_CONST_COLOR_W, 232 QUNIFORM_BLEND_CONST_COLOR_RGBA, 233 QUNIFORM_BLEND_CONST_COLOR_AAAA, 234 235 QUNIFORM_STENCIL, 236 237 QUNIFORM_ALPHA_REF, 238 QUNIFORM_SAMPLE_MASK, 239}; 240 241struct vc4_varying_slot { 242 uint8_t slot; 243 uint8_t swizzle; 244}; 245 246struct vc4_compiler_ubo_range { 247 /** 248 * offset in bytes from the start of the ubo where this range is 249 * uploaded. 250 * 251 * Only set once used is set. 252 */ 253 uint32_t dst_offset; 254 255 /** 256 * offset in bytes from the start of the gallium uniforms where the 257 * data comes from. 258 */ 259 uint32_t src_offset; 260 261 /** size in bytes of this ubo range */ 262 uint32_t size; 263 264 /** 265 * Set if this range is used by the shader for indirect uniforms 266 * access. 267 */ 268 bool used; 269}; 270 271struct vc4_key { 272 struct vc4_uncompiled_shader *shader_state; 273 struct { 274 enum pipe_format format; 275 uint8_t swizzle[4]; 276 union { 277 struct { 278 unsigned compare_mode:1; 279 unsigned compare_func:3; 280 unsigned wrap_s:3; 281 unsigned wrap_t:3; 282 }; 283 struct { 284 uint16_t msaa_width, msaa_height; 285 }; 286 }; 287 } tex[VC4_MAX_TEXTURE_SAMPLERS]; 288 uint8_t ucp_enables; 289}; 290 291struct vc4_fs_key { 292 struct vc4_key base; 293 enum pipe_format color_format; 294 bool depth_enabled; 295 bool stencil_enabled; 296 bool stencil_twoside; 297 bool stencil_full_writemasks; 298 bool is_points; 299 bool is_lines; 300 bool alpha_test; 301 bool point_coord_upper_left; 302 bool light_twoside; 303 bool msaa; 304 bool sample_coverage; 305 bool sample_alpha_to_coverage; 306 bool sample_alpha_to_one; 307 uint8_t alpha_test_func; 308 uint8_t logicop_func; 309 uint32_t point_sprite_mask; 310 311 struct pipe_rt_blend_state blend; 312}; 313 314struct vc4_vs_key { 315 struct vc4_key base; 316 317 /** 318 * This is a proxy for the array of FS input semantics, which is 319 * larger than we would want to put in the key. 320 */ 321 uint64_t compiled_fs_id; 322 323 enum pipe_format attr_formats[8]; 324 bool is_coord; 325 bool per_vertex_point_size; 326}; 327 328struct vc4_compile { 329 struct vc4_context *vc4; 330 nir_shader *s; 331 nir_function_impl *impl; 332 struct exec_list *cf_node_list; 333 334 /** 335 * Mapping from nir_register * or nir_ssa_def * to array of struct 336 * qreg for the values. 337 */ 338 struct hash_table *def_ht; 339 340 /* For each temp, the instruction generating its value. */ 341 struct qinst **defs; 342 uint32_t defs_array_size; 343 344 /** 345 * Inputs to the shader, arranged by TGSI declaration order. 346 * 347 * Not all fragment shader QFILE_VARY reads are present in this array. 348 */ 349 struct qreg *inputs; 350 struct qreg *outputs; 351 bool msaa_per_sample_output; 352 struct qreg color_reads[VC4_MAX_SAMPLES]; 353 struct qreg sample_colors[VC4_MAX_SAMPLES]; 354 uint32_t inputs_array_size; 355 uint32_t outputs_array_size; 356 uint32_t uniforms_array_size; 357 358 struct vc4_compiler_ubo_range *ubo_ranges; 359 uint32_t ubo_ranges_array_size; 360 /** Number of uniform areas declared in ubo_ranges. */ 361 uint32_t num_uniform_ranges; 362 /** Number of uniform areas used for indirect addressed loads. */ 363 uint32_t num_ubo_ranges; 364 uint32_t next_ubo_dst_offset; 365 366 struct qreg line_x, point_x, point_y; 367 struct qreg discard; 368 369 uint8_t vattr_sizes[8]; 370 371 /* Bitfield for whether a given channel of a sampler needs sRGB 372 * decode. 373 */ 374 uint8_t tex_srgb_decode[VC4_MAX_TEXTURE_SAMPLERS]; 375 376 /** 377 * Array of the VARYING_SLOT_* of all FS QFILE_VARY reads. 378 * 379 * This includes those that aren't part of the VPM varyings, like 380 * point/line coordinates. 381 */ 382 struct vc4_varying_slot *input_slots; 383 uint32_t num_input_slots; 384 uint32_t input_slots_array_size; 385 386 /** 387 * An entry per outputs[] in the VS indicating what the VARYING_SLOT_* 388 * of the output is. Used to emit from the VS in the order that the 389 * FS needs. 390 */ 391 struct vc4_varying_slot *output_slots; 392 393 struct pipe_shader_state *shader_state; 394 struct vc4_key *key; 395 struct vc4_fs_key *fs_key; 396 struct vc4_vs_key *vs_key; 397 398 uint32_t *uniform_data; 399 enum quniform_contents *uniform_contents; 400 uint32_t uniform_array_size; 401 uint32_t num_uniforms; 402 uint32_t num_outputs; 403 uint32_t num_texture_samples; 404 uint32_t output_position_index; 405 uint32_t output_color_index; 406 uint32_t output_point_size_index; 407 uint32_t output_sample_mask_index; 408 409 struct qreg undef; 410 enum qstage stage; 411 uint32_t num_temps; 412 struct list_head instructions; 413 uint32_t immediates[1024]; 414 415 struct list_head qpu_inst_list; 416 uint64_t *qpu_insts; 417 uint32_t qpu_inst_count; 418 uint32_t qpu_inst_size; 419 uint32_t num_inputs; 420 421 uint32_t program_id; 422 uint32_t variant_id; 423}; 424 425/* Special nir_load_input intrinsic index for loading the current TLB 426 * destination color. 427 */ 428#define VC4_NIR_TLB_COLOR_READ_INPUT 2000000000 429 430#define VC4_NIR_MS_MASK_OUTPUT 2000000000 431 432/* Special offset for nir_load_uniform values to get a QUNIFORM_* 433 * state-dependent value. 434 */ 435#define VC4_NIR_STATE_UNIFORM_OFFSET 1000000000 436 437struct vc4_compile *qir_compile_init(void); 438void qir_compile_destroy(struct vc4_compile *c); 439struct qinst *qir_inst(enum qop op, struct qreg dst, 440 struct qreg src0, struct qreg src1); 441struct qinst *qir_inst4(enum qop op, struct qreg dst, 442 struct qreg a, 443 struct qreg b, 444 struct qreg c, 445 struct qreg d); 446void qir_remove_instruction(struct vc4_compile *c, struct qinst *qinst); 447struct qreg qir_uniform(struct vc4_compile *c, 448 enum quniform_contents contents, 449 uint32_t data); 450void qir_schedule_instructions(struct vc4_compile *c); 451void qir_reorder_uniforms(struct vc4_compile *c); 452 453void qir_emit(struct vc4_compile *c, struct qinst *inst); 454static inline struct qinst * 455qir_emit_nodef(struct vc4_compile *c, struct qinst *inst) 456{ 457 list_addtail(&inst->link, &c->instructions); 458 return inst; 459} 460 461struct qreg qir_get_temp(struct vc4_compile *c); 462int qir_get_op_nsrc(enum qop qop); 463bool qir_reg_equals(struct qreg a, struct qreg b); 464bool qir_has_side_effects(struct vc4_compile *c, struct qinst *inst); 465bool qir_has_side_effect_reads(struct vc4_compile *c, struct qinst *inst); 466bool qir_is_multi_instruction(struct qinst *inst); 467bool qir_is_mul(struct qinst *inst); 468bool qir_is_raw_mov(struct qinst *inst); 469bool qir_is_tex(struct qinst *inst); 470bool qir_is_float_input(struct qinst *inst); 471bool qir_depends_on_flags(struct qinst *inst); 472bool qir_writes_r4(struct qinst *inst); 473struct qreg qir_follow_movs(struct vc4_compile *c, struct qreg reg); 474 475void qir_dump(struct vc4_compile *c); 476void qir_dump_inst(struct vc4_compile *c, struct qinst *inst); 477const char *qir_get_stage_name(enum qstage stage); 478 479void qir_optimize(struct vc4_compile *c); 480bool qir_opt_algebraic(struct vc4_compile *c); 481bool qir_opt_constant_folding(struct vc4_compile *c); 482bool qir_opt_copy_propagation(struct vc4_compile *c); 483bool qir_opt_cse(struct vc4_compile *c); 484bool qir_opt_dead_code(struct vc4_compile *c); 485bool qir_opt_small_immediates(struct vc4_compile *c); 486bool qir_opt_vpm(struct vc4_compile *c); 487void vc4_nir_lower_blend(struct vc4_compile *c); 488void vc4_nir_lower_io(struct vc4_compile *c); 489nir_ssa_def *vc4_nir_get_state_uniform(struct nir_builder *b, 490 enum quniform_contents contents); 491nir_ssa_def *vc4_nir_get_swizzled_channel(struct nir_builder *b, 492 nir_ssa_def **srcs, int swiz); 493void vc4_nir_lower_txf_ms(struct vc4_compile *c); 494void qir_lower_uniforms(struct vc4_compile *c); 495 496uint32_t qpu_schedule_instructions(struct vc4_compile *c); 497 498void qir_SF(struct vc4_compile *c, struct qreg src); 499 500static inline struct qreg 501qir_uniform_ui(struct vc4_compile *c, uint32_t ui) 502{ 503 return qir_uniform(c, QUNIFORM_CONSTANT, ui); 504} 505 506static inline struct qreg 507qir_uniform_f(struct vc4_compile *c, float f) 508{ 509 return qir_uniform(c, QUNIFORM_CONSTANT, fui(f)); 510} 511 512#define QIR_ALU0(name) \ 513static inline struct qreg \ 514qir_##name(struct vc4_compile *c) \ 515{ \ 516 struct qreg t = qir_get_temp(c); \ 517 qir_emit(c, qir_inst(QOP_##name, t, c->undef, c->undef)); \ 518 return t; \ 519} 520 521#define QIR_ALU1(name) \ 522static inline struct qreg \ 523qir_##name(struct vc4_compile *c, struct qreg a) \ 524{ \ 525 struct qreg t = qir_get_temp(c); \ 526 qir_emit(c, qir_inst(QOP_##name, t, a, c->undef)); \ 527 return t; \ 528} \ 529static inline struct qinst * \ 530qir_##name##_dest(struct vc4_compile *c, struct qreg dest, \ 531 struct qreg a) \ 532{ \ 533 return qir_emit_nodef(c, qir_inst(QOP_##name, dest, a, \ 534 c->undef)); \ 535} 536 537#define QIR_ALU2(name) \ 538static inline struct qreg \ 539qir_##name(struct vc4_compile *c, struct qreg a, struct qreg b) \ 540{ \ 541 struct qreg t = qir_get_temp(c); \ 542 qir_emit(c, qir_inst(QOP_##name, t, a, b)); \ 543 return t; \ 544} \ 545static inline void \ 546qir_##name##_dest(struct vc4_compile *c, struct qreg dest, \ 547 struct qreg a, struct qreg b) \ 548{ \ 549 qir_emit_nodef(c, qir_inst(QOP_##name, dest, a, b)); \ 550} 551 552#define QIR_NODST_1(name) \ 553static inline struct qinst * \ 554qir_##name(struct vc4_compile *c, struct qreg a) \ 555{ \ 556 struct qinst *inst = qir_inst(QOP_##name, c->undef, \ 557 a, c->undef); \ 558 qir_emit(c, inst); \ 559 return inst; \ 560} 561 562#define QIR_NODST_2(name) \ 563static inline struct qinst * \ 564qir_##name(struct vc4_compile *c, struct qreg a, struct qreg b) \ 565{ \ 566 struct qinst *inst = qir_inst(QOP_##name, c->undef, \ 567 a, b); \ 568 qir_emit(c, inst); \ 569 return inst; \ 570} 571 572#define QIR_PACK(name) \ 573static inline struct qreg \ 574qir_##name(struct vc4_compile *c, struct qreg dest, struct qreg a) \ 575{ \ 576 qir_emit_nodef(c, qir_inst(QOP_##name, dest, a, c->undef)); \ 577 return dest; \ 578} 579 580QIR_ALU1(MOV) 581QIR_ALU1(FMOV) 582QIR_ALU1(MMOV) 583QIR_ALU2(FADD) 584QIR_ALU2(FSUB) 585QIR_ALU2(FMUL) 586QIR_ALU2(V8MULD) 587QIR_ALU2(V8MIN) 588QIR_ALU2(V8MAX) 589QIR_ALU2(V8ADDS) 590QIR_ALU2(V8SUBS) 591QIR_ALU2(MUL24) 592QIR_ALU2(FMIN) 593QIR_ALU2(FMAX) 594QIR_ALU2(FMINABS) 595QIR_ALU2(FMAXABS) 596QIR_ALU1(FTOI) 597QIR_ALU1(ITOF) 598 599QIR_ALU2(ADD) 600QIR_ALU2(SUB) 601QIR_ALU2(SHL) 602QIR_ALU2(SHR) 603QIR_ALU2(ASR) 604QIR_ALU2(MIN) 605QIR_ALU2(MAX) 606QIR_ALU2(AND) 607QIR_ALU2(OR) 608QIR_ALU2(XOR) 609QIR_ALU1(NOT) 610 611QIR_ALU1(RCP) 612QIR_ALU1(RSQ) 613QIR_ALU1(EXP2) 614QIR_ALU1(LOG2) 615QIR_ALU1(VARY_ADD_C) 616QIR_NODST_2(TEX_S) 617QIR_NODST_2(TEX_T) 618QIR_NODST_2(TEX_R) 619QIR_NODST_2(TEX_B) 620QIR_NODST_2(TEX_DIRECT) 621QIR_ALU0(FRAG_X) 622QIR_ALU0(FRAG_Y) 623QIR_ALU0(FRAG_Z) 624QIR_ALU0(FRAG_W) 625QIR_ALU0(FRAG_REV_FLAG) 626QIR_ALU0(TEX_RESULT) 627QIR_ALU0(TLB_COLOR_READ) 628QIR_NODST_1(TLB_COLOR_WRITE) 629QIR_NODST_1(TLB_COLOR_WRITE_MS) 630QIR_NODST_1(TLB_Z_WRITE) 631QIR_NODST_1(TLB_STENCIL_SETUP) 632QIR_NODST_1(MS_MASK) 633 634static inline struct qreg 635qir_SEL(struct vc4_compile *c, uint8_t cond, struct qreg src0, struct qreg src1) 636{ 637 struct qreg t = qir_get_temp(c); 638 struct qinst *a = qir_MOV_dest(c, t, src0); 639 struct qinst *b = qir_MOV_dest(c, t, src1); 640 a->cond = cond; 641 b->cond = cond ^ 1; 642 return t; 643} 644 645static inline struct qreg 646qir_UNPACK_8_F(struct vc4_compile *c, struct qreg src, int i) 647{ 648 struct qreg t = qir_FMOV(c, src); 649 c->defs[t.index]->src[0].pack = QPU_UNPACK_8A + i; 650 return t; 651} 652 653static inline struct qreg 654qir_UNPACK_8_I(struct vc4_compile *c, struct qreg src, int i) 655{ 656 struct qreg t = qir_MOV(c, src); 657 c->defs[t.index]->src[0].pack = QPU_UNPACK_8A + i; 658 return t; 659} 660 661static inline struct qreg 662qir_UNPACK_16_F(struct vc4_compile *c, struct qreg src, int i) 663{ 664 struct qreg t = qir_FMOV(c, src); 665 c->defs[t.index]->src[0].pack = QPU_UNPACK_16A + i; 666 return t; 667} 668 669static inline struct qreg 670qir_UNPACK_16_I(struct vc4_compile *c, struct qreg src, int i) 671{ 672 struct qreg t = qir_MOV(c, src); 673 c->defs[t.index]->src[0].pack = QPU_UNPACK_16A + i; 674 return t; 675} 676 677static inline void 678qir_PACK_8_F(struct vc4_compile *c, struct qreg dest, struct qreg val, int chan) 679{ 680 assert(!dest.pack); 681 dest.pack = QPU_PACK_MUL_8A + chan; 682 qir_emit(c, qir_inst(QOP_MMOV, dest, val, c->undef)); 683 if (dest.file == QFILE_TEMP) 684 c->defs[dest.index] = NULL; 685} 686 687static inline struct qreg 688qir_PACK_8888_F(struct vc4_compile *c, struct qreg val) 689{ 690 struct qreg dest = qir_MMOV(c, val); 691 c->defs[dest.index]->dst.pack = QPU_PACK_MUL_8888; 692 return dest; 693} 694 695static inline struct qreg 696qir_POW(struct vc4_compile *c, struct qreg x, struct qreg y) 697{ 698 return qir_EXP2(c, qir_FMUL(c, 699 y, 700 qir_LOG2(c, x))); 701} 702 703static inline void 704qir_VPM_WRITE(struct vc4_compile *c, struct qreg val) 705{ 706 static const struct qreg vpm = { QFILE_VPM, 0 }; 707 qir_emit(c, qir_inst(QOP_MOV, vpm, val, c->undef)); 708} 709 710#endif /* VC4_QIR_H */ 711