vc4_qir.h revision 3bcd0f1912a60cc9d3813923d18d29465e41ff56
1/* 2 * Copyright © 2014 Broadcom 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24#ifndef VC4_QIR_H 25#define VC4_QIR_H 26 27#include <assert.h> 28#include <stdio.h> 29#include <stdlib.h> 30#include <stdbool.h> 31#include <stdint.h> 32#include <string.h> 33 34#include "util/macros.h" 35#include "compiler/nir/nir.h" 36#include "util/list.h" 37#include "util/u_math.h" 38 39#include "vc4_screen.h" 40#include "vc4_qpu_defines.h" 41#include "vc4_qpu.h" 42#include "kernel/vc4_packet.h" 43#include "pipe/p_state.h" 44 45struct nir_builder; 46 47enum qfile { 48 QFILE_NULL, 49 QFILE_TEMP, 50 QFILE_VARY, 51 QFILE_UNIF, 52 QFILE_VPM, 53 QFILE_TLB_COLOR_WRITE, 54 QFILE_TLB_COLOR_WRITE_MS, 55 QFILE_TLB_Z_WRITE, 56 QFILE_TLB_STENCIL_SETUP, 57 58 /* Payload registers that aren't in the physical register file, so we 59 * can just use the corresponding qpu_reg at qpu_emit time. 60 */ 61 QFILE_FRAG_X, 62 QFILE_FRAG_Y, 63 QFILE_FRAG_REV_FLAG, 64 65 /** 66 * Stores an immediate value in the index field that will be used 67 * directly by qpu_load_imm(). 68 */ 69 QFILE_LOAD_IMM, 70 71 /** 72 * Stores an immediate value in the index field that can be turned 73 * into a small immediate field by qpu_encode_small_immediate(). 74 */ 75 QFILE_SMALL_IMM, 76}; 77 78struct qreg { 79 enum qfile file; 80 uint32_t index; 81 int pack; 82}; 83 84static inline struct qreg qir_reg(enum qfile file, uint32_t index) 85{ 86 return (struct qreg){file, index}; 87} 88 89enum qop { 90 QOP_UNDEF, 91 QOP_MOV, 92 QOP_FMOV, 93 QOP_MMOV, 94 QOP_FADD, 95 QOP_FSUB, 96 QOP_FMUL, 97 QOP_V8MULD, 98 QOP_V8MIN, 99 QOP_V8MAX, 100 QOP_V8ADDS, 101 QOP_V8SUBS, 102 QOP_MUL24, 103 QOP_FMIN, 104 QOP_FMAX, 105 QOP_FMINABS, 106 QOP_FMAXABS, 107 QOP_ADD, 108 QOP_SUB, 109 QOP_SHL, 110 QOP_SHR, 111 QOP_ASR, 112 QOP_MIN, 113 QOP_MAX, 114 QOP_AND, 115 QOP_OR, 116 QOP_XOR, 117 QOP_NOT, 118 119 QOP_FTOI, 120 QOP_ITOF, 121 QOP_RCP, 122 QOP_RSQ, 123 QOP_EXP2, 124 QOP_LOG2, 125 QOP_VW_SETUP, 126 QOP_VR_SETUP, 127 QOP_TLB_COLOR_READ, 128 QOP_MS_MASK, 129 QOP_VARY_ADD_C, 130 131 QOP_FRAG_Z, 132 QOP_FRAG_W, 133 134 /** Texture x coordinate parameter write */ 135 QOP_TEX_S, 136 /** Texture y coordinate parameter write */ 137 QOP_TEX_T, 138 /** Texture border color parameter or cube map z coordinate write */ 139 QOP_TEX_R, 140 /** Texture LOD bias parameter write */ 141 QOP_TEX_B, 142 143 /** 144 * Texture-unit 4-byte read with address provided direct in S 145 * cooordinate. 146 * 147 * The first operand is the offset from the start of the UBO, and the 148 * second is the uniform that has the UBO's base pointer. 149 */ 150 QOP_TEX_DIRECT, 151 152 /** 153 * Signal of texture read being necessary and then reading r4 into 154 * the destination 155 */ 156 QOP_TEX_RESULT, 157 158 QOP_LOAD_IMM, 159 160 /* Jumps to block->successor[0] if the qinst->cond (as a 161 * QPU_COND_BRANCH_*) passes, or block->successor[1] if not. Note 162 * that block->successor[1] may be unset if the condition is ALWAYS. 163 */ 164 QOP_BRANCH, 165 166 /* Emits an ADD from src[0] to src[1], where src[0] must be a 167 * QOP_LOAD_IMM result and src[1] is a QUNIFORM_UNIFORMS_ADDRESS, 168 * required by the kernel as part of its branch validation. 169 */ 170 QOP_UNIFORMS_RESET, 171}; 172 173struct queued_qpu_inst { 174 struct list_head link; 175 uint64_t inst; 176}; 177 178struct qinst { 179 struct list_head link; 180 181 enum qop op; 182 struct qreg dst; 183 struct qreg *src; 184 bool sf; 185 uint8_t cond; 186}; 187 188enum qstage { 189 /** 190 * Coordinate shader, runs during binning, before the VS, and just 191 * outputs position. 192 */ 193 QSTAGE_COORD, 194 QSTAGE_VERT, 195 QSTAGE_FRAG, 196}; 197 198enum quniform_contents { 199 /** 200 * Indicates that a constant 32-bit value is copied from the program's 201 * uniform contents. 202 */ 203 QUNIFORM_CONSTANT, 204 /** 205 * Indicates that the program's uniform contents are used as an index 206 * into the GL uniform storage. 207 */ 208 QUNIFORM_UNIFORM, 209 210 /** @{ 211 * Scaling factors from clip coordinates to relative to the viewport 212 * center. 213 * 214 * This is used by the coordinate and vertex shaders to produce the 215 * 32-bit entry consisting of 2 16-bit fields with 12.4 signed fixed 216 * point offsets from the viewport ccenter. 217 */ 218 QUNIFORM_VIEWPORT_X_SCALE, 219 QUNIFORM_VIEWPORT_Y_SCALE, 220 /** @} */ 221 222 QUNIFORM_VIEWPORT_Z_OFFSET, 223 QUNIFORM_VIEWPORT_Z_SCALE, 224 225 QUNIFORM_USER_CLIP_PLANE, 226 227 /** 228 * A reference to a texture config parameter 0 uniform. 229 * 230 * This is a uniform implicitly loaded with a QPU_W_TMU* write, which 231 * defines texture type, miplevels, and such. It will be found as a 232 * parameter to the first QOP_TEX_[STRB] instruction in a sequence. 233 */ 234 QUNIFORM_TEXTURE_CONFIG_P0, 235 236 /** 237 * A reference to a texture config parameter 1 uniform. 238 * 239 * This is a uniform implicitly loaded with a QPU_W_TMU* write, which 240 * defines texture width, height, filters, and wrap modes. It will be 241 * found as a parameter to the second QOP_TEX_[STRB] instruction in a 242 * sequence. 243 */ 244 QUNIFORM_TEXTURE_CONFIG_P1, 245 246 /** A reference to a texture config parameter 2 cubemap stride uniform */ 247 QUNIFORM_TEXTURE_CONFIG_P2, 248 249 QUNIFORM_TEXTURE_MSAA_ADDR, 250 251 QUNIFORM_UBO_ADDR, 252 253 QUNIFORM_TEXRECT_SCALE_X, 254 QUNIFORM_TEXRECT_SCALE_Y, 255 256 QUNIFORM_TEXTURE_BORDER_COLOR, 257 258 QUNIFORM_BLEND_CONST_COLOR_X, 259 QUNIFORM_BLEND_CONST_COLOR_Y, 260 QUNIFORM_BLEND_CONST_COLOR_Z, 261 QUNIFORM_BLEND_CONST_COLOR_W, 262 QUNIFORM_BLEND_CONST_COLOR_RGBA, 263 QUNIFORM_BLEND_CONST_COLOR_AAAA, 264 265 QUNIFORM_STENCIL, 266 267 QUNIFORM_ALPHA_REF, 268 QUNIFORM_SAMPLE_MASK, 269 270 /* Placeholder uniform that will be updated by the kernel when used by 271 * an instruction writing to QPU_W_UNIFORMS_ADDRESS. 272 */ 273 QUNIFORM_UNIFORMS_ADDRESS, 274}; 275 276struct vc4_varying_slot { 277 uint8_t slot; 278 uint8_t swizzle; 279}; 280 281struct vc4_compiler_ubo_range { 282 /** 283 * offset in bytes from the start of the ubo where this range is 284 * uploaded. 285 * 286 * Only set once used is set. 287 */ 288 uint32_t dst_offset; 289 290 /** 291 * offset in bytes from the start of the gallium uniforms where the 292 * data comes from. 293 */ 294 uint32_t src_offset; 295 296 /** size in bytes of this ubo range */ 297 uint32_t size; 298 299 /** 300 * Set if this range is used by the shader for indirect uniforms 301 * access. 302 */ 303 bool used; 304}; 305 306struct vc4_key { 307 struct vc4_uncompiled_shader *shader_state; 308 struct { 309 enum pipe_format format; 310 uint8_t swizzle[4]; 311 union { 312 struct { 313 unsigned compare_mode:1; 314 unsigned compare_func:3; 315 unsigned wrap_s:3; 316 unsigned wrap_t:3; 317 unsigned forced_first_level:8; 318 }; 319 struct { 320 uint16_t msaa_width, msaa_height; 321 }; 322 }; 323 } tex[VC4_MAX_TEXTURE_SAMPLERS]; 324 uint8_t ucp_enables; 325}; 326 327struct vc4_fs_key { 328 struct vc4_key base; 329 enum pipe_format color_format; 330 bool depth_enabled; 331 bool stencil_enabled; 332 bool stencil_twoside; 333 bool stencil_full_writemasks; 334 bool is_points; 335 bool is_lines; 336 bool alpha_test; 337 bool point_coord_upper_left; 338 bool light_twoside; 339 bool msaa; 340 bool sample_coverage; 341 bool sample_alpha_to_coverage; 342 bool sample_alpha_to_one; 343 uint8_t alpha_test_func; 344 uint8_t logicop_func; 345 uint32_t point_sprite_mask; 346 347 struct pipe_rt_blend_state blend; 348}; 349 350struct vc4_vs_key { 351 struct vc4_key base; 352 353 /** 354 * This is a proxy for the array of FS input semantics, which is 355 * larger than we would want to put in the key. 356 */ 357 uint64_t compiled_fs_id; 358 359 enum pipe_format attr_formats[8]; 360 bool is_coord; 361 bool per_vertex_point_size; 362 bool clamp_color; 363}; 364 365/** A basic block of QIR intructions. */ 366struct qblock { 367 struct list_head link; 368 369 struct list_head instructions; 370 struct list_head qpu_inst_list; 371 372 struct set *predecessors; 373 struct qblock *successors[2]; 374 375 int index; 376 377 /* Instruction IPs for the first and last instruction of the block. 378 * Set by vc4_qpu_schedule.c. 379 */ 380 uint32_t start_qpu_ip; 381 uint32_t end_qpu_ip; 382 383 /* Instruction IP for the branch instruction of the block. Set by 384 * vc4_qpu_schedule.c. 385 */ 386 uint32_t branch_qpu_ip; 387 388 /** @{ used by vc4_qir_live_variables.c */ 389 BITSET_WORD *def; 390 BITSET_WORD *use; 391 BITSET_WORD *live_in; 392 BITSET_WORD *live_out; 393 int start_ip, end_ip; 394 /** @} */ 395}; 396 397struct vc4_compile { 398 struct vc4_context *vc4; 399 nir_shader *s; 400 nir_function_impl *impl; 401 struct exec_list *cf_node_list; 402 403 /** 404 * Mapping from nir_register * or nir_ssa_def * to array of struct 405 * qreg for the values. 406 */ 407 struct hash_table *def_ht; 408 409 /* For each temp, the instruction generating its value. */ 410 struct qinst **defs; 411 uint32_t defs_array_size; 412 413 /** 414 * Inputs to the shader, arranged by TGSI declaration order. 415 * 416 * Not all fragment shader QFILE_VARY reads are present in this array. 417 */ 418 struct qreg *inputs; 419 struct qreg *outputs; 420 bool msaa_per_sample_output; 421 struct qreg color_reads[VC4_MAX_SAMPLES]; 422 struct qreg sample_colors[VC4_MAX_SAMPLES]; 423 uint32_t inputs_array_size; 424 uint32_t outputs_array_size; 425 uint32_t uniforms_array_size; 426 427 struct vc4_compiler_ubo_range *ubo_ranges; 428 uint32_t ubo_ranges_array_size; 429 /** Number of uniform areas declared in ubo_ranges. */ 430 uint32_t num_uniform_ranges; 431 /** Number of uniform areas used for indirect addressed loads. */ 432 uint32_t num_ubo_ranges; 433 uint32_t next_ubo_dst_offset; 434 435 /* State for whether we're executing on each channel currently. 0 if 436 * yes, otherwise a block number + 1 that the channel jumped to. 437 */ 438 struct qreg execute; 439 440 struct qreg line_x, point_x, point_y; 441 struct qreg discard; 442 struct qreg payload_FRAG_Z; 443 struct qreg payload_FRAG_W; 444 445 uint8_t vattr_sizes[8]; 446 447 /** 448 * Array of the VARYING_SLOT_* of all FS QFILE_VARY reads. 449 * 450 * This includes those that aren't part of the VPM varyings, like 451 * point/line coordinates. 452 */ 453 struct vc4_varying_slot *input_slots; 454 uint32_t num_input_slots; 455 uint32_t input_slots_array_size; 456 457 /** 458 * An entry per outputs[] in the VS indicating what the VARYING_SLOT_* 459 * of the output is. Used to emit from the VS in the order that the 460 * FS needs. 461 */ 462 struct vc4_varying_slot *output_slots; 463 464 struct pipe_shader_state *shader_state; 465 struct vc4_key *key; 466 struct vc4_fs_key *fs_key; 467 struct vc4_vs_key *vs_key; 468 469 /* Live ranges of temps. */ 470 int *temp_start, *temp_end; 471 472 uint32_t *uniform_data; 473 enum quniform_contents *uniform_contents; 474 uint32_t uniform_array_size; 475 uint32_t num_uniforms; 476 uint32_t num_outputs; 477 uint32_t num_texture_samples; 478 uint32_t output_position_index; 479 uint32_t output_color_index; 480 uint32_t output_point_size_index; 481 uint32_t output_sample_mask_index; 482 483 struct qreg undef; 484 enum qstage stage; 485 uint32_t num_temps; 486 487 struct list_head blocks; 488 int next_block_index; 489 struct qblock *cur_block; 490 struct qblock *loop_cont_block; 491 struct qblock *loop_break_block; 492 493 struct list_head qpu_inst_list; 494 495 uint64_t *qpu_insts; 496 uint32_t qpu_inst_count; 497 uint32_t qpu_inst_size; 498 uint32_t num_inputs; 499 500 uint32_t program_id; 501 uint32_t variant_id; 502}; 503 504/* Special nir_load_input intrinsic index for loading the current TLB 505 * destination color. 506 */ 507#define VC4_NIR_TLB_COLOR_READ_INPUT 2000000000 508 509#define VC4_NIR_MS_MASK_OUTPUT 2000000000 510 511/* Special offset for nir_load_uniform values to get a QUNIFORM_* 512 * state-dependent value. 513 */ 514#define VC4_NIR_STATE_UNIFORM_OFFSET 1000000000 515 516struct vc4_compile *qir_compile_init(void); 517void qir_compile_destroy(struct vc4_compile *c); 518struct qblock *qir_new_block(struct vc4_compile *c); 519void qir_set_emit_block(struct vc4_compile *c, struct qblock *block); 520void qir_link_blocks(struct qblock *predecessor, struct qblock *successor); 521struct qblock *qir_entry_block(struct vc4_compile *c); 522struct qblock *qir_exit_block(struct vc4_compile *c); 523struct qinst *qir_inst(enum qop op, struct qreg dst, 524 struct qreg src0, struct qreg src1); 525struct qinst *qir_inst4(enum qop op, struct qreg dst, 526 struct qreg a, 527 struct qreg b, 528 struct qreg c, 529 struct qreg d); 530void qir_remove_instruction(struct vc4_compile *c, struct qinst *qinst); 531struct qreg qir_uniform(struct vc4_compile *c, 532 enum quniform_contents contents, 533 uint32_t data); 534void qir_schedule_instructions(struct vc4_compile *c); 535void qir_reorder_uniforms(struct vc4_compile *c); 536void qir_emit_uniform_stream_resets(struct vc4_compile *c); 537 538struct qreg qir_emit_def(struct vc4_compile *c, struct qinst *inst); 539struct qinst *qir_emit_nondef(struct vc4_compile *c, struct qinst *inst); 540 541struct qreg qir_get_temp(struct vc4_compile *c); 542void qir_calculate_live_intervals(struct vc4_compile *c); 543int qir_get_op_nsrc(enum qop qop); 544bool qir_reg_equals(struct qreg a, struct qreg b); 545bool qir_has_side_effects(struct vc4_compile *c, struct qinst *inst); 546bool qir_has_side_effect_reads(struct vc4_compile *c, struct qinst *inst); 547bool qir_is_mul(struct qinst *inst); 548bool qir_is_raw_mov(struct qinst *inst); 549bool qir_is_tex(struct qinst *inst); 550bool qir_is_float_input(struct qinst *inst); 551bool qir_depends_on_flags(struct qinst *inst); 552bool qir_writes_r4(struct qinst *inst); 553struct qreg qir_follow_movs(struct vc4_compile *c, struct qreg reg); 554uint8_t qir_channels_written(struct qinst *inst); 555 556void qir_dump(struct vc4_compile *c); 557void qir_dump_inst(struct vc4_compile *c, struct qinst *inst); 558const char *qir_get_stage_name(enum qstage stage); 559 560void qir_validate(struct vc4_compile *c); 561 562void qir_optimize(struct vc4_compile *c); 563bool qir_opt_algebraic(struct vc4_compile *c); 564bool qir_opt_constant_folding(struct vc4_compile *c); 565bool qir_opt_copy_propagation(struct vc4_compile *c); 566bool qir_opt_dead_code(struct vc4_compile *c); 567bool qir_opt_peephole_sf(struct vc4_compile *c); 568bool qir_opt_small_immediates(struct vc4_compile *c); 569bool qir_opt_vpm(struct vc4_compile *c); 570void vc4_nir_lower_blend(nir_shader *s, struct vc4_compile *c); 571void vc4_nir_lower_io(nir_shader *s, struct vc4_compile *c); 572nir_ssa_def *vc4_nir_get_state_uniform(struct nir_builder *b, 573 enum quniform_contents contents); 574nir_ssa_def *vc4_nir_get_swizzled_channel(struct nir_builder *b, 575 nir_ssa_def **srcs, int swiz); 576void vc4_nir_lower_txf_ms(nir_shader *s, struct vc4_compile *c); 577void qir_lower_uniforms(struct vc4_compile *c); 578 579uint32_t qpu_schedule_instructions(struct vc4_compile *c); 580 581void qir_SF(struct vc4_compile *c, struct qreg src); 582 583static inline struct qreg 584qir_uniform_ui(struct vc4_compile *c, uint32_t ui) 585{ 586 return qir_uniform(c, QUNIFORM_CONSTANT, ui); 587} 588 589static inline struct qreg 590qir_uniform_f(struct vc4_compile *c, float f) 591{ 592 return qir_uniform(c, QUNIFORM_CONSTANT, fui(f)); 593} 594 595#define QIR_ALU0(name) \ 596static inline struct qreg \ 597qir_##name(struct vc4_compile *c) \ 598{ \ 599 return qir_emit_def(c, qir_inst(QOP_##name, c->undef, \ 600 c->undef, c->undef)); \ 601} \ 602static inline struct qinst * \ 603qir_##name##_dest(struct vc4_compile *c, struct qreg dest) \ 604{ \ 605 return qir_emit_nondef(c, qir_inst(QOP_##name, dest, \ 606 c->undef, c->undef)); \ 607} 608 609#define QIR_ALU1(name) \ 610static inline struct qreg \ 611qir_##name(struct vc4_compile *c, struct qreg a) \ 612{ \ 613 return qir_emit_def(c, qir_inst(QOP_##name, c->undef, \ 614 a, c->undef)); \ 615} \ 616static inline struct qinst * \ 617qir_##name##_dest(struct vc4_compile *c, struct qreg dest, \ 618 struct qreg a) \ 619{ \ 620 return qir_emit_nondef(c, qir_inst(QOP_##name, dest, a, \ 621 c->undef)); \ 622} 623 624#define QIR_ALU2(name) \ 625static inline struct qreg \ 626qir_##name(struct vc4_compile *c, struct qreg a, struct qreg b) \ 627{ \ 628 return qir_emit_def(c, qir_inst(QOP_##name, c->undef, a, b)); \ 629} \ 630static inline struct qinst * \ 631qir_##name##_dest(struct vc4_compile *c, struct qreg dest, \ 632 struct qreg a, struct qreg b) \ 633{ \ 634 return qir_emit_nondef(c, qir_inst(QOP_##name, dest, a, b)); \ 635} 636 637#define QIR_NODST_1(name) \ 638static inline struct qinst * \ 639qir_##name(struct vc4_compile *c, struct qreg a) \ 640{ \ 641 return qir_emit_nondef(c, qir_inst(QOP_##name, c->undef, \ 642 a, c->undef)); \ 643} 644 645#define QIR_NODST_2(name) \ 646static inline struct qinst * \ 647qir_##name(struct vc4_compile *c, struct qreg a, struct qreg b) \ 648{ \ 649 return qir_emit_nondef(c, qir_inst(QOP_##name, c->undef, \ 650 a, b)); \ 651} 652 653#define QIR_PAYLOAD(name) \ 654static inline struct qreg \ 655qir_##name(struct vc4_compile *c) \ 656{ \ 657 struct qreg *payload = &c->payload_##name; \ 658 if (payload->file != QFILE_NULL) \ 659 return *payload; \ 660 *payload = qir_get_temp(c); \ 661 struct qinst *inst = qir_inst(QOP_##name, *payload, \ 662 c->undef, c->undef); \ 663 struct qblock *entry = qir_entry_block(c); \ 664 list_add(&inst->link, &entry->instructions); \ 665 c->defs[payload->index] = inst; \ 666 return *payload; \ 667} 668 669QIR_ALU1(MOV) 670QIR_ALU1(FMOV) 671QIR_ALU1(MMOV) 672QIR_ALU2(FADD) 673QIR_ALU2(FSUB) 674QIR_ALU2(FMUL) 675QIR_ALU2(V8MULD) 676QIR_ALU2(V8MIN) 677QIR_ALU2(V8MAX) 678QIR_ALU2(V8ADDS) 679QIR_ALU2(V8SUBS) 680QIR_ALU2(MUL24) 681QIR_ALU2(FMIN) 682QIR_ALU2(FMAX) 683QIR_ALU2(FMINABS) 684QIR_ALU2(FMAXABS) 685QIR_ALU1(FTOI) 686QIR_ALU1(ITOF) 687 688QIR_ALU2(ADD) 689QIR_ALU2(SUB) 690QIR_ALU2(SHL) 691QIR_ALU2(SHR) 692QIR_ALU2(ASR) 693QIR_ALU2(MIN) 694QIR_ALU2(MAX) 695QIR_ALU2(AND) 696QIR_ALU2(OR) 697QIR_ALU2(XOR) 698QIR_ALU1(NOT) 699 700QIR_ALU1(RCP) 701QIR_ALU1(RSQ) 702QIR_ALU1(EXP2) 703QIR_ALU1(LOG2) 704QIR_ALU1(VARY_ADD_C) 705QIR_NODST_2(TEX_S) 706QIR_NODST_2(TEX_T) 707QIR_NODST_2(TEX_R) 708QIR_NODST_2(TEX_B) 709QIR_NODST_2(TEX_DIRECT) 710QIR_PAYLOAD(FRAG_Z) 711QIR_PAYLOAD(FRAG_W) 712QIR_ALU0(TEX_RESULT) 713QIR_ALU0(TLB_COLOR_READ) 714QIR_NODST_1(MS_MASK) 715 716static inline struct qreg 717qir_SEL(struct vc4_compile *c, uint8_t cond, struct qreg src0, struct qreg src1) 718{ 719 struct qreg t = qir_get_temp(c); 720 struct qinst *a = qir_MOV_dest(c, t, src0); 721 struct qinst *b = qir_MOV_dest(c, t, src1); 722 a->cond = cond; 723 b->cond = qpu_cond_complement(cond); 724 return t; 725} 726 727static inline struct qreg 728qir_UNPACK_8_F(struct vc4_compile *c, struct qreg src, int i) 729{ 730 struct qreg t = qir_FMOV(c, src); 731 c->defs[t.index]->src[0].pack = QPU_UNPACK_8A + i; 732 return t; 733} 734 735static inline struct qreg 736qir_UNPACK_8_I(struct vc4_compile *c, struct qreg src, int i) 737{ 738 struct qreg t = qir_MOV(c, src); 739 c->defs[t.index]->src[0].pack = QPU_UNPACK_8A + i; 740 return t; 741} 742 743static inline struct qreg 744qir_UNPACK_16_F(struct vc4_compile *c, struct qreg src, int i) 745{ 746 struct qreg t = qir_FMOV(c, src); 747 c->defs[t.index]->src[0].pack = QPU_UNPACK_16A + i; 748 return t; 749} 750 751static inline struct qreg 752qir_UNPACK_16_I(struct vc4_compile *c, struct qreg src, int i) 753{ 754 struct qreg t = qir_MOV(c, src); 755 c->defs[t.index]->src[0].pack = QPU_UNPACK_16A + i; 756 return t; 757} 758 759static inline void 760qir_PACK_8_F(struct vc4_compile *c, struct qreg dest, struct qreg val, int chan) 761{ 762 assert(!dest.pack); 763 dest.pack = QPU_PACK_MUL_8A + chan; 764 qir_emit_nondef(c, qir_inst(QOP_MMOV, dest, val, c->undef)); 765} 766 767static inline struct qreg 768qir_PACK_8888_F(struct vc4_compile *c, struct qreg val) 769{ 770 struct qreg dest = qir_MMOV(c, val); 771 c->defs[dest.index]->dst.pack = QPU_PACK_MUL_8888; 772 return dest; 773} 774 775static inline struct qreg 776qir_POW(struct vc4_compile *c, struct qreg x, struct qreg y) 777{ 778 return qir_EXP2(c, qir_FMUL(c, 779 y, 780 qir_LOG2(c, x))); 781} 782 783static inline void 784qir_VPM_WRITE(struct vc4_compile *c, struct qreg val) 785{ 786 qir_MOV_dest(c, qir_reg(QFILE_VPM, 0), val); 787} 788 789static inline struct qreg 790qir_LOAD_IMM(struct vc4_compile *c, uint32_t val) 791{ 792 return qir_emit_def(c, qir_inst(QOP_LOAD_IMM, c->undef, 793 qir_reg(QFILE_LOAD_IMM, val), c->undef)); 794} 795 796static inline void 797qir_MOV_cond(struct vc4_compile *c, uint8_t cond, 798 struct qreg dest, struct qreg src) 799{ 800 qir_MOV_dest(c, dest, src)->cond = cond; 801} 802 803static inline struct qinst * 804qir_BRANCH(struct vc4_compile *c, uint8_t cond) 805{ 806 struct qinst *inst = qir_inst(QOP_BRANCH, c->undef, c->undef, c->undef); 807 inst->cond = cond; 808 qir_emit_nondef(c, inst); 809 return inst; 810} 811 812#define qir_for_each_block(block, c) \ 813 list_for_each_entry(struct qblock, block, &c->blocks, link) 814 815#define qir_for_each_block_rev(block, c) \ 816 list_for_each_entry_rev(struct qblock, block, &c->blocks, link) 817 818/* Loop over the non-NULL members of the successors array. */ 819#define qir_for_each_successor(succ, block) \ 820 for (struct qblock *succ = block->successors[0]; \ 821 succ != NULL; \ 822 succ = (succ == block->successors[1] ? NULL : \ 823 block->successors[1])) 824 825#define qir_for_each_inst(inst, block) \ 826 list_for_each_entry(struct qinst, inst, &block->instructions, link) 827 828#define qir_for_each_inst_rev(inst, block) \ 829 list_for_each_entry_rev(struct qinst, inst, &block->instructions, link) 830 831#define qir_for_each_inst_safe(inst, block) \ 832 list_for_each_entry_safe(struct qinst, inst, &block->instructions, link) 833 834#define qir_for_each_inst_inorder(inst, c) \ 835 qir_for_each_block(_block, c) \ 836 qir_for_each_inst(inst, _block) 837 838#endif /* VC4_QIR_H */ 839