vc4_qir.h revision 6c1f834a237540c344fa794d60501a69bf066fb5
1/* 2 * Copyright © 2014 Broadcom 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24#ifndef VC4_QIR_H 25#define VC4_QIR_H 26 27#include <assert.h> 28#include <stdio.h> 29#include <stdlib.h> 30#include <stdbool.h> 31#include <stdint.h> 32#include <string.h> 33 34#include "util/macros.h" 35#include "compiler/nir/nir.h" 36#include "util/list.h" 37#include "util/u_math.h" 38 39#include "vc4_screen.h" 40#include "vc4_qpu_defines.h" 41#include "kernel/vc4_packet.h" 42#include "pipe/p_state.h" 43 44struct nir_builder; 45 46enum qfile { 47 QFILE_NULL, 48 QFILE_TEMP, 49 QFILE_VARY, 50 QFILE_UNIF, 51 QFILE_VPM, 52 QFILE_TLB_COLOR_WRITE, 53 QFILE_TLB_COLOR_WRITE_MS, 54 QFILE_TLB_Z_WRITE, 55 QFILE_TLB_STENCIL_SETUP, 56 57 /* Payload registers that aren't in the physical register file, so we 58 * can just use the corresponding qpu_reg at qpu_emit time. 59 */ 60 QFILE_FRAG_X, 61 QFILE_FRAG_Y, 62 QFILE_FRAG_REV_FLAG, 63 64 /** 65 * Stores an immediate value in the index field that will be used 66 * directly by qpu_load_imm(). 67 */ 68 QFILE_LOAD_IMM, 69 70 /** 71 * Stores an immediate value in the index field that can be turned 72 * into a small immediate field by qpu_encode_small_immediate(). 73 */ 74 QFILE_SMALL_IMM, 75}; 76 77struct qreg { 78 enum qfile file; 79 uint32_t index; 80 int pack; 81}; 82 83static inline struct qreg qir_reg(enum qfile file, uint32_t index) 84{ 85 return (struct qreg){file, index}; 86} 87 88enum qop { 89 QOP_UNDEF, 90 QOP_MOV, 91 QOP_FMOV, 92 QOP_MMOV, 93 QOP_FADD, 94 QOP_FSUB, 95 QOP_FMUL, 96 QOP_V8MULD, 97 QOP_V8MIN, 98 QOP_V8MAX, 99 QOP_V8ADDS, 100 QOP_V8SUBS, 101 QOP_MUL24, 102 QOP_FMIN, 103 QOP_FMAX, 104 QOP_FMINABS, 105 QOP_FMAXABS, 106 QOP_ADD, 107 QOP_SUB, 108 QOP_SHL, 109 QOP_SHR, 110 QOP_ASR, 111 QOP_MIN, 112 QOP_MAX, 113 QOP_AND, 114 QOP_OR, 115 QOP_XOR, 116 QOP_NOT, 117 118 QOP_FTOI, 119 QOP_ITOF, 120 QOP_RCP, 121 QOP_RSQ, 122 QOP_EXP2, 123 QOP_LOG2, 124 QOP_VW_SETUP, 125 QOP_VR_SETUP, 126 QOP_TLB_COLOR_READ, 127 QOP_MS_MASK, 128 QOP_VARY_ADD_C, 129 130 QOP_FRAG_Z, 131 QOP_FRAG_W, 132 133 /** Texture x coordinate parameter write */ 134 QOP_TEX_S, 135 /** Texture y coordinate parameter write */ 136 QOP_TEX_T, 137 /** Texture border color parameter or cube map z coordinate write */ 138 QOP_TEX_R, 139 /** Texture LOD bias parameter write */ 140 QOP_TEX_B, 141 142 /** 143 * Texture-unit 4-byte read with address provided direct in S 144 * cooordinate. 145 * 146 * The first operand is the offset from the start of the UBO, and the 147 * second is the uniform that has the UBO's base pointer. 148 */ 149 QOP_TEX_DIRECT, 150 151 /** 152 * Signal of texture read being necessary and then reading r4 into 153 * the destination 154 */ 155 QOP_TEX_RESULT, 156 157 QOP_LOAD_IMM, 158}; 159 160struct queued_qpu_inst { 161 struct list_head link; 162 uint64_t inst; 163}; 164 165struct qinst { 166 struct list_head link; 167 168 enum qop op; 169 struct qreg dst; 170 struct qreg *src; 171 bool sf; 172 uint8_t cond; 173}; 174 175enum qstage { 176 /** 177 * Coordinate shader, runs during binning, before the VS, and just 178 * outputs position. 179 */ 180 QSTAGE_COORD, 181 QSTAGE_VERT, 182 QSTAGE_FRAG, 183}; 184 185enum quniform_contents { 186 /** 187 * Indicates that a constant 32-bit value is copied from the program's 188 * uniform contents. 189 */ 190 QUNIFORM_CONSTANT, 191 /** 192 * Indicates that the program's uniform contents are used as an index 193 * into the GL uniform storage. 194 */ 195 QUNIFORM_UNIFORM, 196 197 /** @{ 198 * Scaling factors from clip coordinates to relative to the viewport 199 * center. 200 * 201 * This is used by the coordinate and vertex shaders to produce the 202 * 32-bit entry consisting of 2 16-bit fields with 12.4 signed fixed 203 * point offsets from the viewport ccenter. 204 */ 205 QUNIFORM_VIEWPORT_X_SCALE, 206 QUNIFORM_VIEWPORT_Y_SCALE, 207 /** @} */ 208 209 QUNIFORM_VIEWPORT_Z_OFFSET, 210 QUNIFORM_VIEWPORT_Z_SCALE, 211 212 QUNIFORM_USER_CLIP_PLANE, 213 214 /** 215 * A reference to a texture config parameter 0 uniform. 216 * 217 * This is a uniform implicitly loaded with a QPU_W_TMU* write, which 218 * defines texture type, miplevels, and such. It will be found as a 219 * parameter to the first QOP_TEX_[STRB] instruction in a sequence. 220 */ 221 QUNIFORM_TEXTURE_CONFIG_P0, 222 223 /** 224 * A reference to a texture config parameter 1 uniform. 225 * 226 * This is a uniform implicitly loaded with a QPU_W_TMU* write, which 227 * defines texture width, height, filters, and wrap modes. It will be 228 * found as a parameter to the second QOP_TEX_[STRB] instruction in a 229 * sequence. 230 */ 231 QUNIFORM_TEXTURE_CONFIG_P1, 232 233 /** A reference to a texture config parameter 2 cubemap stride uniform */ 234 QUNIFORM_TEXTURE_CONFIG_P2, 235 236 QUNIFORM_TEXTURE_MSAA_ADDR, 237 238 QUNIFORM_UBO_ADDR, 239 240 QUNIFORM_TEXRECT_SCALE_X, 241 QUNIFORM_TEXRECT_SCALE_Y, 242 243 QUNIFORM_TEXTURE_BORDER_COLOR, 244 245 QUNIFORM_BLEND_CONST_COLOR_X, 246 QUNIFORM_BLEND_CONST_COLOR_Y, 247 QUNIFORM_BLEND_CONST_COLOR_Z, 248 QUNIFORM_BLEND_CONST_COLOR_W, 249 QUNIFORM_BLEND_CONST_COLOR_RGBA, 250 QUNIFORM_BLEND_CONST_COLOR_AAAA, 251 252 QUNIFORM_STENCIL, 253 254 QUNIFORM_ALPHA_REF, 255 QUNIFORM_SAMPLE_MASK, 256}; 257 258struct vc4_varying_slot { 259 uint8_t slot; 260 uint8_t swizzle; 261}; 262 263struct vc4_compiler_ubo_range { 264 /** 265 * offset in bytes from the start of the ubo where this range is 266 * uploaded. 267 * 268 * Only set once used is set. 269 */ 270 uint32_t dst_offset; 271 272 /** 273 * offset in bytes from the start of the gallium uniforms where the 274 * data comes from. 275 */ 276 uint32_t src_offset; 277 278 /** size in bytes of this ubo range */ 279 uint32_t size; 280 281 /** 282 * Set if this range is used by the shader for indirect uniforms 283 * access. 284 */ 285 bool used; 286}; 287 288struct vc4_key { 289 struct vc4_uncompiled_shader *shader_state; 290 struct { 291 enum pipe_format format; 292 uint8_t swizzle[4]; 293 union { 294 struct { 295 unsigned compare_mode:1; 296 unsigned compare_func:3; 297 unsigned wrap_s:3; 298 unsigned wrap_t:3; 299 }; 300 struct { 301 uint16_t msaa_width, msaa_height; 302 }; 303 }; 304 } tex[VC4_MAX_TEXTURE_SAMPLERS]; 305 uint8_t ucp_enables; 306}; 307 308struct vc4_fs_key { 309 struct vc4_key base; 310 enum pipe_format color_format; 311 bool depth_enabled; 312 bool stencil_enabled; 313 bool stencil_twoside; 314 bool stencil_full_writemasks; 315 bool is_points; 316 bool is_lines; 317 bool alpha_test; 318 bool point_coord_upper_left; 319 bool light_twoside; 320 bool msaa; 321 bool sample_coverage; 322 bool sample_alpha_to_coverage; 323 bool sample_alpha_to_one; 324 uint8_t alpha_test_func; 325 uint8_t logicop_func; 326 uint32_t point_sprite_mask; 327 328 struct pipe_rt_blend_state blend; 329}; 330 331struct vc4_vs_key { 332 struct vc4_key base; 333 334 /** 335 * This is a proxy for the array of FS input semantics, which is 336 * larger than we would want to put in the key. 337 */ 338 uint64_t compiled_fs_id; 339 340 enum pipe_format attr_formats[8]; 341 bool is_coord; 342 bool per_vertex_point_size; 343 bool clamp_color; 344}; 345 346/** A basic block of QIR intructions. */ 347struct qblock { 348 struct list_head link; 349 350 struct list_head instructions; 351 352 struct set *predecessors; 353 struct qblock *successors[2]; 354 355 int index; 356}; 357 358struct vc4_compile { 359 struct vc4_context *vc4; 360 nir_shader *s; 361 nir_function_impl *impl; 362 struct exec_list *cf_node_list; 363 364 /** 365 * Mapping from nir_register * or nir_ssa_def * to array of struct 366 * qreg for the values. 367 */ 368 struct hash_table *def_ht; 369 370 /* For each temp, the instruction generating its value. */ 371 struct qinst **defs; 372 uint32_t defs_array_size; 373 374 /** 375 * Inputs to the shader, arranged by TGSI declaration order. 376 * 377 * Not all fragment shader QFILE_VARY reads are present in this array. 378 */ 379 struct qreg *inputs; 380 struct qreg *outputs; 381 bool msaa_per_sample_output; 382 struct qreg color_reads[VC4_MAX_SAMPLES]; 383 struct qreg sample_colors[VC4_MAX_SAMPLES]; 384 uint32_t inputs_array_size; 385 uint32_t outputs_array_size; 386 uint32_t uniforms_array_size; 387 388 struct vc4_compiler_ubo_range *ubo_ranges; 389 uint32_t ubo_ranges_array_size; 390 /** Number of uniform areas declared in ubo_ranges. */ 391 uint32_t num_uniform_ranges; 392 /** Number of uniform areas used for indirect addressed loads. */ 393 uint32_t num_ubo_ranges; 394 uint32_t next_ubo_dst_offset; 395 396 struct qreg line_x, point_x, point_y; 397 struct qreg discard; 398 struct qreg payload_FRAG_Z; 399 struct qreg payload_FRAG_W; 400 401 uint8_t vattr_sizes[8]; 402 403 /** 404 * Array of the VARYING_SLOT_* of all FS QFILE_VARY reads. 405 * 406 * This includes those that aren't part of the VPM varyings, like 407 * point/line coordinates. 408 */ 409 struct vc4_varying_slot *input_slots; 410 uint32_t num_input_slots; 411 uint32_t input_slots_array_size; 412 413 /** 414 * An entry per outputs[] in the VS indicating what the VARYING_SLOT_* 415 * of the output is. Used to emit from the VS in the order that the 416 * FS needs. 417 */ 418 struct vc4_varying_slot *output_slots; 419 420 struct pipe_shader_state *shader_state; 421 struct vc4_key *key; 422 struct vc4_fs_key *fs_key; 423 struct vc4_vs_key *vs_key; 424 425 uint32_t *uniform_data; 426 enum quniform_contents *uniform_contents; 427 uint32_t uniform_array_size; 428 uint32_t num_uniforms; 429 uint32_t num_outputs; 430 uint32_t num_texture_samples; 431 uint32_t output_position_index; 432 uint32_t output_color_index; 433 uint32_t output_point_size_index; 434 uint32_t output_sample_mask_index; 435 436 struct qreg undef; 437 enum qstage stage; 438 uint32_t num_temps; 439 440 struct list_head blocks; 441 int next_block_index; 442 struct qblock *cur_block; 443 444 struct list_head qpu_inst_list; 445 uint64_t *qpu_insts; 446 uint32_t qpu_inst_count; 447 uint32_t qpu_inst_size; 448 uint32_t num_inputs; 449 450 uint32_t program_id; 451 uint32_t variant_id; 452}; 453 454/* Special nir_load_input intrinsic index for loading the current TLB 455 * destination color. 456 */ 457#define VC4_NIR_TLB_COLOR_READ_INPUT 2000000000 458 459#define VC4_NIR_MS_MASK_OUTPUT 2000000000 460 461/* Special offset for nir_load_uniform values to get a QUNIFORM_* 462 * state-dependent value. 463 */ 464#define VC4_NIR_STATE_UNIFORM_OFFSET 1000000000 465 466struct vc4_compile *qir_compile_init(void); 467void qir_compile_destroy(struct vc4_compile *c); 468struct qblock *qir_new_block(struct vc4_compile *c); 469void qir_set_emit_block(struct vc4_compile *c, struct qblock *block); 470void qir_link_blocks(struct qblock *predecessor, struct qblock *successor); 471struct qblock *qir_entry_block(struct vc4_compile *c); 472struct qblock *qir_exit_block(struct vc4_compile *c); 473struct qinst *qir_inst(enum qop op, struct qreg dst, 474 struct qreg src0, struct qreg src1); 475struct qinst *qir_inst4(enum qop op, struct qreg dst, 476 struct qreg a, 477 struct qreg b, 478 struct qreg c, 479 struct qreg d); 480void qir_remove_instruction(struct vc4_compile *c, struct qinst *qinst); 481struct qreg qir_uniform(struct vc4_compile *c, 482 enum quniform_contents contents, 483 uint32_t data); 484void qir_schedule_instructions(struct vc4_compile *c); 485void qir_reorder_uniforms(struct vc4_compile *c); 486 487struct qreg qir_emit_def(struct vc4_compile *c, struct qinst *inst); 488struct qinst *qir_emit_nondef(struct vc4_compile *c, struct qinst *inst); 489 490struct qreg qir_get_temp(struct vc4_compile *c); 491int qir_get_op_nsrc(enum qop qop); 492bool qir_reg_equals(struct qreg a, struct qreg b); 493bool qir_has_side_effects(struct vc4_compile *c, struct qinst *inst); 494bool qir_has_side_effect_reads(struct vc4_compile *c, struct qinst *inst); 495bool qir_is_mul(struct qinst *inst); 496bool qir_is_raw_mov(struct qinst *inst); 497bool qir_is_tex(struct qinst *inst); 498bool qir_is_float_input(struct qinst *inst); 499bool qir_depends_on_flags(struct qinst *inst); 500bool qir_writes_r4(struct qinst *inst); 501struct qreg qir_follow_movs(struct vc4_compile *c, struct qreg reg); 502 503void qir_dump(struct vc4_compile *c); 504void qir_dump_inst(struct vc4_compile *c, struct qinst *inst); 505const char *qir_get_stage_name(enum qstage stage); 506 507void qir_validate(struct vc4_compile *c); 508 509void qir_optimize(struct vc4_compile *c); 510bool qir_opt_algebraic(struct vc4_compile *c); 511bool qir_opt_constant_folding(struct vc4_compile *c); 512bool qir_opt_copy_propagation(struct vc4_compile *c); 513bool qir_opt_dead_code(struct vc4_compile *c); 514bool qir_opt_peephole_sf(struct vc4_compile *c); 515bool qir_opt_small_immediates(struct vc4_compile *c); 516bool qir_opt_vpm(struct vc4_compile *c); 517void vc4_nir_lower_blend(nir_shader *s, struct vc4_compile *c); 518void vc4_nir_lower_io(nir_shader *s, struct vc4_compile *c); 519nir_ssa_def *vc4_nir_get_state_uniform(struct nir_builder *b, 520 enum quniform_contents contents); 521nir_ssa_def *vc4_nir_get_swizzled_channel(struct nir_builder *b, 522 nir_ssa_def **srcs, int swiz); 523void vc4_nir_lower_txf_ms(nir_shader *s, struct vc4_compile *c); 524void qir_lower_uniforms(struct vc4_compile *c); 525 526uint32_t qpu_schedule_instructions(struct vc4_compile *c); 527 528void qir_SF(struct vc4_compile *c, struct qreg src); 529 530static inline struct qreg 531qir_uniform_ui(struct vc4_compile *c, uint32_t ui) 532{ 533 return qir_uniform(c, QUNIFORM_CONSTANT, ui); 534} 535 536static inline struct qreg 537qir_uniform_f(struct vc4_compile *c, float f) 538{ 539 return qir_uniform(c, QUNIFORM_CONSTANT, fui(f)); 540} 541 542#define QIR_ALU0(name) \ 543static inline struct qreg \ 544qir_##name(struct vc4_compile *c) \ 545{ \ 546 return qir_emit_def(c, qir_inst(QOP_##name, c->undef, \ 547 c->undef, c->undef)); \ 548} \ 549static inline struct qinst * \ 550qir_##name##_dest(struct vc4_compile *c, struct qreg dest) \ 551{ \ 552 return qir_emit_nondef(c, qir_inst(QOP_##name, dest, \ 553 c->undef, c->undef)); \ 554} 555 556#define QIR_ALU1(name) \ 557static inline struct qreg \ 558qir_##name(struct vc4_compile *c, struct qreg a) \ 559{ \ 560 return qir_emit_def(c, qir_inst(QOP_##name, c->undef, \ 561 a, c->undef)); \ 562} \ 563static inline struct qinst * \ 564qir_##name##_dest(struct vc4_compile *c, struct qreg dest, \ 565 struct qreg a) \ 566{ \ 567 return qir_emit_nondef(c, qir_inst(QOP_##name, dest, a, \ 568 c->undef)); \ 569} 570 571#define QIR_ALU2(name) \ 572static inline struct qreg \ 573qir_##name(struct vc4_compile *c, struct qreg a, struct qreg b) \ 574{ \ 575 return qir_emit_def(c, qir_inst(QOP_##name, c->undef, a, b)); \ 576} \ 577static inline struct qinst * \ 578qir_##name##_dest(struct vc4_compile *c, struct qreg dest, \ 579 struct qreg a, struct qreg b) \ 580{ \ 581 return qir_emit_nondef(c, qir_inst(QOP_##name, dest, a, b)); \ 582} 583 584#define QIR_NODST_1(name) \ 585static inline struct qinst * \ 586qir_##name(struct vc4_compile *c, struct qreg a) \ 587{ \ 588 return qir_emit_nondef(c, qir_inst(QOP_##name, c->undef, \ 589 a, c->undef)); \ 590} 591 592#define QIR_NODST_2(name) \ 593static inline struct qinst * \ 594qir_##name(struct vc4_compile *c, struct qreg a, struct qreg b) \ 595{ \ 596 return qir_emit_nondef(c, qir_inst(QOP_##name, c->undef, \ 597 a, b)); \ 598} 599 600#define QIR_PAYLOAD(name) \ 601static inline struct qreg \ 602qir_##name(struct vc4_compile *c) \ 603{ \ 604 struct qreg *payload = &c->payload_##name; \ 605 if (payload->file != QFILE_NULL) \ 606 return *payload; \ 607 *payload = qir_get_temp(c); \ 608 struct qinst *inst = qir_inst(QOP_##name, *payload, \ 609 c->undef, c->undef); \ 610 struct qblock *entry = qir_entry_block(c); \ 611 list_add(&inst->link, &entry->instructions); \ 612 c->defs[payload->index] = inst; \ 613 return *payload; \ 614} 615 616QIR_ALU1(MOV) 617QIR_ALU1(FMOV) 618QIR_ALU1(MMOV) 619QIR_ALU2(FADD) 620QIR_ALU2(FSUB) 621QIR_ALU2(FMUL) 622QIR_ALU2(V8MULD) 623QIR_ALU2(V8MIN) 624QIR_ALU2(V8MAX) 625QIR_ALU2(V8ADDS) 626QIR_ALU2(V8SUBS) 627QIR_ALU2(MUL24) 628QIR_ALU2(FMIN) 629QIR_ALU2(FMAX) 630QIR_ALU2(FMINABS) 631QIR_ALU2(FMAXABS) 632QIR_ALU1(FTOI) 633QIR_ALU1(ITOF) 634 635QIR_ALU2(ADD) 636QIR_ALU2(SUB) 637QIR_ALU2(SHL) 638QIR_ALU2(SHR) 639QIR_ALU2(ASR) 640QIR_ALU2(MIN) 641QIR_ALU2(MAX) 642QIR_ALU2(AND) 643QIR_ALU2(OR) 644QIR_ALU2(XOR) 645QIR_ALU1(NOT) 646 647QIR_ALU1(RCP) 648QIR_ALU1(RSQ) 649QIR_ALU1(EXP2) 650QIR_ALU1(LOG2) 651QIR_ALU1(VARY_ADD_C) 652QIR_NODST_2(TEX_S) 653QIR_NODST_2(TEX_T) 654QIR_NODST_2(TEX_R) 655QIR_NODST_2(TEX_B) 656QIR_NODST_2(TEX_DIRECT) 657QIR_PAYLOAD(FRAG_Z) 658QIR_PAYLOAD(FRAG_W) 659QIR_ALU0(TEX_RESULT) 660QIR_ALU0(TLB_COLOR_READ) 661QIR_NODST_1(MS_MASK) 662 663static inline struct qreg 664qir_SEL(struct vc4_compile *c, uint8_t cond, struct qreg src0, struct qreg src1) 665{ 666 struct qreg t = qir_get_temp(c); 667 struct qinst *a = qir_MOV_dest(c, t, src0); 668 struct qinst *b = qir_MOV_dest(c, t, src1); 669 a->cond = cond; 670 b->cond = cond ^ 1; 671 return t; 672} 673 674static inline struct qreg 675qir_UNPACK_8_F(struct vc4_compile *c, struct qreg src, int i) 676{ 677 struct qreg t = qir_FMOV(c, src); 678 c->defs[t.index]->src[0].pack = QPU_UNPACK_8A + i; 679 return t; 680} 681 682static inline struct qreg 683qir_UNPACK_8_I(struct vc4_compile *c, struct qreg src, int i) 684{ 685 struct qreg t = qir_MOV(c, src); 686 c->defs[t.index]->src[0].pack = QPU_UNPACK_8A + i; 687 return t; 688} 689 690static inline struct qreg 691qir_UNPACK_16_F(struct vc4_compile *c, struct qreg src, int i) 692{ 693 struct qreg t = qir_FMOV(c, src); 694 c->defs[t.index]->src[0].pack = QPU_UNPACK_16A + i; 695 return t; 696} 697 698static inline struct qreg 699qir_UNPACK_16_I(struct vc4_compile *c, struct qreg src, int i) 700{ 701 struct qreg t = qir_MOV(c, src); 702 c->defs[t.index]->src[0].pack = QPU_UNPACK_16A + i; 703 return t; 704} 705 706static inline void 707qir_PACK_8_F(struct vc4_compile *c, struct qreg dest, struct qreg val, int chan) 708{ 709 assert(!dest.pack); 710 dest.pack = QPU_PACK_MUL_8A + chan; 711 qir_emit_nondef(c, qir_inst(QOP_MMOV, dest, val, c->undef)); 712} 713 714static inline struct qreg 715qir_PACK_8888_F(struct vc4_compile *c, struct qreg val) 716{ 717 struct qreg dest = qir_MMOV(c, val); 718 c->defs[dest.index]->dst.pack = QPU_PACK_MUL_8888; 719 return dest; 720} 721 722static inline struct qreg 723qir_POW(struct vc4_compile *c, struct qreg x, struct qreg y) 724{ 725 return qir_EXP2(c, qir_FMUL(c, 726 y, 727 qir_LOG2(c, x))); 728} 729 730static inline void 731qir_VPM_WRITE(struct vc4_compile *c, struct qreg val) 732{ 733 qir_MOV_dest(c, qir_reg(QFILE_VPM, 0), val); 734} 735 736static inline struct qreg 737qir_LOAD_IMM(struct vc4_compile *c, uint32_t val) 738{ 739 return qir_emit_def(c, qir_inst(QOP_LOAD_IMM, c->undef, 740 qir_reg(QFILE_LOAD_IMM, val), c->undef)); 741} 742 743#define qir_for_each_block(block, c) \ 744 list_for_each_entry(struct qblock, block, &c->blocks, link) 745 746#define qir_for_each_block_rev(block, c) \ 747 list_for_each_entry_rev(struct qblock, block, &c->blocks, link) 748 749/* Loop over the non-NULL members of the successors array. */ 750#define qir_for_each_successor(succ, block) \ 751 for (struct qblock *succ = block->successors[0]; \ 752 succ != NULL; \ 753 succ = (succ == block->successors[1] ? NULL : \ 754 block->successors[1])) 755 756#define qir_for_each_inst(inst, block) \ 757 list_for_each_entry(struct qinst, inst, &block->instructions, link) 758 759#define qir_for_each_inst_rev(inst, block) \ 760 list_for_each_entry_rev(struct qinst, inst, &block->instructions, link) 761 762#define qir_for_each_inst_safe(inst, block) \ 763 list_for_each_entry_safe(struct qinst, inst, &block->instructions, link) 764 765#define qir_for_each_inst_inorder(inst, c) \ 766 qir_for_each_block(_block, c) \ 767 qir_for_each_inst(inst, _block) 768 769#endif /* VC4_QIR_H */ 770