vc4_qir.h revision 74c4b3b80cc4246fd1eb503d97edb3d293eef5de
1/*
2 * Copyright © 2014 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24#ifndef VC4_QIR_H
25#define VC4_QIR_H
26
27#include <assert.h>
28#include <stdio.h>
29#include <stdlib.h>
30#include <stdbool.h>
31#include <stdint.h>
32#include <string.h>
33
34#include "util/macros.h"
35#include "glsl/nir/nir.h"
36#include "util/list.h"
37#include "util/u_math.h"
38
39#include "vc4_screen.h"
40#include "vc4_qpu_defines.h"
41#include "pipe/p_state.h"
42
43struct nir_builder;
44
45enum qfile {
46        QFILE_NULL,
47        QFILE_TEMP,
48        QFILE_VARY,
49        QFILE_UNIF,
50        QFILE_VPM,
51
52        /**
53         * Stores an immediate value in the index field that can be turned
54         * into a small immediate field by qpu_encode_small_immediate().
55         */
56        QFILE_SMALL_IMM,
57};
58
59struct qreg {
60        enum qfile file;
61        uint32_t index;
62        int pack;
63};
64
65enum qop {
66        QOP_UNDEF,
67        QOP_MOV,
68        QOP_FMOV,
69        QOP_MMOV,
70        QOP_FADD,
71        QOP_FSUB,
72        QOP_FMUL,
73        QOP_V8MULD,
74        QOP_V8MIN,
75        QOP_V8MAX,
76        QOP_V8ADDS,
77        QOP_V8SUBS,
78        QOP_MUL24,
79        QOP_FMIN,
80        QOP_FMAX,
81        QOP_FMINABS,
82        QOP_FMAXABS,
83        QOP_ADD,
84        QOP_SUB,
85        QOP_SHL,
86        QOP_SHR,
87        QOP_ASR,
88        QOP_MIN,
89        QOP_MAX,
90        QOP_AND,
91        QOP_OR,
92        QOP_XOR,
93        QOP_NOT,
94
95        /* Note: Orderings of these compares must be the same as in
96         * qpu_defines.h.  Selects the src[0] if the ns flag bit is set,
97         * otherwise 0. */
98        QOP_SEL_X_0_ZS,
99        QOP_SEL_X_0_ZC,
100        QOP_SEL_X_0_NS,
101        QOP_SEL_X_0_NC,
102        QOP_SEL_X_0_CS,
103        QOP_SEL_X_0_CC,
104        /* Selects the src[0] if the ns flag bit is set, otherwise src[1]. */
105        QOP_SEL_X_Y_ZS,
106        QOP_SEL_X_Y_ZC,
107        QOP_SEL_X_Y_NS,
108        QOP_SEL_X_Y_NC,
109        QOP_SEL_X_Y_CS,
110        QOP_SEL_X_Y_CC,
111
112        QOP_FTOI,
113        QOP_ITOF,
114        QOP_RCP,
115        QOP_RSQ,
116        QOP_EXP2,
117        QOP_LOG2,
118        QOP_VW_SETUP,
119        QOP_VR_SETUP,
120        QOP_TLB_DISCARD_SETUP,
121        QOP_TLB_STENCIL_SETUP,
122        QOP_TLB_Z_WRITE,
123        QOP_TLB_COLOR_WRITE,
124        QOP_TLB_COLOR_READ,
125        QOP_MS_MASK,
126        QOP_VARY_ADD_C,
127
128        QOP_FRAG_X,
129        QOP_FRAG_Y,
130        QOP_FRAG_Z,
131        QOP_FRAG_W,
132        QOP_FRAG_REV_FLAG,
133
134        /** Texture x coordinate parameter write */
135        QOP_TEX_S,
136        /** Texture y coordinate parameter write */
137        QOP_TEX_T,
138        /** Texture border color parameter or cube map z coordinate write */
139        QOP_TEX_R,
140        /** Texture LOD bias parameter write */
141        QOP_TEX_B,
142
143        /**
144         * Texture-unit 4-byte read with address provided direct in S
145         * cooordinate.
146         *
147         * The first operand is the offset from the start of the UBO, and the
148         * second is the uniform that has the UBO's base pointer.
149         */
150        QOP_TEX_DIRECT,
151
152        /**
153         * Signal of texture read being necessary and then reading r4 into
154         * the destination
155         */
156        QOP_TEX_RESULT,
157};
158
159struct queued_qpu_inst {
160        struct list_head link;
161        uint64_t inst;
162};
163
164struct qinst {
165        struct list_head link;
166
167        enum qop op;
168        struct qreg dst;
169        struct qreg *src;
170        bool sf;
171};
172
173enum qstage {
174        /**
175         * Coordinate shader, runs during binning, before the VS, and just
176         * outputs position.
177         */
178        QSTAGE_COORD,
179        QSTAGE_VERT,
180        QSTAGE_FRAG,
181};
182
183enum quniform_contents {
184        /**
185         * Indicates that a constant 32-bit value is copied from the program's
186         * uniform contents.
187         */
188        QUNIFORM_CONSTANT,
189        /**
190         * Indicates that the program's uniform contents are used as an index
191         * into the GL uniform storage.
192         */
193        QUNIFORM_UNIFORM,
194
195        /** @{
196         * Scaling factors from clip coordinates to relative to the viewport
197         * center.
198         *
199         * This is used by the coordinate and vertex shaders to produce the
200         * 32-bit entry consisting of 2 16-bit fields with 12.4 signed fixed
201         * point offsets from the viewport ccenter.
202         */
203        QUNIFORM_VIEWPORT_X_SCALE,
204        QUNIFORM_VIEWPORT_Y_SCALE,
205        /** @} */
206
207        QUNIFORM_VIEWPORT_Z_OFFSET,
208        QUNIFORM_VIEWPORT_Z_SCALE,
209
210        QUNIFORM_USER_CLIP_PLANE,
211
212        /**
213         * A reference to a texture config parameter 0 uniform.
214         *
215         * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
216         * defines texture type, miplevels, and such.  It will be found as a
217         * parameter to the first QOP_TEX_[STRB] instruction in a sequence.
218         */
219        QUNIFORM_TEXTURE_CONFIG_P0,
220
221        /**
222         * A reference to a texture config parameter 1 uniform.
223         *
224         * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
225         * defines texture width, height, filters, and wrap modes.  It will be
226         * found as a parameter to the second QOP_TEX_[STRB] instruction in a
227         * sequence.
228         */
229        QUNIFORM_TEXTURE_CONFIG_P1,
230
231        /** A reference to a texture config parameter 2 cubemap stride uniform */
232        QUNIFORM_TEXTURE_CONFIG_P2,
233
234        QUNIFORM_UBO_ADDR,
235
236        QUNIFORM_TEXRECT_SCALE_X,
237        QUNIFORM_TEXRECT_SCALE_Y,
238
239        QUNIFORM_TEXTURE_BORDER_COLOR,
240
241        QUNIFORM_BLEND_CONST_COLOR_X,
242        QUNIFORM_BLEND_CONST_COLOR_Y,
243        QUNIFORM_BLEND_CONST_COLOR_Z,
244        QUNIFORM_BLEND_CONST_COLOR_W,
245        QUNIFORM_BLEND_CONST_COLOR_RGBA,
246        QUNIFORM_BLEND_CONST_COLOR_AAAA,
247
248        QUNIFORM_STENCIL,
249
250        QUNIFORM_ALPHA_REF,
251        QUNIFORM_SAMPLE_MASK,
252};
253
254struct vc4_varying_slot {
255        uint8_t slot;
256        uint8_t swizzle;
257};
258
259struct vc4_compiler_ubo_range {
260        /**
261         * offset in bytes from the start of the ubo where this range is
262         * uploaded.
263         *
264         * Only set once used is set.
265         */
266        uint32_t dst_offset;
267
268        /**
269         * offset in bytes from the start of the gallium uniforms where the
270         * data comes from.
271         */
272        uint32_t src_offset;
273
274        /** size in bytes of this ubo range */
275        uint32_t size;
276
277        /**
278         * Set if this range is used by the shader for indirect uniforms
279         * access.
280         */
281        bool used;
282};
283
284struct vc4_key {
285        struct vc4_uncompiled_shader *shader_state;
286        struct {
287                enum pipe_format format;
288                unsigned compare_mode:1;
289                unsigned compare_func:3;
290                unsigned wrap_s:3;
291                unsigned wrap_t:3;
292                uint8_t swizzle[4];
293        } tex[VC4_MAX_TEXTURE_SAMPLERS];
294        uint8_t ucp_enables;
295};
296
297struct vc4_fs_key {
298        struct vc4_key base;
299        enum pipe_format color_format;
300        bool depth_enabled;
301        bool stencil_enabled;
302        bool stencil_twoside;
303        bool stencil_full_writemasks;
304        bool is_points;
305        bool is_lines;
306        bool alpha_test;
307        bool point_coord_upper_left;
308        bool light_twoside;
309        uint8_t alpha_test_func;
310        uint8_t logicop_func;
311        uint32_t point_sprite_mask;
312
313        struct pipe_rt_blend_state blend;
314};
315
316struct vc4_vs_key {
317        struct vc4_key base;
318
319        /**
320         * This is a proxy for the array of FS input semantics, which is
321         * larger than we would want to put in the key.
322         */
323        uint64_t compiled_fs_id;
324
325        enum pipe_format attr_formats[8];
326        bool is_coord;
327        bool per_vertex_point_size;
328};
329
330struct vc4_compile {
331        struct vc4_context *vc4;
332        nir_shader *s;
333        nir_function_impl *impl;
334        struct exec_list *cf_node_list;
335
336        /**
337         * Mapping from nir_register * or nir_ssa_def * to array of struct
338         * qreg for the values.
339         */
340        struct hash_table *def_ht;
341
342        /* For each temp, the instruction generating its value. */
343        struct qinst **defs;
344        uint32_t defs_array_size;
345
346        /**
347         * Inputs to the shader, arranged by TGSI declaration order.
348         *
349         * Not all fragment shader QFILE_VARY reads are present in this array.
350         */
351        struct qreg *inputs;
352        struct qreg *outputs;
353        uint32_t inputs_array_size;
354        uint32_t outputs_array_size;
355        uint32_t uniforms_array_size;
356
357        struct vc4_compiler_ubo_range *ubo_ranges;
358        uint32_t ubo_ranges_array_size;
359        /** Number of uniform areas declared in ubo_ranges. */
360        uint32_t num_uniform_ranges;
361        /** Number of uniform areas used for indirect addressed loads. */
362        uint32_t num_ubo_ranges;
363        uint32_t next_ubo_dst_offset;
364
365        struct qreg line_x, point_x, point_y;
366        struct qreg discard;
367
368        uint8_t vattr_sizes[8];
369
370        /**
371         * Array of the VARYING_SLOT_* of all FS QFILE_VARY reads.
372         *
373         * This includes those that aren't part of the VPM varyings, like
374         * point/line coordinates.
375         */
376        struct vc4_varying_slot *input_slots;
377        uint32_t num_input_slots;
378        uint32_t input_slots_array_size;
379
380        /**
381         * An entry per outputs[] in the VS indicating what the VARYING_SLOT_*
382         * of the output is.  Used to emit from the VS in the order that the
383         * FS needs.
384         */
385        struct vc4_varying_slot *output_slots;
386
387        struct pipe_shader_state *shader_state;
388        struct vc4_key *key;
389        struct vc4_fs_key *fs_key;
390        struct vc4_vs_key *vs_key;
391
392        uint32_t *uniform_data;
393        enum quniform_contents *uniform_contents;
394        uint32_t uniform_array_size;
395        uint32_t num_uniforms;
396        uint32_t num_outputs;
397        uint32_t num_texture_samples;
398        uint32_t output_position_index;
399        uint32_t output_color_index;
400        uint32_t output_point_size_index;
401        uint32_t output_sample_mask_index;
402
403        struct qreg undef;
404        enum qstage stage;
405        uint32_t num_temps;
406        struct list_head instructions;
407        uint32_t immediates[1024];
408
409        struct list_head qpu_inst_list;
410        uint64_t *qpu_insts;
411        uint32_t qpu_inst_count;
412        uint32_t qpu_inst_size;
413        uint32_t num_inputs;
414
415        uint32_t program_id;
416        uint32_t variant_id;
417};
418
419/* Special nir_load_input intrinsic index for loading the current TLB
420 * destination color.
421 */
422#define VC4_NIR_TLB_COLOR_READ_INPUT		2000000000
423
424/* Special offset for nir_load_uniform values to get a QUNIFORM_*
425 * state-dependent value.
426 */
427#define VC4_NIR_STATE_UNIFORM_OFFSET		2000000000
428
429struct vc4_compile *qir_compile_init(void);
430void qir_compile_destroy(struct vc4_compile *c);
431struct qinst *qir_inst(enum qop op, struct qreg dst,
432                       struct qreg src0, struct qreg src1);
433struct qinst *qir_inst4(enum qop op, struct qreg dst,
434                        struct qreg a,
435                        struct qreg b,
436                        struct qreg c,
437                        struct qreg d);
438void qir_remove_instruction(struct vc4_compile *c, struct qinst *qinst);
439struct qreg qir_uniform(struct vc4_compile *c,
440                        enum quniform_contents contents,
441                        uint32_t data);
442void qir_reorder_uniforms(struct vc4_compile *c);
443
444void qir_emit(struct vc4_compile *c, struct qinst *inst);
445static inline void qir_emit_nodef(struct vc4_compile *c, struct qinst *inst)
446{
447        list_addtail(&inst->link, &c->instructions);
448}
449
450struct qreg qir_get_temp(struct vc4_compile *c);
451int qir_get_op_nsrc(enum qop qop);
452bool qir_reg_equals(struct qreg a, struct qreg b);
453bool qir_has_side_effects(struct vc4_compile *c, struct qinst *inst);
454bool qir_has_side_effect_reads(struct vc4_compile *c, struct qinst *inst);
455bool qir_is_multi_instruction(struct qinst *inst);
456bool qir_is_mul(struct qinst *inst);
457bool qir_is_raw_mov(struct qinst *inst);
458bool qir_is_tex(struct qinst *inst);
459bool qir_is_float_input(struct qinst *inst);
460bool qir_depends_on_flags(struct qinst *inst);
461bool qir_writes_r4(struct qinst *inst);
462struct qreg qir_follow_movs(struct vc4_compile *c, struct qreg reg);
463
464void qir_dump(struct vc4_compile *c);
465void qir_dump_inst(struct vc4_compile *c, struct qinst *inst);
466const char *qir_get_stage_name(enum qstage stage);
467
468void qir_optimize(struct vc4_compile *c);
469bool qir_opt_algebraic(struct vc4_compile *c);
470bool qir_opt_constant_folding(struct vc4_compile *c);
471bool qir_opt_copy_propagation(struct vc4_compile *c);
472bool qir_opt_cse(struct vc4_compile *c);
473bool qir_opt_dead_code(struct vc4_compile *c);
474bool qir_opt_small_immediates(struct vc4_compile *c);
475bool qir_opt_vpm_writes(struct vc4_compile *c);
476void vc4_nir_lower_blend(struct vc4_compile *c);
477void vc4_nir_lower_io(struct vc4_compile *c);
478nir_ssa_def *vc4_nir_get_state_uniform(struct nir_builder *b,
479                                       enum quniform_contents contents);
480nir_ssa_def *vc4_nir_get_swizzled_channel(struct nir_builder *b,
481                                          nir_ssa_def **srcs, int swiz);
482void qir_lower_uniforms(struct vc4_compile *c);
483
484void qpu_schedule_instructions(struct vc4_compile *c);
485
486void qir_SF(struct vc4_compile *c, struct qreg src);
487
488static inline struct qreg
489qir_uniform_ui(struct vc4_compile *c, uint32_t ui)
490{
491        return qir_uniform(c, QUNIFORM_CONSTANT, ui);
492}
493
494static inline struct qreg
495qir_uniform_f(struct vc4_compile *c, float f)
496{
497        return qir_uniform(c, QUNIFORM_CONSTANT, fui(f));
498}
499
500#define QIR_ALU0(name)                                                   \
501static inline struct qreg                                                \
502qir_##name(struct vc4_compile *c)                                        \
503{                                                                        \
504        struct qreg t = qir_get_temp(c);                                 \
505        qir_emit(c, qir_inst(QOP_##name, t, c->undef, c->undef));        \
506        return t;                                                        \
507}
508
509#define QIR_ALU1(name)                                                   \
510static inline struct qreg                                                \
511qir_##name(struct vc4_compile *c, struct qreg a)                         \
512{                                                                        \
513        struct qreg t = qir_get_temp(c);                                 \
514        qir_emit(c, qir_inst(QOP_##name, t, a, c->undef));               \
515        return t;                                                        \
516}                                                                        \
517static inline void                                                       \
518qir_##name##_dest(struct vc4_compile *c, struct qreg dest,               \
519                  struct qreg a)                                         \
520{                                                                        \
521        qir_emit_nodef(c, qir_inst(QOP_##name, dest, a, c->undef));      \
522}
523
524#define QIR_ALU2(name)                                                   \
525static inline struct qreg                                                \
526qir_##name(struct vc4_compile *c, struct qreg a, struct qreg b)          \
527{                                                                        \
528        struct qreg t = qir_get_temp(c);                                 \
529        qir_emit(c, qir_inst(QOP_##name, t, a, b));                      \
530        return t;                                                        \
531}                                                                        \
532static inline void                                                       \
533qir_##name##_dest(struct vc4_compile *c, struct qreg dest,               \
534                  struct qreg a, struct qreg b)                          \
535{                                                                        \
536        qir_emit_nodef(c, qir_inst(QOP_##name, dest, a, b));             \
537}
538
539#define QIR_NODST_1(name)                                               \
540static inline void                                                      \
541qir_##name(struct vc4_compile *c, struct qreg a)                        \
542{                                                                       \
543        qir_emit(c, qir_inst(QOP_##name, c->undef, a, c->undef));       \
544}
545
546#define QIR_NODST_2(name)                                               \
547static inline void                                                      \
548qir_##name(struct vc4_compile *c, struct qreg a, struct qreg b)         \
549{                                                                       \
550        qir_emit(c, qir_inst(QOP_##name, c->undef, a, b));       \
551}
552
553#define QIR_PACK(name)                                                   \
554static inline struct qreg                                                \
555qir_##name(struct vc4_compile *c, struct qreg dest, struct qreg a)       \
556{                                                                        \
557        qir_emit_nodef(c, qir_inst(QOP_##name, dest, a, c->undef));      \
558        return dest;                                                     \
559}
560
561QIR_ALU1(MOV)
562QIR_ALU1(FMOV)
563QIR_ALU1(MMOV)
564QIR_ALU2(FADD)
565QIR_ALU2(FSUB)
566QIR_ALU2(FMUL)
567QIR_ALU2(V8MULD)
568QIR_ALU2(V8MIN)
569QIR_ALU2(V8MAX)
570QIR_ALU2(V8ADDS)
571QIR_ALU2(V8SUBS)
572QIR_ALU2(MUL24)
573QIR_ALU1(SEL_X_0_ZS)
574QIR_ALU1(SEL_X_0_ZC)
575QIR_ALU1(SEL_X_0_NS)
576QIR_ALU1(SEL_X_0_NC)
577QIR_ALU1(SEL_X_0_CS)
578QIR_ALU1(SEL_X_0_CC)
579QIR_ALU2(SEL_X_Y_ZS)
580QIR_ALU2(SEL_X_Y_ZC)
581QIR_ALU2(SEL_X_Y_NS)
582QIR_ALU2(SEL_X_Y_NC)
583QIR_ALU2(SEL_X_Y_CS)
584QIR_ALU2(SEL_X_Y_CC)
585QIR_ALU2(FMIN)
586QIR_ALU2(FMAX)
587QIR_ALU2(FMINABS)
588QIR_ALU2(FMAXABS)
589QIR_ALU1(FTOI)
590QIR_ALU1(ITOF)
591
592QIR_ALU2(ADD)
593QIR_ALU2(SUB)
594QIR_ALU2(SHL)
595QIR_ALU2(SHR)
596QIR_ALU2(ASR)
597QIR_ALU2(MIN)
598QIR_ALU2(MAX)
599QIR_ALU2(AND)
600QIR_ALU2(OR)
601QIR_ALU2(XOR)
602QIR_ALU1(NOT)
603
604QIR_ALU1(RCP)
605QIR_ALU1(RSQ)
606QIR_ALU1(EXP2)
607QIR_ALU1(LOG2)
608QIR_ALU1(VARY_ADD_C)
609QIR_NODST_2(TEX_S)
610QIR_NODST_2(TEX_T)
611QIR_NODST_2(TEX_R)
612QIR_NODST_2(TEX_B)
613QIR_NODST_2(TEX_DIRECT)
614QIR_ALU0(FRAG_X)
615QIR_ALU0(FRAG_Y)
616QIR_ALU0(FRAG_Z)
617QIR_ALU0(FRAG_W)
618QIR_ALU0(FRAG_REV_FLAG)
619QIR_ALU0(TEX_RESULT)
620QIR_ALU0(TLB_COLOR_READ)
621QIR_NODST_1(TLB_COLOR_WRITE)
622QIR_NODST_1(TLB_Z_WRITE)
623QIR_NODST_1(TLB_DISCARD_SETUP)
624QIR_NODST_1(TLB_STENCIL_SETUP)
625QIR_NODST_1(MS_MASK)
626
627static inline struct qreg
628qir_UNPACK_8_F(struct vc4_compile *c, struct qreg src, int i)
629{
630        struct qreg t = qir_FMOV(c, src);
631        c->defs[t.index]->src[0].pack = QPU_UNPACK_8A + i;
632        return t;
633}
634
635static inline struct qreg
636qir_UNPACK_8_I(struct vc4_compile *c, struct qreg src, int i)
637{
638        struct qreg t = qir_MOV(c, src);
639        c->defs[t.index]->src[0].pack = QPU_UNPACK_8A + i;
640        return t;
641}
642
643static inline struct qreg
644qir_UNPACK_16_F(struct vc4_compile *c, struct qreg src, int i)
645{
646        struct qreg t = qir_FMOV(c, src);
647        c->defs[t.index]->src[0].pack = QPU_UNPACK_16A + i;
648        return t;
649}
650
651static inline struct qreg
652qir_UNPACK_16_I(struct vc4_compile *c, struct qreg src, int i)
653{
654        struct qreg t = qir_MOV(c, src);
655        c->defs[t.index]->src[0].pack = QPU_UNPACK_16A + i;
656        return t;
657}
658
659static inline void
660qir_PACK_8_F(struct vc4_compile *c, struct qreg dest, struct qreg val, int chan)
661{
662        assert(!dest.pack);
663        dest.pack = QPU_PACK_MUL_8A + chan;
664        qir_emit(c, qir_inst(QOP_MMOV, dest, val, c->undef));
665        if (dest.file == QFILE_TEMP)
666                c->defs[dest.index] = NULL;
667}
668
669static inline struct qreg
670qir_PACK_8888_F(struct vc4_compile *c, struct qreg val)
671{
672        struct qreg dest = qir_MMOV(c, val);
673        c->defs[dest.index]->dst.pack = QPU_PACK_MUL_8888;
674        return dest;
675}
676
677static inline struct qreg
678qir_POW(struct vc4_compile *c, struct qreg x, struct qreg y)
679{
680        return qir_EXP2(c, qir_FMUL(c,
681                                    y,
682                                    qir_LOG2(c, x)));
683}
684
685static inline void
686qir_VPM_WRITE(struct vc4_compile *c, struct qreg val)
687{
688        static const struct qreg vpm = { QFILE_VPM, 0 };
689        qir_emit(c, qir_inst(QOP_MOV, vpm, val, c->undef));
690}
691
692#endif /* VC4_QIR_H */
693