vc4_qir.h revision 89918c1e74e454af119e7ae23f3ed66fc26abc4b
1/* 2 * Copyright © 2014 Broadcom 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24#ifndef VC4_QIR_H 25#define VC4_QIR_H 26 27#include <assert.h> 28#include <stdio.h> 29#include <stdlib.h> 30#include <stdbool.h> 31#include <stdint.h> 32#include <string.h> 33 34#include "util/macros.h" 35#include "compiler/nir/nir.h" 36#include "util/list.h" 37#include "util/u_math.h" 38 39#include "vc4_screen.h" 40#include "vc4_qpu_defines.h" 41#include "vc4_qpu.h" 42#include "kernel/vc4_packet.h" 43#include "pipe/p_state.h" 44 45struct nir_builder; 46 47enum qfile { 48 QFILE_NULL, 49 QFILE_TEMP, 50 QFILE_VARY, 51 QFILE_UNIF, 52 QFILE_VPM, 53 QFILE_TLB_COLOR_WRITE, 54 QFILE_TLB_COLOR_WRITE_MS, 55 QFILE_TLB_Z_WRITE, 56 QFILE_TLB_STENCIL_SETUP, 57 58 /* Payload registers that aren't in the physical register file, so we 59 * can just use the corresponding qpu_reg at qpu_emit time. 60 */ 61 QFILE_FRAG_X, 62 QFILE_FRAG_Y, 63 QFILE_FRAG_REV_FLAG, 64 65 /** 66 * Stores an immediate value in the index field that will be used 67 * directly by qpu_load_imm(). 68 */ 69 QFILE_LOAD_IMM, 70 71 /** 72 * Stores an immediate value in the index field that can be turned 73 * into a small immediate field by qpu_encode_small_immediate(). 74 */ 75 QFILE_SMALL_IMM, 76}; 77 78struct qreg { 79 enum qfile file; 80 uint32_t index; 81 int pack; 82}; 83 84static inline struct qreg qir_reg(enum qfile file, uint32_t index) 85{ 86 return (struct qreg){file, index}; 87} 88 89enum qop { 90 QOP_UNDEF, 91 QOP_MOV, 92 QOP_FMOV, 93 QOP_MMOV, 94 QOP_FADD, 95 QOP_FSUB, 96 QOP_FMUL, 97 QOP_V8MULD, 98 QOP_V8MIN, 99 QOP_V8MAX, 100 QOP_V8ADDS, 101 QOP_V8SUBS, 102 QOP_MUL24, 103 QOP_FMIN, 104 QOP_FMAX, 105 QOP_FMINABS, 106 QOP_FMAXABS, 107 QOP_ADD, 108 QOP_SUB, 109 QOP_SHL, 110 QOP_SHR, 111 QOP_ASR, 112 QOP_MIN, 113 QOP_MAX, 114 QOP_AND, 115 QOP_OR, 116 QOP_XOR, 117 QOP_NOT, 118 119 QOP_FTOI, 120 QOP_ITOF, 121 QOP_RCP, 122 QOP_RSQ, 123 QOP_EXP2, 124 QOP_LOG2, 125 QOP_VW_SETUP, 126 QOP_VR_SETUP, 127 QOP_TLB_COLOR_READ, 128 QOP_MS_MASK, 129 QOP_VARY_ADD_C, 130 131 QOP_FRAG_Z, 132 QOP_FRAG_W, 133 134 /** Texture x coordinate parameter write */ 135 QOP_TEX_S, 136 /** Texture y coordinate parameter write */ 137 QOP_TEX_T, 138 /** Texture border color parameter or cube map z coordinate write */ 139 QOP_TEX_R, 140 /** Texture LOD bias parameter write */ 141 QOP_TEX_B, 142 143 /** 144 * Texture-unit 4-byte read with address provided direct in S 145 * cooordinate. 146 * 147 * The first operand is the offset from the start of the UBO, and the 148 * second is the uniform that has the UBO's base pointer. 149 */ 150 QOP_TEX_DIRECT, 151 152 /** 153 * Signal of texture read being necessary and then reading r4 into 154 * the destination 155 */ 156 QOP_TEX_RESULT, 157 158 QOP_LOAD_IMM, 159}; 160 161struct queued_qpu_inst { 162 struct list_head link; 163 uint64_t inst; 164}; 165 166struct qinst { 167 struct list_head link; 168 169 enum qop op; 170 struct qreg dst; 171 struct qreg *src; 172 bool sf; 173 uint8_t cond; 174}; 175 176enum qstage { 177 /** 178 * Coordinate shader, runs during binning, before the VS, and just 179 * outputs position. 180 */ 181 QSTAGE_COORD, 182 QSTAGE_VERT, 183 QSTAGE_FRAG, 184}; 185 186enum quniform_contents { 187 /** 188 * Indicates that a constant 32-bit value is copied from the program's 189 * uniform contents. 190 */ 191 QUNIFORM_CONSTANT, 192 /** 193 * Indicates that the program's uniform contents are used as an index 194 * into the GL uniform storage. 195 */ 196 QUNIFORM_UNIFORM, 197 198 /** @{ 199 * Scaling factors from clip coordinates to relative to the viewport 200 * center. 201 * 202 * This is used by the coordinate and vertex shaders to produce the 203 * 32-bit entry consisting of 2 16-bit fields with 12.4 signed fixed 204 * point offsets from the viewport ccenter. 205 */ 206 QUNIFORM_VIEWPORT_X_SCALE, 207 QUNIFORM_VIEWPORT_Y_SCALE, 208 /** @} */ 209 210 QUNIFORM_VIEWPORT_Z_OFFSET, 211 QUNIFORM_VIEWPORT_Z_SCALE, 212 213 QUNIFORM_USER_CLIP_PLANE, 214 215 /** 216 * A reference to a texture config parameter 0 uniform. 217 * 218 * This is a uniform implicitly loaded with a QPU_W_TMU* write, which 219 * defines texture type, miplevels, and such. It will be found as a 220 * parameter to the first QOP_TEX_[STRB] instruction in a sequence. 221 */ 222 QUNIFORM_TEXTURE_CONFIG_P0, 223 224 /** 225 * A reference to a texture config parameter 1 uniform. 226 * 227 * This is a uniform implicitly loaded with a QPU_W_TMU* write, which 228 * defines texture width, height, filters, and wrap modes. It will be 229 * found as a parameter to the second QOP_TEX_[STRB] instruction in a 230 * sequence. 231 */ 232 QUNIFORM_TEXTURE_CONFIG_P1, 233 234 /** A reference to a texture config parameter 2 cubemap stride uniform */ 235 QUNIFORM_TEXTURE_CONFIG_P2, 236 237 QUNIFORM_TEXTURE_MSAA_ADDR, 238 239 QUNIFORM_UBO_ADDR, 240 241 QUNIFORM_TEXRECT_SCALE_X, 242 QUNIFORM_TEXRECT_SCALE_Y, 243 244 QUNIFORM_TEXTURE_BORDER_COLOR, 245 246 QUNIFORM_BLEND_CONST_COLOR_X, 247 QUNIFORM_BLEND_CONST_COLOR_Y, 248 QUNIFORM_BLEND_CONST_COLOR_Z, 249 QUNIFORM_BLEND_CONST_COLOR_W, 250 QUNIFORM_BLEND_CONST_COLOR_RGBA, 251 QUNIFORM_BLEND_CONST_COLOR_AAAA, 252 253 QUNIFORM_STENCIL, 254 255 QUNIFORM_ALPHA_REF, 256 QUNIFORM_SAMPLE_MASK, 257}; 258 259struct vc4_varying_slot { 260 uint8_t slot; 261 uint8_t swizzle; 262}; 263 264struct vc4_compiler_ubo_range { 265 /** 266 * offset in bytes from the start of the ubo where this range is 267 * uploaded. 268 * 269 * Only set once used is set. 270 */ 271 uint32_t dst_offset; 272 273 /** 274 * offset in bytes from the start of the gallium uniforms where the 275 * data comes from. 276 */ 277 uint32_t src_offset; 278 279 /** size in bytes of this ubo range */ 280 uint32_t size; 281 282 /** 283 * Set if this range is used by the shader for indirect uniforms 284 * access. 285 */ 286 bool used; 287}; 288 289struct vc4_key { 290 struct vc4_uncompiled_shader *shader_state; 291 struct { 292 enum pipe_format format; 293 uint8_t swizzle[4]; 294 union { 295 struct { 296 unsigned compare_mode:1; 297 unsigned compare_func:3; 298 unsigned wrap_s:3; 299 unsigned wrap_t:3; 300 }; 301 struct { 302 uint16_t msaa_width, msaa_height; 303 }; 304 }; 305 } tex[VC4_MAX_TEXTURE_SAMPLERS]; 306 uint8_t ucp_enables; 307}; 308 309struct vc4_fs_key { 310 struct vc4_key base; 311 enum pipe_format color_format; 312 bool depth_enabled; 313 bool stencil_enabled; 314 bool stencil_twoside; 315 bool stencil_full_writemasks; 316 bool is_points; 317 bool is_lines; 318 bool alpha_test; 319 bool point_coord_upper_left; 320 bool light_twoside; 321 bool msaa; 322 bool sample_coverage; 323 bool sample_alpha_to_coverage; 324 bool sample_alpha_to_one; 325 uint8_t alpha_test_func; 326 uint8_t logicop_func; 327 uint32_t point_sprite_mask; 328 329 struct pipe_rt_blend_state blend; 330}; 331 332struct vc4_vs_key { 333 struct vc4_key base; 334 335 /** 336 * This is a proxy for the array of FS input semantics, which is 337 * larger than we would want to put in the key. 338 */ 339 uint64_t compiled_fs_id; 340 341 enum pipe_format attr_formats[8]; 342 bool is_coord; 343 bool per_vertex_point_size; 344 bool clamp_color; 345}; 346 347/** A basic block of QIR intructions. */ 348struct qblock { 349 struct list_head link; 350 351 struct list_head instructions; 352 353 struct set *predecessors; 354 struct qblock *successors[2]; 355 356 int index; 357 358 /** @{ used by vc4_qir_live_variables.c */ 359 BITSET_WORD *def; 360 BITSET_WORD *use; 361 BITSET_WORD *live_in; 362 BITSET_WORD *live_out; 363 int start_ip, end_ip; 364 /** @} */ 365}; 366 367struct vc4_compile { 368 struct vc4_context *vc4; 369 nir_shader *s; 370 nir_function_impl *impl; 371 struct exec_list *cf_node_list; 372 373 /** 374 * Mapping from nir_register * or nir_ssa_def * to array of struct 375 * qreg for the values. 376 */ 377 struct hash_table *def_ht; 378 379 /* For each temp, the instruction generating its value. */ 380 struct qinst **defs; 381 uint32_t defs_array_size; 382 383 /** 384 * Inputs to the shader, arranged by TGSI declaration order. 385 * 386 * Not all fragment shader QFILE_VARY reads are present in this array. 387 */ 388 struct qreg *inputs; 389 struct qreg *outputs; 390 bool msaa_per_sample_output; 391 struct qreg color_reads[VC4_MAX_SAMPLES]; 392 struct qreg sample_colors[VC4_MAX_SAMPLES]; 393 uint32_t inputs_array_size; 394 uint32_t outputs_array_size; 395 uint32_t uniforms_array_size; 396 397 struct vc4_compiler_ubo_range *ubo_ranges; 398 uint32_t ubo_ranges_array_size; 399 /** Number of uniform areas declared in ubo_ranges. */ 400 uint32_t num_uniform_ranges; 401 /** Number of uniform areas used for indirect addressed loads. */ 402 uint32_t num_ubo_ranges; 403 uint32_t next_ubo_dst_offset; 404 405 struct qreg line_x, point_x, point_y; 406 struct qreg discard; 407 struct qreg payload_FRAG_Z; 408 struct qreg payload_FRAG_W; 409 410 uint8_t vattr_sizes[8]; 411 412 /** 413 * Array of the VARYING_SLOT_* of all FS QFILE_VARY reads. 414 * 415 * This includes those that aren't part of the VPM varyings, like 416 * point/line coordinates. 417 */ 418 struct vc4_varying_slot *input_slots; 419 uint32_t num_input_slots; 420 uint32_t input_slots_array_size; 421 422 /** 423 * An entry per outputs[] in the VS indicating what the VARYING_SLOT_* 424 * of the output is. Used to emit from the VS in the order that the 425 * FS needs. 426 */ 427 struct vc4_varying_slot *output_slots; 428 429 struct pipe_shader_state *shader_state; 430 struct vc4_key *key; 431 struct vc4_fs_key *fs_key; 432 struct vc4_vs_key *vs_key; 433 434 /* Live ranges of temps. */ 435 int *temp_start, *temp_end; 436 437 uint32_t *uniform_data; 438 enum quniform_contents *uniform_contents; 439 uint32_t uniform_array_size; 440 uint32_t num_uniforms; 441 uint32_t num_outputs; 442 uint32_t num_texture_samples; 443 uint32_t output_position_index; 444 uint32_t output_color_index; 445 uint32_t output_point_size_index; 446 uint32_t output_sample_mask_index; 447 448 struct qreg undef; 449 enum qstage stage; 450 uint32_t num_temps; 451 452 struct list_head blocks; 453 int next_block_index; 454 struct qblock *cur_block; 455 456 struct list_head qpu_inst_list; 457 uint64_t *qpu_insts; 458 uint32_t qpu_inst_count; 459 uint32_t qpu_inst_size; 460 uint32_t num_inputs; 461 462 uint32_t program_id; 463 uint32_t variant_id; 464}; 465 466/* Special nir_load_input intrinsic index for loading the current TLB 467 * destination color. 468 */ 469#define VC4_NIR_TLB_COLOR_READ_INPUT 2000000000 470 471#define VC4_NIR_MS_MASK_OUTPUT 2000000000 472 473/* Special offset for nir_load_uniform values to get a QUNIFORM_* 474 * state-dependent value. 475 */ 476#define VC4_NIR_STATE_UNIFORM_OFFSET 1000000000 477 478struct vc4_compile *qir_compile_init(void); 479void qir_compile_destroy(struct vc4_compile *c); 480struct qblock *qir_new_block(struct vc4_compile *c); 481void qir_set_emit_block(struct vc4_compile *c, struct qblock *block); 482void qir_link_blocks(struct qblock *predecessor, struct qblock *successor); 483struct qblock *qir_entry_block(struct vc4_compile *c); 484struct qblock *qir_exit_block(struct vc4_compile *c); 485struct qinst *qir_inst(enum qop op, struct qreg dst, 486 struct qreg src0, struct qreg src1); 487struct qinst *qir_inst4(enum qop op, struct qreg dst, 488 struct qreg a, 489 struct qreg b, 490 struct qreg c, 491 struct qreg d); 492void qir_remove_instruction(struct vc4_compile *c, struct qinst *qinst); 493struct qreg qir_uniform(struct vc4_compile *c, 494 enum quniform_contents contents, 495 uint32_t data); 496void qir_schedule_instructions(struct vc4_compile *c); 497void qir_reorder_uniforms(struct vc4_compile *c); 498 499struct qreg qir_emit_def(struct vc4_compile *c, struct qinst *inst); 500struct qinst *qir_emit_nondef(struct vc4_compile *c, struct qinst *inst); 501 502struct qreg qir_get_temp(struct vc4_compile *c); 503void qir_calculate_live_intervals(struct vc4_compile *c); 504int qir_get_op_nsrc(enum qop qop); 505bool qir_reg_equals(struct qreg a, struct qreg b); 506bool qir_has_side_effects(struct vc4_compile *c, struct qinst *inst); 507bool qir_has_side_effect_reads(struct vc4_compile *c, struct qinst *inst); 508bool qir_is_mul(struct qinst *inst); 509bool qir_is_raw_mov(struct qinst *inst); 510bool qir_is_tex(struct qinst *inst); 511bool qir_is_float_input(struct qinst *inst); 512bool qir_depends_on_flags(struct qinst *inst); 513bool qir_writes_r4(struct qinst *inst); 514struct qreg qir_follow_movs(struct vc4_compile *c, struct qreg reg); 515uint8_t qir_channels_written(struct qinst *inst); 516 517void qir_dump(struct vc4_compile *c); 518void qir_dump_inst(struct vc4_compile *c, struct qinst *inst); 519const char *qir_get_stage_name(enum qstage stage); 520 521void qir_validate(struct vc4_compile *c); 522 523void qir_optimize(struct vc4_compile *c); 524bool qir_opt_algebraic(struct vc4_compile *c); 525bool qir_opt_constant_folding(struct vc4_compile *c); 526bool qir_opt_copy_propagation(struct vc4_compile *c); 527bool qir_opt_dead_code(struct vc4_compile *c); 528bool qir_opt_peephole_sf(struct vc4_compile *c); 529bool qir_opt_small_immediates(struct vc4_compile *c); 530bool qir_opt_vpm(struct vc4_compile *c); 531void vc4_nir_lower_blend(nir_shader *s, struct vc4_compile *c); 532void vc4_nir_lower_io(nir_shader *s, struct vc4_compile *c); 533nir_ssa_def *vc4_nir_get_state_uniform(struct nir_builder *b, 534 enum quniform_contents contents); 535nir_ssa_def *vc4_nir_get_swizzled_channel(struct nir_builder *b, 536 nir_ssa_def **srcs, int swiz); 537void vc4_nir_lower_txf_ms(nir_shader *s, struct vc4_compile *c); 538void qir_lower_uniforms(struct vc4_compile *c); 539 540uint32_t qpu_schedule_instructions(struct vc4_compile *c); 541 542void qir_SF(struct vc4_compile *c, struct qreg src); 543 544static inline struct qreg 545qir_uniform_ui(struct vc4_compile *c, uint32_t ui) 546{ 547 return qir_uniform(c, QUNIFORM_CONSTANT, ui); 548} 549 550static inline struct qreg 551qir_uniform_f(struct vc4_compile *c, float f) 552{ 553 return qir_uniform(c, QUNIFORM_CONSTANT, fui(f)); 554} 555 556#define QIR_ALU0(name) \ 557static inline struct qreg \ 558qir_##name(struct vc4_compile *c) \ 559{ \ 560 return qir_emit_def(c, qir_inst(QOP_##name, c->undef, \ 561 c->undef, c->undef)); \ 562} \ 563static inline struct qinst * \ 564qir_##name##_dest(struct vc4_compile *c, struct qreg dest) \ 565{ \ 566 return qir_emit_nondef(c, qir_inst(QOP_##name, dest, \ 567 c->undef, c->undef)); \ 568} 569 570#define QIR_ALU1(name) \ 571static inline struct qreg \ 572qir_##name(struct vc4_compile *c, struct qreg a) \ 573{ \ 574 return qir_emit_def(c, qir_inst(QOP_##name, c->undef, \ 575 a, c->undef)); \ 576} \ 577static inline struct qinst * \ 578qir_##name##_dest(struct vc4_compile *c, struct qreg dest, \ 579 struct qreg a) \ 580{ \ 581 return qir_emit_nondef(c, qir_inst(QOP_##name, dest, a, \ 582 c->undef)); \ 583} 584 585#define QIR_ALU2(name) \ 586static inline struct qreg \ 587qir_##name(struct vc4_compile *c, struct qreg a, struct qreg b) \ 588{ \ 589 return qir_emit_def(c, qir_inst(QOP_##name, c->undef, a, b)); \ 590} \ 591static inline struct qinst * \ 592qir_##name##_dest(struct vc4_compile *c, struct qreg dest, \ 593 struct qreg a, struct qreg b) \ 594{ \ 595 return qir_emit_nondef(c, qir_inst(QOP_##name, dest, a, b)); \ 596} 597 598#define QIR_NODST_1(name) \ 599static inline struct qinst * \ 600qir_##name(struct vc4_compile *c, struct qreg a) \ 601{ \ 602 return qir_emit_nondef(c, qir_inst(QOP_##name, c->undef, \ 603 a, c->undef)); \ 604} 605 606#define QIR_NODST_2(name) \ 607static inline struct qinst * \ 608qir_##name(struct vc4_compile *c, struct qreg a, struct qreg b) \ 609{ \ 610 return qir_emit_nondef(c, qir_inst(QOP_##name, c->undef, \ 611 a, b)); \ 612} 613 614#define QIR_PAYLOAD(name) \ 615static inline struct qreg \ 616qir_##name(struct vc4_compile *c) \ 617{ \ 618 struct qreg *payload = &c->payload_##name; \ 619 if (payload->file != QFILE_NULL) \ 620 return *payload; \ 621 *payload = qir_get_temp(c); \ 622 struct qinst *inst = qir_inst(QOP_##name, *payload, \ 623 c->undef, c->undef); \ 624 struct qblock *entry = qir_entry_block(c); \ 625 list_add(&inst->link, &entry->instructions); \ 626 c->defs[payload->index] = inst; \ 627 return *payload; \ 628} 629 630QIR_ALU1(MOV) 631QIR_ALU1(FMOV) 632QIR_ALU1(MMOV) 633QIR_ALU2(FADD) 634QIR_ALU2(FSUB) 635QIR_ALU2(FMUL) 636QIR_ALU2(V8MULD) 637QIR_ALU2(V8MIN) 638QIR_ALU2(V8MAX) 639QIR_ALU2(V8ADDS) 640QIR_ALU2(V8SUBS) 641QIR_ALU2(MUL24) 642QIR_ALU2(FMIN) 643QIR_ALU2(FMAX) 644QIR_ALU2(FMINABS) 645QIR_ALU2(FMAXABS) 646QIR_ALU1(FTOI) 647QIR_ALU1(ITOF) 648 649QIR_ALU2(ADD) 650QIR_ALU2(SUB) 651QIR_ALU2(SHL) 652QIR_ALU2(SHR) 653QIR_ALU2(ASR) 654QIR_ALU2(MIN) 655QIR_ALU2(MAX) 656QIR_ALU2(AND) 657QIR_ALU2(OR) 658QIR_ALU2(XOR) 659QIR_ALU1(NOT) 660 661QIR_ALU1(RCP) 662QIR_ALU1(RSQ) 663QIR_ALU1(EXP2) 664QIR_ALU1(LOG2) 665QIR_ALU1(VARY_ADD_C) 666QIR_NODST_2(TEX_S) 667QIR_NODST_2(TEX_T) 668QIR_NODST_2(TEX_R) 669QIR_NODST_2(TEX_B) 670QIR_NODST_2(TEX_DIRECT) 671QIR_PAYLOAD(FRAG_Z) 672QIR_PAYLOAD(FRAG_W) 673QIR_ALU0(TEX_RESULT) 674QIR_ALU0(TLB_COLOR_READ) 675QIR_NODST_1(MS_MASK) 676 677static inline struct qreg 678qir_SEL(struct vc4_compile *c, uint8_t cond, struct qreg src0, struct qreg src1) 679{ 680 struct qreg t = qir_get_temp(c); 681 struct qinst *a = qir_MOV_dest(c, t, src0); 682 struct qinst *b = qir_MOV_dest(c, t, src1); 683 a->cond = cond; 684 b->cond = qpu_cond_complement(cond); 685 return t; 686} 687 688static inline struct qreg 689qir_UNPACK_8_F(struct vc4_compile *c, struct qreg src, int i) 690{ 691 struct qreg t = qir_FMOV(c, src); 692 c->defs[t.index]->src[0].pack = QPU_UNPACK_8A + i; 693 return t; 694} 695 696static inline struct qreg 697qir_UNPACK_8_I(struct vc4_compile *c, struct qreg src, int i) 698{ 699 struct qreg t = qir_MOV(c, src); 700 c->defs[t.index]->src[0].pack = QPU_UNPACK_8A + i; 701 return t; 702} 703 704static inline struct qreg 705qir_UNPACK_16_F(struct vc4_compile *c, struct qreg src, int i) 706{ 707 struct qreg t = qir_FMOV(c, src); 708 c->defs[t.index]->src[0].pack = QPU_UNPACK_16A + i; 709 return t; 710} 711 712static inline struct qreg 713qir_UNPACK_16_I(struct vc4_compile *c, struct qreg src, int i) 714{ 715 struct qreg t = qir_MOV(c, src); 716 c->defs[t.index]->src[0].pack = QPU_UNPACK_16A + i; 717 return t; 718} 719 720static inline void 721qir_PACK_8_F(struct vc4_compile *c, struct qreg dest, struct qreg val, int chan) 722{ 723 assert(!dest.pack); 724 dest.pack = QPU_PACK_MUL_8A + chan; 725 qir_emit_nondef(c, qir_inst(QOP_MMOV, dest, val, c->undef)); 726} 727 728static inline struct qreg 729qir_PACK_8888_F(struct vc4_compile *c, struct qreg val) 730{ 731 struct qreg dest = qir_MMOV(c, val); 732 c->defs[dest.index]->dst.pack = QPU_PACK_MUL_8888; 733 return dest; 734} 735 736static inline struct qreg 737qir_POW(struct vc4_compile *c, struct qreg x, struct qreg y) 738{ 739 return qir_EXP2(c, qir_FMUL(c, 740 y, 741 qir_LOG2(c, x))); 742} 743 744static inline void 745qir_VPM_WRITE(struct vc4_compile *c, struct qreg val) 746{ 747 qir_MOV_dest(c, qir_reg(QFILE_VPM, 0), val); 748} 749 750static inline struct qreg 751qir_LOAD_IMM(struct vc4_compile *c, uint32_t val) 752{ 753 return qir_emit_def(c, qir_inst(QOP_LOAD_IMM, c->undef, 754 qir_reg(QFILE_LOAD_IMM, val), c->undef)); 755} 756 757#define qir_for_each_block(block, c) \ 758 list_for_each_entry(struct qblock, block, &c->blocks, link) 759 760#define qir_for_each_block_rev(block, c) \ 761 list_for_each_entry_rev(struct qblock, block, &c->blocks, link) 762 763/* Loop over the non-NULL members of the successors array. */ 764#define qir_for_each_successor(succ, block) \ 765 for (struct qblock *succ = block->successors[0]; \ 766 succ != NULL; \ 767 succ = (succ == block->successors[1] ? NULL : \ 768 block->successors[1])) 769 770#define qir_for_each_inst(inst, block) \ 771 list_for_each_entry(struct qinst, inst, &block->instructions, link) 772 773#define qir_for_each_inst_rev(inst, block) \ 774 list_for_each_entry_rev(struct qinst, inst, &block->instructions, link) 775 776#define qir_for_each_inst_safe(inst, block) \ 777 list_for_each_entry_safe(struct qinst, inst, &block->instructions, link) 778 779#define qir_for_each_inst_inorder(inst, c) \ 780 qir_for_each_block(_block, c) \ 781 qir_for_each_inst(inst, _block) 782 783#endif /* VC4_QIR_H */ 784