vc4_qir.h revision eaa53f80d9da292ade219c609f8ac37f9a8ca0d7
1/* 2 * Copyright © 2014 Broadcom 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24#ifndef VC4_QIR_H 25#define VC4_QIR_H 26 27#include <assert.h> 28#include <stdio.h> 29#include <stdlib.h> 30#include <stdbool.h> 31#include <stdint.h> 32#include <string.h> 33 34#include "util/macros.h" 35#include "compiler/nir/nir.h" 36#include "util/list.h" 37#include "util/u_math.h" 38 39#include "vc4_screen.h" 40#include "vc4_qpu_defines.h" 41#include "kernel/vc4_packet.h" 42#include "pipe/p_state.h" 43 44struct nir_builder; 45 46enum qfile { 47 QFILE_NULL, 48 QFILE_TEMP, 49 QFILE_VARY, 50 QFILE_UNIF, 51 QFILE_VPM, 52 QFILE_TLB_COLOR_WRITE, 53 QFILE_TLB_COLOR_WRITE_MS, 54 QFILE_TLB_Z_WRITE, 55 QFILE_TLB_STENCIL_SETUP, 56 57 /* Payload registers that aren't in the physical register file, so we 58 * can just use the corresponding qpu_reg at qpu_emit time. 59 */ 60 QFILE_FRAG_X, 61 QFILE_FRAG_Y, 62 QFILE_FRAG_REV_FLAG, 63 64 /** 65 * Stores an immediate value in the index field that will be used 66 * directly by qpu_load_imm(). 67 */ 68 QFILE_LOAD_IMM, 69 70 /** 71 * Stores an immediate value in the index field that can be turned 72 * into a small immediate field by qpu_encode_small_immediate(). 73 */ 74 QFILE_SMALL_IMM, 75}; 76 77struct qreg { 78 enum qfile file; 79 uint32_t index; 80 int pack; 81}; 82 83static inline struct qreg qir_reg(enum qfile file, uint32_t index) 84{ 85 return (struct qreg){file, index}; 86} 87 88enum qop { 89 QOP_UNDEF, 90 QOP_MOV, 91 QOP_FMOV, 92 QOP_MMOV, 93 QOP_FADD, 94 QOP_FSUB, 95 QOP_FMUL, 96 QOP_V8MULD, 97 QOP_V8MIN, 98 QOP_V8MAX, 99 QOP_V8ADDS, 100 QOP_V8SUBS, 101 QOP_MUL24, 102 QOP_FMIN, 103 QOP_FMAX, 104 QOP_FMINABS, 105 QOP_FMAXABS, 106 QOP_ADD, 107 QOP_SUB, 108 QOP_SHL, 109 QOP_SHR, 110 QOP_ASR, 111 QOP_MIN, 112 QOP_MAX, 113 QOP_AND, 114 QOP_OR, 115 QOP_XOR, 116 QOP_NOT, 117 118 QOP_FTOI, 119 QOP_ITOF, 120 QOP_RCP, 121 QOP_RSQ, 122 QOP_EXP2, 123 QOP_LOG2, 124 QOP_VW_SETUP, 125 QOP_VR_SETUP, 126 QOP_TLB_COLOR_READ, 127 QOP_MS_MASK, 128 QOP_VARY_ADD_C, 129 130 QOP_FRAG_Z, 131 QOP_FRAG_W, 132 133 /** Texture x coordinate parameter write */ 134 QOP_TEX_S, 135 /** Texture y coordinate parameter write */ 136 QOP_TEX_T, 137 /** Texture border color parameter or cube map z coordinate write */ 138 QOP_TEX_R, 139 /** Texture LOD bias parameter write */ 140 QOP_TEX_B, 141 142 /** 143 * Texture-unit 4-byte read with address provided direct in S 144 * cooordinate. 145 * 146 * The first operand is the offset from the start of the UBO, and the 147 * second is the uniform that has the UBO's base pointer. 148 */ 149 QOP_TEX_DIRECT, 150 151 /** 152 * Signal of texture read being necessary and then reading r4 into 153 * the destination 154 */ 155 QOP_TEX_RESULT, 156 157 QOP_LOAD_IMM, 158}; 159 160struct queued_qpu_inst { 161 struct list_head link; 162 uint64_t inst; 163}; 164 165struct qinst { 166 struct list_head link; 167 168 enum qop op; 169 struct qreg dst; 170 struct qreg *src; 171 bool sf; 172 uint8_t cond; 173}; 174 175enum qstage { 176 /** 177 * Coordinate shader, runs during binning, before the VS, and just 178 * outputs position. 179 */ 180 QSTAGE_COORD, 181 QSTAGE_VERT, 182 QSTAGE_FRAG, 183}; 184 185enum quniform_contents { 186 /** 187 * Indicates that a constant 32-bit value is copied from the program's 188 * uniform contents. 189 */ 190 QUNIFORM_CONSTANT, 191 /** 192 * Indicates that the program's uniform contents are used as an index 193 * into the GL uniform storage. 194 */ 195 QUNIFORM_UNIFORM, 196 197 /** @{ 198 * Scaling factors from clip coordinates to relative to the viewport 199 * center. 200 * 201 * This is used by the coordinate and vertex shaders to produce the 202 * 32-bit entry consisting of 2 16-bit fields with 12.4 signed fixed 203 * point offsets from the viewport ccenter. 204 */ 205 QUNIFORM_VIEWPORT_X_SCALE, 206 QUNIFORM_VIEWPORT_Y_SCALE, 207 /** @} */ 208 209 QUNIFORM_VIEWPORT_Z_OFFSET, 210 QUNIFORM_VIEWPORT_Z_SCALE, 211 212 QUNIFORM_USER_CLIP_PLANE, 213 214 /** 215 * A reference to a texture config parameter 0 uniform. 216 * 217 * This is a uniform implicitly loaded with a QPU_W_TMU* write, which 218 * defines texture type, miplevels, and such. It will be found as a 219 * parameter to the first QOP_TEX_[STRB] instruction in a sequence. 220 */ 221 QUNIFORM_TEXTURE_CONFIG_P0, 222 223 /** 224 * A reference to a texture config parameter 1 uniform. 225 * 226 * This is a uniform implicitly loaded with a QPU_W_TMU* write, which 227 * defines texture width, height, filters, and wrap modes. It will be 228 * found as a parameter to the second QOP_TEX_[STRB] instruction in a 229 * sequence. 230 */ 231 QUNIFORM_TEXTURE_CONFIG_P1, 232 233 /** A reference to a texture config parameter 2 cubemap stride uniform */ 234 QUNIFORM_TEXTURE_CONFIG_P2, 235 236 QUNIFORM_TEXTURE_MSAA_ADDR, 237 238 QUNIFORM_UBO_ADDR, 239 240 QUNIFORM_TEXRECT_SCALE_X, 241 QUNIFORM_TEXRECT_SCALE_Y, 242 243 QUNIFORM_TEXTURE_BORDER_COLOR, 244 245 QUNIFORM_BLEND_CONST_COLOR_X, 246 QUNIFORM_BLEND_CONST_COLOR_Y, 247 QUNIFORM_BLEND_CONST_COLOR_Z, 248 QUNIFORM_BLEND_CONST_COLOR_W, 249 QUNIFORM_BLEND_CONST_COLOR_RGBA, 250 QUNIFORM_BLEND_CONST_COLOR_AAAA, 251 252 QUNIFORM_STENCIL, 253 254 QUNIFORM_ALPHA_REF, 255 QUNIFORM_SAMPLE_MASK, 256}; 257 258struct vc4_varying_slot { 259 uint8_t slot; 260 uint8_t swizzle; 261}; 262 263struct vc4_compiler_ubo_range { 264 /** 265 * offset in bytes from the start of the ubo where this range is 266 * uploaded. 267 * 268 * Only set once used is set. 269 */ 270 uint32_t dst_offset; 271 272 /** 273 * offset in bytes from the start of the gallium uniforms where the 274 * data comes from. 275 */ 276 uint32_t src_offset; 277 278 /** size in bytes of this ubo range */ 279 uint32_t size; 280 281 /** 282 * Set if this range is used by the shader for indirect uniforms 283 * access. 284 */ 285 bool used; 286}; 287 288struct vc4_key { 289 struct vc4_uncompiled_shader *shader_state; 290 struct { 291 enum pipe_format format; 292 uint8_t swizzle[4]; 293 union { 294 struct { 295 unsigned compare_mode:1; 296 unsigned compare_func:3; 297 unsigned wrap_s:3; 298 unsigned wrap_t:3; 299 }; 300 struct { 301 uint16_t msaa_width, msaa_height; 302 }; 303 }; 304 } tex[VC4_MAX_TEXTURE_SAMPLERS]; 305 uint8_t ucp_enables; 306}; 307 308struct vc4_fs_key { 309 struct vc4_key base; 310 enum pipe_format color_format; 311 bool depth_enabled; 312 bool stencil_enabled; 313 bool stencil_twoside; 314 bool stencil_full_writemasks; 315 bool is_points; 316 bool is_lines; 317 bool alpha_test; 318 bool point_coord_upper_left; 319 bool light_twoside; 320 bool msaa; 321 bool sample_coverage; 322 bool sample_alpha_to_coverage; 323 bool sample_alpha_to_one; 324 uint8_t alpha_test_func; 325 uint8_t logicop_func; 326 uint32_t point_sprite_mask; 327 328 struct pipe_rt_blend_state blend; 329}; 330 331struct vc4_vs_key { 332 struct vc4_key base; 333 334 /** 335 * This is a proxy for the array of FS input semantics, which is 336 * larger than we would want to put in the key. 337 */ 338 uint64_t compiled_fs_id; 339 340 enum pipe_format attr_formats[8]; 341 bool is_coord; 342 bool per_vertex_point_size; 343 bool clamp_color; 344}; 345 346struct vc4_compile { 347 struct vc4_context *vc4; 348 nir_shader *s; 349 nir_function_impl *impl; 350 struct exec_list *cf_node_list; 351 352 /** 353 * Mapping from nir_register * or nir_ssa_def * to array of struct 354 * qreg for the values. 355 */ 356 struct hash_table *def_ht; 357 358 /* For each temp, the instruction generating its value. */ 359 struct qinst **defs; 360 uint32_t defs_array_size; 361 362 /** 363 * Inputs to the shader, arranged by TGSI declaration order. 364 * 365 * Not all fragment shader QFILE_VARY reads are present in this array. 366 */ 367 struct qreg *inputs; 368 struct qreg *outputs; 369 bool msaa_per_sample_output; 370 struct qreg color_reads[VC4_MAX_SAMPLES]; 371 struct qreg sample_colors[VC4_MAX_SAMPLES]; 372 uint32_t inputs_array_size; 373 uint32_t outputs_array_size; 374 uint32_t uniforms_array_size; 375 376 struct vc4_compiler_ubo_range *ubo_ranges; 377 uint32_t ubo_ranges_array_size; 378 /** Number of uniform areas declared in ubo_ranges. */ 379 uint32_t num_uniform_ranges; 380 /** Number of uniform areas used for indirect addressed loads. */ 381 uint32_t num_ubo_ranges; 382 uint32_t next_ubo_dst_offset; 383 384 struct qreg line_x, point_x, point_y; 385 struct qreg discard; 386 struct qreg payload_FRAG_Z; 387 struct qreg payload_FRAG_W; 388 389 uint8_t vattr_sizes[8]; 390 391 /** 392 * Array of the VARYING_SLOT_* of all FS QFILE_VARY reads. 393 * 394 * This includes those that aren't part of the VPM varyings, like 395 * point/line coordinates. 396 */ 397 struct vc4_varying_slot *input_slots; 398 uint32_t num_input_slots; 399 uint32_t input_slots_array_size; 400 401 /** 402 * An entry per outputs[] in the VS indicating what the VARYING_SLOT_* 403 * of the output is. Used to emit from the VS in the order that the 404 * FS needs. 405 */ 406 struct vc4_varying_slot *output_slots; 407 408 struct pipe_shader_state *shader_state; 409 struct vc4_key *key; 410 struct vc4_fs_key *fs_key; 411 struct vc4_vs_key *vs_key; 412 413 uint32_t *uniform_data; 414 enum quniform_contents *uniform_contents; 415 uint32_t uniform_array_size; 416 uint32_t num_uniforms; 417 uint32_t num_outputs; 418 uint32_t num_texture_samples; 419 uint32_t output_position_index; 420 uint32_t output_color_index; 421 uint32_t output_point_size_index; 422 uint32_t output_sample_mask_index; 423 424 struct qreg undef; 425 enum qstage stage; 426 uint32_t num_temps; 427 struct list_head instructions; 428 429 struct list_head qpu_inst_list; 430 uint64_t *qpu_insts; 431 uint32_t qpu_inst_count; 432 uint32_t qpu_inst_size; 433 uint32_t num_inputs; 434 435 uint32_t program_id; 436 uint32_t variant_id; 437}; 438 439/* Special nir_load_input intrinsic index for loading the current TLB 440 * destination color. 441 */ 442#define VC4_NIR_TLB_COLOR_READ_INPUT 2000000000 443 444#define VC4_NIR_MS_MASK_OUTPUT 2000000000 445 446/* Special offset for nir_load_uniform values to get a QUNIFORM_* 447 * state-dependent value. 448 */ 449#define VC4_NIR_STATE_UNIFORM_OFFSET 1000000000 450 451struct vc4_compile *qir_compile_init(void); 452void qir_compile_destroy(struct vc4_compile *c); 453struct qinst *qir_inst(enum qop op, struct qreg dst, 454 struct qreg src0, struct qreg src1); 455struct qinst *qir_inst4(enum qop op, struct qreg dst, 456 struct qreg a, 457 struct qreg b, 458 struct qreg c, 459 struct qreg d); 460void qir_remove_instruction(struct vc4_compile *c, struct qinst *qinst); 461struct qreg qir_uniform(struct vc4_compile *c, 462 enum quniform_contents contents, 463 uint32_t data); 464void qir_schedule_instructions(struct vc4_compile *c); 465void qir_reorder_uniforms(struct vc4_compile *c); 466 467void qir_emit(struct vc4_compile *c, struct qinst *inst); 468static inline struct qinst * 469qir_emit_nodef(struct vc4_compile *c, struct qinst *inst) 470{ 471 list_addtail(&inst->link, &c->instructions); 472 return inst; 473} 474 475struct qreg qir_get_temp(struct vc4_compile *c); 476int qir_get_op_nsrc(enum qop qop); 477bool qir_reg_equals(struct qreg a, struct qreg b); 478bool qir_has_side_effects(struct vc4_compile *c, struct qinst *inst); 479bool qir_has_side_effect_reads(struct vc4_compile *c, struct qinst *inst); 480bool qir_is_mul(struct qinst *inst); 481bool qir_is_raw_mov(struct qinst *inst); 482bool qir_is_tex(struct qinst *inst); 483bool qir_is_float_input(struct qinst *inst); 484bool qir_depends_on_flags(struct qinst *inst); 485bool qir_writes_r4(struct qinst *inst); 486struct qreg qir_follow_movs(struct vc4_compile *c, struct qreg reg); 487 488void qir_dump(struct vc4_compile *c); 489void qir_dump_inst(struct vc4_compile *c, struct qinst *inst); 490const char *qir_get_stage_name(enum qstage stage); 491 492void qir_validate(struct vc4_compile *c); 493 494void qir_optimize(struct vc4_compile *c); 495bool qir_opt_algebraic(struct vc4_compile *c); 496bool qir_opt_constant_folding(struct vc4_compile *c); 497bool qir_opt_copy_propagation(struct vc4_compile *c); 498bool qir_opt_dead_code(struct vc4_compile *c); 499bool qir_opt_small_immediates(struct vc4_compile *c); 500bool qir_opt_vpm(struct vc4_compile *c); 501void vc4_nir_lower_blend(nir_shader *s, struct vc4_compile *c); 502void vc4_nir_lower_io(nir_shader *s, struct vc4_compile *c); 503nir_ssa_def *vc4_nir_get_state_uniform(struct nir_builder *b, 504 enum quniform_contents contents); 505nir_ssa_def *vc4_nir_get_swizzled_channel(struct nir_builder *b, 506 nir_ssa_def **srcs, int swiz); 507void vc4_nir_lower_txf_ms(nir_shader *s, struct vc4_compile *c); 508void qir_lower_uniforms(struct vc4_compile *c); 509 510uint32_t qpu_schedule_instructions(struct vc4_compile *c); 511 512void qir_SF(struct vc4_compile *c, struct qreg src); 513 514static inline struct qreg 515qir_uniform_ui(struct vc4_compile *c, uint32_t ui) 516{ 517 return qir_uniform(c, QUNIFORM_CONSTANT, ui); 518} 519 520static inline struct qreg 521qir_uniform_f(struct vc4_compile *c, float f) 522{ 523 return qir_uniform(c, QUNIFORM_CONSTANT, fui(f)); 524} 525 526#define QIR_ALU0(name) \ 527static inline struct qreg \ 528qir_##name(struct vc4_compile *c) \ 529{ \ 530 struct qreg t = qir_get_temp(c); \ 531 qir_emit(c, qir_inst(QOP_##name, t, c->undef, c->undef)); \ 532 return t; \ 533} 534 535#define QIR_ALU1(name) \ 536static inline struct qreg \ 537qir_##name(struct vc4_compile *c, struct qreg a) \ 538{ \ 539 struct qreg t = qir_get_temp(c); \ 540 qir_emit(c, qir_inst(QOP_##name, t, a, c->undef)); \ 541 return t; \ 542} \ 543static inline struct qinst * \ 544qir_##name##_dest(struct vc4_compile *c, struct qreg dest, \ 545 struct qreg a) \ 546{ \ 547 if (dest.file == QFILE_TEMP) \ 548 c->defs[dest.index] = NULL; \ 549 return qir_emit_nodef(c, qir_inst(QOP_##name, dest, a, \ 550 c->undef)); \ 551} 552 553#define QIR_ALU2(name) \ 554static inline struct qreg \ 555qir_##name(struct vc4_compile *c, struct qreg a, struct qreg b) \ 556{ \ 557 struct qreg t = qir_get_temp(c); \ 558 qir_emit(c, qir_inst(QOP_##name, t, a, b)); \ 559 return t; \ 560} \ 561static inline void \ 562qir_##name##_dest(struct vc4_compile *c, struct qreg dest, \ 563 struct qreg a, struct qreg b) \ 564{ \ 565 qir_emit_nodef(c, qir_inst(QOP_##name, dest, a, b)); \ 566} 567 568#define QIR_NODST_1(name) \ 569static inline struct qinst * \ 570qir_##name(struct vc4_compile *c, struct qreg a) \ 571{ \ 572 struct qinst *inst = qir_inst(QOP_##name, c->undef, \ 573 a, c->undef); \ 574 qir_emit(c, inst); \ 575 return inst; \ 576} 577 578#define QIR_NODST_2(name) \ 579static inline struct qinst * \ 580qir_##name(struct vc4_compile *c, struct qreg a, struct qreg b) \ 581{ \ 582 struct qinst *inst = qir_inst(QOP_##name, c->undef, \ 583 a, b); \ 584 qir_emit(c, inst); \ 585 return inst; \ 586} 587 588#define QIR_PAYLOAD(name) \ 589static inline struct qreg \ 590qir_##name(struct vc4_compile *c) \ 591{ \ 592 struct qreg *payload = &c->payload_##name; \ 593 if (payload->file != QFILE_NULL) \ 594 return *payload; \ 595 *payload = qir_get_temp(c); \ 596 struct qinst *inst = qir_inst(QOP_##name, *payload, \ 597 c->undef, c->undef); \ 598 list_add(&inst->link, &c->instructions); \ 599 c->defs[payload->index] = inst; \ 600 return *payload; \ 601} 602 603QIR_ALU1(MOV) 604QIR_ALU1(FMOV) 605QIR_ALU1(MMOV) 606QIR_ALU2(FADD) 607QIR_ALU2(FSUB) 608QIR_ALU2(FMUL) 609QIR_ALU2(V8MULD) 610QIR_ALU2(V8MIN) 611QIR_ALU2(V8MAX) 612QIR_ALU2(V8ADDS) 613QIR_ALU2(V8SUBS) 614QIR_ALU2(MUL24) 615QIR_ALU2(FMIN) 616QIR_ALU2(FMAX) 617QIR_ALU2(FMINABS) 618QIR_ALU2(FMAXABS) 619QIR_ALU1(FTOI) 620QIR_ALU1(ITOF) 621 622QIR_ALU2(ADD) 623QIR_ALU2(SUB) 624QIR_ALU2(SHL) 625QIR_ALU2(SHR) 626QIR_ALU2(ASR) 627QIR_ALU2(MIN) 628QIR_ALU2(MAX) 629QIR_ALU2(AND) 630QIR_ALU2(OR) 631QIR_ALU2(XOR) 632QIR_ALU1(NOT) 633 634QIR_ALU1(RCP) 635QIR_ALU1(RSQ) 636QIR_ALU1(EXP2) 637QIR_ALU1(LOG2) 638QIR_ALU1(VARY_ADD_C) 639QIR_NODST_2(TEX_S) 640QIR_NODST_2(TEX_T) 641QIR_NODST_2(TEX_R) 642QIR_NODST_2(TEX_B) 643QIR_NODST_2(TEX_DIRECT) 644QIR_PAYLOAD(FRAG_Z) 645QIR_PAYLOAD(FRAG_W) 646QIR_ALU0(TEX_RESULT) 647QIR_ALU0(TLB_COLOR_READ) 648QIR_NODST_1(MS_MASK) 649 650static inline struct qreg 651qir_SEL(struct vc4_compile *c, uint8_t cond, struct qreg src0, struct qreg src1) 652{ 653 struct qreg t = qir_get_temp(c); 654 struct qinst *a = qir_MOV_dest(c, t, src0); 655 struct qinst *b = qir_MOV_dest(c, t, src1); 656 a->cond = cond; 657 b->cond = cond ^ 1; 658 return t; 659} 660 661static inline struct qreg 662qir_UNPACK_8_F(struct vc4_compile *c, struct qreg src, int i) 663{ 664 struct qreg t = qir_FMOV(c, src); 665 c->defs[t.index]->src[0].pack = QPU_UNPACK_8A + i; 666 return t; 667} 668 669static inline struct qreg 670qir_UNPACK_8_I(struct vc4_compile *c, struct qreg src, int i) 671{ 672 struct qreg t = qir_MOV(c, src); 673 c->defs[t.index]->src[0].pack = QPU_UNPACK_8A + i; 674 return t; 675} 676 677static inline struct qreg 678qir_UNPACK_16_F(struct vc4_compile *c, struct qreg src, int i) 679{ 680 struct qreg t = qir_FMOV(c, src); 681 c->defs[t.index]->src[0].pack = QPU_UNPACK_16A + i; 682 return t; 683} 684 685static inline struct qreg 686qir_UNPACK_16_I(struct vc4_compile *c, struct qreg src, int i) 687{ 688 struct qreg t = qir_MOV(c, src); 689 c->defs[t.index]->src[0].pack = QPU_UNPACK_16A + i; 690 return t; 691} 692 693static inline void 694qir_PACK_8_F(struct vc4_compile *c, struct qreg dest, struct qreg val, int chan) 695{ 696 assert(!dest.pack); 697 dest.pack = QPU_PACK_MUL_8A + chan; 698 qir_emit(c, qir_inst(QOP_MMOV, dest, val, c->undef)); 699 if (dest.file == QFILE_TEMP) 700 c->defs[dest.index] = NULL; 701} 702 703static inline struct qreg 704qir_PACK_8888_F(struct vc4_compile *c, struct qreg val) 705{ 706 struct qreg dest = qir_MMOV(c, val); 707 c->defs[dest.index]->dst.pack = QPU_PACK_MUL_8888; 708 return dest; 709} 710 711static inline struct qreg 712qir_POW(struct vc4_compile *c, struct qreg x, struct qreg y) 713{ 714 return qir_EXP2(c, qir_FMUL(c, 715 y, 716 qir_LOG2(c, x))); 717} 718 719static inline void 720qir_VPM_WRITE(struct vc4_compile *c, struct qreg val) 721{ 722 qir_MOV_dest(c, qir_reg(QFILE_VPM, 0), val); 723} 724 725static inline struct qreg 726qir_LOAD_IMM(struct vc4_compile *c, uint32_t val) 727{ 728 struct qreg t = qir_get_temp(c); 729 qir_emit(c, qir_inst(QOP_LOAD_IMM, t, 730 qir_reg(QFILE_LOAD_IMM, val), c->undef)); 731 return t; 732} 733 734#endif /* VC4_QIR_H */ 735