1/* 2 * Copyright © 2014 Broadcom 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24#ifndef VC4_QPU_H 25#define VC4_QPU_H 26 27#include <stdio.h> 28#include <stdint.h> 29 30#include "util/u_math.h" 31 32#include "vc4_qpu_defines.h" 33 34struct vc4_compile; 35 36struct qpu_reg { 37 enum qpu_mux mux; 38 uint8_t addr; 39}; 40 41static inline struct qpu_reg 42qpu_rn(int n) 43{ 44 struct qpu_reg r = { 45 QPU_MUX_R0 + n, 46 0, 47 }; 48 49 return r; 50} 51 52static inline struct qpu_reg 53qpu_ra(int addr) 54{ 55 struct qpu_reg r = { 56 QPU_MUX_A, 57 addr, 58 }; 59 60 return r; 61} 62 63static inline struct qpu_reg 64qpu_rb(int addr) 65{ 66 struct qpu_reg r = { 67 QPU_MUX_B, 68 addr, 69 }; 70 71 return r; 72} 73 74static inline struct qpu_reg 75qpu_vary() 76{ 77 struct qpu_reg r = { 78 QPU_MUX_A, 79 QPU_R_VARY, 80 }; 81 82 return r; 83} 84 85static inline struct qpu_reg 86qpu_unif() 87{ 88 struct qpu_reg r = { 89 QPU_MUX_A, 90 QPU_R_UNIF, 91 }; 92 93 return r; 94} 95 96static inline struct qpu_reg 97qpu_vrsetup() 98{ 99 return qpu_ra(QPU_W_VPMVCD_SETUP); 100} 101 102static inline struct qpu_reg 103qpu_vwsetup() 104{ 105 return qpu_rb(QPU_W_VPMVCD_SETUP); 106} 107 108static inline struct qpu_reg 109qpu_tlbc() 110{ 111 struct qpu_reg r = { 112 QPU_MUX_A, 113 QPU_W_TLB_COLOR_ALL, 114 }; 115 116 return r; 117} 118 119static inline struct qpu_reg 120qpu_tlbc_ms() 121{ 122 struct qpu_reg r = { 123 QPU_MUX_A, 124 QPU_W_TLB_COLOR_MS, 125 }; 126 127 return r; 128} 129 130static inline struct qpu_reg qpu_r0(void) { return qpu_rn(0); } 131static inline struct qpu_reg qpu_r1(void) { return qpu_rn(1); } 132static inline struct qpu_reg qpu_r2(void) { return qpu_rn(2); } 133static inline struct qpu_reg qpu_r3(void) { return qpu_rn(3); } 134static inline struct qpu_reg qpu_r4(void) { return qpu_rn(4); } 135static inline struct qpu_reg qpu_r5(void) { return qpu_rn(5); } 136 137uint64_t qpu_NOP(void) ATTRIBUTE_CONST; 138uint64_t qpu_a_MOV(struct qpu_reg dst, struct qpu_reg src) ATTRIBUTE_CONST; 139uint64_t qpu_m_MOV(struct qpu_reg dst, struct qpu_reg src) ATTRIBUTE_CONST; 140uint64_t qpu_a_alu2(enum qpu_op_add op, struct qpu_reg dst, 141 struct qpu_reg src0, struct qpu_reg src1) ATTRIBUTE_CONST; 142uint64_t qpu_m_alu2(enum qpu_op_mul op, struct qpu_reg dst, 143 struct qpu_reg src0, struct qpu_reg src1) ATTRIBUTE_CONST; 144uint64_t qpu_merge_inst(uint64_t a, uint64_t b) ATTRIBUTE_CONST; 145uint64_t qpu_load_imm_ui(struct qpu_reg dst, uint32_t val) ATTRIBUTE_CONST; 146uint64_t qpu_load_imm_u2(struct qpu_reg dst, uint32_t val) ATTRIBUTE_CONST; 147uint64_t qpu_load_imm_i2(struct qpu_reg dst, uint32_t val) ATTRIBUTE_CONST; 148uint64_t qpu_branch(uint32_t cond, uint32_t target) ATTRIBUTE_CONST; 149uint64_t qpu_set_sig(uint64_t inst, uint32_t sig) ATTRIBUTE_CONST; 150uint64_t qpu_set_cond_add(uint64_t inst, uint32_t cond) ATTRIBUTE_CONST; 151uint64_t qpu_set_cond_mul(uint64_t inst, uint32_t cond) ATTRIBUTE_CONST; 152uint32_t qpu_encode_small_immediate(uint32_t i) ATTRIBUTE_CONST; 153uint64_t qpu_m_rot(struct qpu_reg dst, struct qpu_reg src, int rot) ATTRIBUTE_CONST; 154 155bool qpu_waddr_is_tlb(uint32_t waddr) ATTRIBUTE_CONST; 156bool qpu_inst_is_tlb(uint64_t inst) ATTRIBUTE_CONST; 157int qpu_num_sf_accesses(uint64_t inst) ATTRIBUTE_CONST; 158void qpu_serialize_one_inst(struct vc4_compile *c, uint64_t inst); 159 160static inline enum qpu_cond 161qpu_cond_complement(enum qpu_cond cond) 162{ 163 return cond ^ 1; 164} 165 166static inline uint64_t 167qpu_load_imm_f(struct qpu_reg dst, float val) 168{ 169 return qpu_load_imm_ui(dst, fui(val)); 170} 171 172#define A_ALU2(op) \ 173static inline uint64_t \ 174qpu_a_##op(struct qpu_reg dst, struct qpu_reg src0, struct qpu_reg src1) \ 175{ \ 176 return qpu_a_alu2(QPU_A_##op, dst, src0, src1); \ 177} 178 179#define M_ALU2(op) \ 180static inline uint64_t \ 181qpu_m_##op(struct qpu_reg dst, struct qpu_reg src0, struct qpu_reg src1) \ 182{ \ 183 return qpu_m_alu2(QPU_M_##op, dst, src0, src1); \ 184} 185 186#define A_ALU1(op) \ 187static inline uint64_t \ 188qpu_a_##op(struct qpu_reg dst, struct qpu_reg src0) \ 189{ \ 190 return qpu_a_alu2(QPU_A_##op, dst, src0, src0); \ 191} 192 193/*A_ALU2(NOP) */ 194A_ALU2(FADD) 195A_ALU2(FSUB) 196A_ALU2(FMIN) 197A_ALU2(FMAX) 198A_ALU2(FMINABS) 199A_ALU2(FMAXABS) 200A_ALU1(FTOI) 201A_ALU1(ITOF) 202A_ALU2(ADD) 203A_ALU2(SUB) 204A_ALU2(SHR) 205A_ALU2(ASR) 206A_ALU2(ROR) 207A_ALU2(SHL) 208A_ALU2(MIN) 209A_ALU2(MAX) 210A_ALU2(AND) 211A_ALU2(OR) 212A_ALU2(XOR) 213A_ALU1(NOT) 214A_ALU1(CLZ) 215A_ALU2(V8ADDS) 216A_ALU2(V8SUBS) 217 218/* M_ALU2(NOP) */ 219M_ALU2(FMUL) 220M_ALU2(MUL24) 221M_ALU2(V8MULD) 222M_ALU2(V8MIN) 223M_ALU2(V8MAX) 224M_ALU2(V8ADDS) 225M_ALU2(V8SUBS) 226 227void 228vc4_qpu_disasm(const uint64_t *instructions, int num_instructions); 229 230void 231vc4_qpu_disasm_pack_mul(FILE *out, uint32_t pack); 232 233void 234vc4_qpu_disasm_pack_a(FILE *out, uint32_t pack); 235 236void 237vc4_qpu_disasm_unpack(FILE *out, uint32_t pack); 238 239void 240vc4_qpu_validate(uint64_t *insts, uint32_t num_inst); 241 242void 243vc4_qpu_disasm_cond(FILE *out, uint32_t cond); 244 245void 246vc4_qpu_disasm_cond_branch(FILE *out, uint32_t cond); 247 248#endif /* VC4_QPU_H */ 249