radeon_drm_winsys.h revision d794072b3e1f27b96aaf2c476fcd5dcc5fd9d445 
1/*
2 * Copyright © 2009 Corbin Simpson
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
14 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
15 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
16 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
17 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
20 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * The above copyright notice and this permission notice (including the
23 * next paragraph) shall be included in all copies or substantial portions
24 * of the Software.
25 */
26/*
27 * Authors:
28 *      Corbin Simpson <MostAwesomeDude@gmail.com>
29 */
30#ifndef RADEON_DRM_WINSYS_H
31#define RADEON_DRM_WINSYS_H
32
33#include "gallium/drivers/radeon/radeon_winsys.h"
34#include "pipebuffer/pb_cache.h"
35#include "util/u_queue.h"
36#include "util/list.h"
37#include <radeon_drm.h>
38
39#ifndef DRM_RADEON_GEM_USERPTR
40
41#define DRM_RADEON_GEM_USERPTR		0x2d
42
43#define RADEON_GEM_USERPTR_READONLY	(1 << 0)
44#define RADEON_GEM_USERPTR_ANONONLY	(1 << 1)
45#define RADEON_GEM_USERPTR_VALIDATE	(1 << 2)
46#define RADEON_GEM_USERPTR_REGISTER	(1 << 3)
47
48struct drm_radeon_gem_userptr {
49       uint64_t                addr;
50       uint64_t                size;
51       uint32_t                flags;
52       uint32_t                handle;
53};
54
55#endif
56
57struct radeon_drm_cs;
58
59enum radeon_generation {
60    DRV_R300,
61    DRV_R600,
62    DRV_SI
63};
64
65struct radeon_drm_winsys {
66    struct radeon_winsys base;
67    struct pipe_reference reference;
68    struct pb_cache bo_cache;
69
70    int fd; /* DRM file descriptor */
71    int num_cs; /* The number of command streams created. */
72    uint64_t allocated_vram;
73    uint64_t allocated_gtt;
74    uint64_t buffer_wait_time; /* time spent in buffer_wait in ns */
75    uint64_t num_cs_flushes;
76
77    enum radeon_generation gen;
78    struct radeon_info info;
79    uint32_t va_start;
80    uint32_t va_unmap_working;
81    uint32_t accel_working2;
82
83    /* List of buffer GEM names. Protected by bo_handles_mutex. */
84    struct util_hash_table *bo_names;
85    /* List of buffer handles. Protectded by bo_handles_mutex. */
86    struct util_hash_table *bo_handles;
87    /* List of buffer virtual memory ranges. Protectded by bo_handles_mutex. */
88    struct util_hash_table *bo_vas;
89    pipe_mutex bo_handles_mutex;
90    pipe_mutex bo_va_mutex;
91
92    uint64_t va_offset;
93    struct list_head va_holes;
94
95    struct radeon_surface_manager *surf_man;
96
97    uint32_t num_cpus;      /* Number of CPUs. */
98
99    struct radeon_drm_cs *hyperz_owner;
100    pipe_mutex hyperz_owner_mutex;
101    struct radeon_drm_cs *cmask_owner;
102    pipe_mutex cmask_owner_mutex;
103
104    /* multithreaded command submission */
105    struct util_queue cs_queue;
106};
107
108static inline struct radeon_drm_winsys *
109radeon_drm_winsys(struct radeon_winsys *base)
110{
111    return (struct radeon_drm_winsys*)base;
112}
113
114void radeon_surface_init_functions(struct radeon_drm_winsys *ws);
115
116#endif
117