blorp.c revision 81be7be11960e3edb6968fd5c8d9475f234aae48 
1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24#include <errno.h>
25
26#include "program/prog_instruction.h"
27
28#include "blorp_priv.h"
29#include "brw_compiler.h"
30#include "brw_nir.h"
31
32void
33blorp_init(struct blorp_context *blorp, void *driver_ctx,
34           struct isl_device *isl_dev)
35{
36   blorp->driver_ctx = driver_ctx;
37   blorp->isl_dev = isl_dev;
38}
39
40void
41blorp_finish(struct blorp_context *blorp)
42{
43   blorp->driver_ctx = NULL;
44}
45
46void
47blorp_batch_init(struct blorp_context *blorp,
48                 struct blorp_batch *batch, void *driver_batch)
49{
50   batch->blorp = blorp;
51   batch->driver_batch = driver_batch;
52}
53
54void
55blorp_batch_finish(struct blorp_batch *batch)
56{
57   batch->blorp = NULL;
58}
59
60void
61brw_blorp_surface_info_init(struct blorp_context *blorp,
62                            struct brw_blorp_surface_info *info,
63                            const struct blorp_surf *surf,
64                            unsigned int level, unsigned int layer,
65                            enum isl_format format, bool is_render_target)
66{
67   info->enabled = true;
68
69   if (format == ISL_FORMAT_UNSUPPORTED)
70      format = surf->surf->format;
71
72   if (format == ISL_FORMAT_R24_UNORM_X8_TYPELESS) {
73      /* Unfortunately, ISL_FORMAT_R24_UNORM_X8_TYPELESS it isn't supported as
74       * a render target, which would prevent us from blitting to 24-bit
75       * depth.  The miptree consists of 32 bits per pixel, arranged as 24-bit
76       * depth values interleaved with 8 "don't care" bits.  Since depth
77       * values don't require any blending, it doesn't matter how we interpret
78       * the bit pattern as long as we copy the right amount of data, so just
79       * map it as 8-bit BGRA.
80       */
81      format = ISL_FORMAT_B8G8R8A8_UNORM;
82   } else if (surf->surf->usage & ISL_SURF_USAGE_STENCIL_BIT) {
83      assert(surf->surf->format == ISL_FORMAT_R8_UINT);
84      /* Prior to Broadwell, we can't render to R8_UINT */
85      if (blorp->isl_dev->info->gen < 8)
86         format = ISL_FORMAT_R8_UNORM;
87   }
88
89   info->surf = *surf->surf;
90   info->addr = surf->addr;
91
92   info->aux_usage = surf->aux_usage;
93   if (info->aux_usage != ISL_AUX_USAGE_NONE) {
94      info->aux_surf = *surf->aux_surf;
95      info->aux_addr = surf->aux_addr;
96   }
97
98   info->clear_color = surf->clear_color;
99
100   info->view = (struct isl_view) {
101      .usage = is_render_target ? ISL_SURF_USAGE_RENDER_TARGET_BIT :
102                                  ISL_SURF_USAGE_TEXTURE_BIT,
103      .format = format,
104      .base_level = level,
105      .levels = 1,
106      .swizzle = ISL_SWIZZLE_IDENTITY,
107   };
108
109   info->view.array_len = MAX2(info->surf.logical_level0_px.depth,
110                               info->surf.logical_level0_px.array_len);
111
112   if (!is_render_target &&
113       (info->surf.dim == ISL_SURF_DIM_3D ||
114        info->surf.msaa_layout == ISL_MSAA_LAYOUT_ARRAY)) {
115      /* 3-D textures don't support base_array layer and neither do 2-D
116       * multisampled textures on IVB so we need to pass it through the
117       * sampler in those cases.  These are also two cases where we are
118       * guaranteed that we won't be doing any funny surface hacks.
119       */
120      info->view.base_array_layer = 0;
121      info->z_offset = layer;
122   } else {
123      info->view.base_array_layer = layer;
124
125      assert(info->view.array_len >= info->view.base_array_layer);
126      info->view.array_len -= info->view.base_array_layer;
127      info->z_offset = 0;
128   }
129
130   /* Sandy Bridge has a limit of a maximum of 512 layers for layered
131    * rendering.
132    */
133   if (is_render_target && blorp->isl_dev->info->gen == 6)
134      info->view.array_len = MIN2(info->view.array_len, 512);
135}
136
137
138void
139blorp_params_init(struct blorp_params *params)
140{
141   memset(params, 0, sizeof(*params));
142   params->num_draw_buffers = 1;
143   params->num_layers = 1;
144}
145
146void
147brw_blorp_init_wm_prog_key(struct brw_wm_prog_key *wm_key)
148{
149   memset(wm_key, 0, sizeof(*wm_key));
150   wm_key->nr_color_regions = 1;
151   for (int i = 0; i < MAX_SAMPLERS; i++)
152      wm_key->tex.swizzles[i] = SWIZZLE_XYZW;
153}
154
155static int
156nir_uniform_type_size(const struct glsl_type *type)
157{
158   /* Only very basic types are allowed */
159   assert(glsl_type_is_vector_or_scalar(type));
160   assert(glsl_get_bit_size(type) == 32);
161
162   return glsl_get_vector_elements(type) * 4;
163}
164
165const unsigned *
166brw_blorp_compile_nir_shader(struct blorp_context *blorp, struct nir_shader *nir,
167                             const struct brw_wm_prog_key *wm_key,
168                             bool use_repclear,
169                             struct brw_blorp_prog_data *prog_data,
170                             unsigned *program_size)
171{
172   const struct brw_compiler *compiler = blorp->compiler;
173
174   void *mem_ctx = ralloc_context(NULL);
175
176   /* Calling brw_preprocess_nir and friends is destructive and, if cloning is
177    * enabled, may end up completely replacing the nir_shader.  Therefore, we
178    * own it and might as well put it in our context for easy cleanup.
179    */
180   ralloc_steal(mem_ctx, nir);
181   nir->options =
182      compiler->glsl_compiler_options[MESA_SHADER_FRAGMENT].NirOptions;
183
184   struct brw_wm_prog_data wm_prog_data;
185   memset(&wm_prog_data, 0, sizeof(wm_prog_data));
186
187   wm_prog_data.base.nr_params = 0;
188   wm_prog_data.base.param = NULL;
189
190   /* BLORP always just uses the first two binding table entries */
191   wm_prog_data.binding_table.render_target_start = BLORP_RENDERBUFFER_BT_INDEX;
192   wm_prog_data.base.binding_table.texture_start = BLORP_TEXTURE_BT_INDEX;
193
194   nir = brw_preprocess_nir(compiler, nir);
195   nir_remove_dead_variables(nir, nir_var_shader_in);
196   nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
197
198   /* Uniforms are required to be lowered before going into compile_fs.  For
199    * BLORP, we'll assume that whoever builds the shader sets the location
200    * they want so we just need to lower them and figure out how many we have
201    * in total.
202    */
203   nir->num_uniforms = 0;
204   nir_foreach_variable(var, &nir->uniforms) {
205      var->data.driver_location = var->data.location;
206      unsigned end = var->data.location + nir_uniform_type_size(var->type);
207      nir->num_uniforms = MAX2(nir->num_uniforms, end);
208   }
209   nir_lower_io(nir, nir_var_uniform, nir_uniform_type_size, 0);
210
211   const unsigned *program =
212      brw_compile_fs(compiler, blorp->driver_ctx, mem_ctx,
213                     wm_key, &wm_prog_data, nir,
214                     NULL, -1, -1, false, use_repclear, program_size, NULL);
215
216   /* Copy the relavent bits of wm_prog_data over into the blorp prog data */
217   prog_data->dispatch_8 = wm_prog_data.dispatch_8;
218   prog_data->dispatch_16 = wm_prog_data.dispatch_16;
219   prog_data->first_curbe_grf_0 = wm_prog_data.base.dispatch_grf_start_reg;
220   prog_data->first_curbe_grf_2 = wm_prog_data.dispatch_grf_start_reg_2;
221   prog_data->ksp_offset_2 = wm_prog_data.prog_offset_2;
222   prog_data->persample_msaa_dispatch = wm_prog_data.persample_dispatch;
223   prog_data->flat_inputs = wm_prog_data.flat_inputs;
224   prog_data->num_varying_inputs = wm_prog_data.num_varying_inputs;
225   prog_data->inputs_read = nir->info.inputs_read;
226
227   assert(wm_prog_data.base.nr_params == 0);
228
229   return program;
230}
231
232void
233blorp_gen6_hiz_op(struct blorp_batch *batch,
234                  struct blorp_surf *surf, unsigned level, unsigned layer,
235                  enum blorp_hiz_op op)
236{
237   struct blorp_params params;
238   blorp_params_init(&params);
239
240   params.hiz_op = op;
241
242   brw_blorp_surface_info_init(batch->blorp, &params.depth, surf, level, layer,
243                               surf->surf->format, true);
244
245   /* Align the rectangle primitive to 8x4 pixels.
246    *
247    * During fast depth clears, the emitted rectangle primitive  must be
248    * aligned to 8x4 pixels.  From the Ivybridge PRM, Vol 2 Part 1 Section
249    * 11.5.3.1 Depth Buffer Clear (and the matching section in the Sandybridge
250    * PRM):
251    *     If Number of Multisamples is NUMSAMPLES_1, the rectangle must be
252    *     aligned to an 8x4 pixel block relative to the upper left corner
253    *     of the depth buffer [...]
254    *
255    * For hiz resolves, the rectangle must also be 8x4 aligned. Item
256    * WaHizAmbiguate8x4Aligned from the Haswell workarounds page and the
257    * Ivybridge simulator require the alignment.
258    *
259    * To be safe, let's just align the rect for all hiz operations and all
260    * hardware generations.
261    *
262    * However, for some miptree slices of a Z24 texture, emitting an 8x4
263    * aligned rectangle that covers the slice may clobber adjacent slices if
264    * we strictly adhered to the texture alignments specified in the PRM.  The
265    * Ivybridge PRM, Section "Alignment Unit Size", states that
266    * SURFACE_STATE.Surface_Horizontal_Alignment should be 4 for Z24 surfaces,
267    * not 8. But commit 1f112cc increased the alignment from 4 to 8, which
268    * prevents the clobbering.
269    */
270   params.x1 = minify(params.depth.surf.logical_level0_px.width,
271                      params.depth.view.base_level);
272   params.y1 = minify(params.depth.surf.logical_level0_px.height,
273                      params.depth.view.base_level);
274   params.x1 = ALIGN(params.x1, 8);
275   params.y1 = ALIGN(params.y1, 4);
276
277   if (params.depth.view.base_level == 0) {
278      /* TODO: What about MSAA? */
279      params.depth.surf.logical_level0_px.width = params.x1;
280      params.depth.surf.logical_level0_px.height = params.y1;
281   }
282
283   params.dst.surf.samples = params.depth.surf.samples;
284   params.dst.surf.logical_level0_px = params.depth.surf.logical_level0_px;
285   params.depth_format = isl_format_get_depth_format(surf->surf->format, false);
286
287   batch->blorp->exec(batch, &params);
288}
289