1/* 2 * Copyright (C) 2009 Maciej Cencora <m.cencora@gmail.com> 3 * 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining 7 * a copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sublicense, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial 16 * portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 19 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 21 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 22 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 23 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 24 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 */ 27 28#include "radeon_common.h" 29#include "r200_context.h" 30#include "r200_blit.h" 31#include "r200_tex.h" 32 33static inline uint32_t cmdpacket0(struct radeon_screen *rscrn, 34 int reg, int count) 35{ 36 if (count) 37 return CP_PACKET0(reg, count - 1); 38 return CP_PACKET2; 39} 40 41/* common formats supported as both textures and render targets */ 42unsigned r200_check_blit(mesa_format mesa_format, uint32_t dst_pitch) 43{ 44 /* XXX others? */ 45 if (_mesa_little_endian()) { 46 switch (mesa_format) { 47 case MESA_FORMAT_B8G8R8A8_UNORM: 48 case MESA_FORMAT_B8G8R8X8_UNORM: 49 case MESA_FORMAT_B5G6R5_UNORM: 50 case MESA_FORMAT_B4G4R4A4_UNORM: 51 case MESA_FORMAT_B5G5R5A1_UNORM: 52 case MESA_FORMAT_A_UNORM8: 53 case MESA_FORMAT_L_UNORM8: 54 case MESA_FORMAT_I_UNORM8: 55 /* swizzled - probably can't happen with the disabled Choose8888TexFormat code */ 56 case MESA_FORMAT_A8B8G8R8_UNORM: 57 case MESA_FORMAT_R8G8B8A8_UNORM: 58 break; 59 default: 60 return 0; 61 } 62 } 63 else { 64 switch (mesa_format) { 65 case MESA_FORMAT_A8R8G8B8_UNORM: 66 case MESA_FORMAT_X8R8G8B8_UNORM: 67 case MESA_FORMAT_R5G6B5_UNORM: 68 case MESA_FORMAT_A4R4G4B4_UNORM: 69 case MESA_FORMAT_A1R5G5B5_UNORM: 70 case MESA_FORMAT_A_UNORM8: 71 case MESA_FORMAT_L_UNORM8: 72 case MESA_FORMAT_I_UNORM8: 73 /* swizzled - probably can't happen with the disabled Choose8888TexFormat code */ 74 case MESA_FORMAT_R8G8B8A8_UNORM: 75 case MESA_FORMAT_A8B8G8R8_UNORM: 76 break; 77 default: 78 return 0; 79 } 80 } 81 82 /* Rendering to small buffer doesn't work. 83 * Looks like a hw limitation. 84 */ 85 if (dst_pitch < 32) 86 return 0; 87 88 /* ??? */ 89 if (_mesa_get_format_bits(mesa_format, GL_DEPTH_BITS) > 0) 90 return 0; 91 92 return 1; 93} 94 95static inline void emit_vtx_state(struct r200_context *r200) 96{ 97 BATCH_LOCALS(&r200->radeon); 98 99 BEGIN_BATCH(14); 100 if (r200->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) { 101 OUT_BATCH_REGVAL(R200_SE_VAP_CNTL_STATUS, 0); 102 } else { 103 OUT_BATCH_REGVAL(R200_SE_VAP_CNTL_STATUS, RADEON_TCL_BYPASS); 104 } 105 OUT_BATCH_REGVAL(R200_SE_VAP_CNTL, (R200_VAP_FORCE_W_TO_ONE | 106 (9 << R200_VAP_VF_MAX_VTX_NUM__SHIFT))); 107 OUT_BATCH_REGVAL(R200_SE_VTX_STATE_CNTL, 0); 108 OUT_BATCH_REGVAL(R200_SE_VTE_CNTL, 0); 109 OUT_BATCH_REGVAL(R200_SE_VTX_FMT_0, R200_VTX_XY); 110 OUT_BATCH_REGVAL(R200_SE_VTX_FMT_1, (2 << R200_VTX_TEX0_COMP_CNT_SHIFT)); 111 OUT_BATCH_REGVAL(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD | 112 RADEON_BFACE_SOLID | 113 RADEON_FFACE_SOLID | 114 RADEON_VTX_PIX_CENTER_OGL | 115 RADEON_ROUND_MODE_ROUND | 116 RADEON_ROUND_PREC_4TH_PIX)); 117 END_BATCH(); 118} 119 120static void inline emit_tx_setup(struct r200_context *r200, 121 mesa_format src_mesa_format, 122 mesa_format dst_mesa_format, 123 struct radeon_bo *bo, 124 intptr_t offset, 125 unsigned width, 126 unsigned height, 127 unsigned pitch) 128{ 129 uint32_t txformat = R200_TXFORMAT_NON_POWER2; 130 BATCH_LOCALS(&r200->radeon); 131 132 assert(width <= 2048); 133 assert(height <= 2048); 134 assert(offset % 32 == 0); 135 136 if (_mesa_little_endian()) { 137 txformat |= tx_table_le[src_mesa_format].format; 138 } 139 else { 140 txformat |= tx_table_be[src_mesa_format].format; 141 } 142 143 if (bo->flags & RADEON_BO_FLAGS_MACRO_TILE) 144 offset |= R200_TXO_MACRO_TILE; 145 if (bo->flags & RADEON_BO_FLAGS_MICRO_TILE) 146 offset |= R200_TXO_MICRO_TILE; 147 148 switch (dst_mesa_format) { 149 /* le */ 150 case MESA_FORMAT_B8G8R8A8_UNORM: 151 case MESA_FORMAT_B8G8R8X8_UNORM: 152 case MESA_FORMAT_B5G6R5_UNORM: 153 case MESA_FORMAT_B4G4R4A4_UNORM: 154 case MESA_FORMAT_B5G5R5A1_UNORM: 155 /* be */ 156 case MESA_FORMAT_A8R8G8B8_UNORM: 157 case MESA_FORMAT_X8R8G8B8_UNORM: 158 case MESA_FORMAT_R5G6B5_UNORM: 159 case MESA_FORMAT_A4R4G4B4_UNORM: 160 case MESA_FORMAT_A1R5G5B5_UNORM: 161 /* little and big */ 162 case MESA_FORMAT_A_UNORM8: 163 case MESA_FORMAT_L_UNORM8: 164 case MESA_FORMAT_I_UNORM8: 165 default: 166 /* no swizzle required */ 167 BEGIN_BATCH(10); 168 OUT_BATCH_REGVAL(RADEON_PP_CNTL, (RADEON_TEX_0_ENABLE | 169 RADEON_TEX_BLEND_0_ENABLE)); 170 OUT_BATCH_REGVAL(R200_PP_TXCBLEND_0, (R200_TXC_ARG_A_ZERO | 171 R200_TXC_ARG_B_ZERO | 172 R200_TXC_ARG_C_R0_COLOR | 173 R200_TXC_OP_MADD)); 174 OUT_BATCH_REGVAL(R200_PP_TXCBLEND2_0, (R200_TXC_CLAMP_0_1 | 175 R200_TXC_OUTPUT_REG_R0)); 176 OUT_BATCH_REGVAL(R200_PP_TXABLEND_0, (R200_TXA_ARG_A_ZERO | 177 R200_TXA_ARG_B_ZERO | 178 R200_TXA_ARG_C_R0_ALPHA | 179 R200_TXA_OP_MADD)); 180 OUT_BATCH_REGVAL(R200_PP_TXABLEND2_0, (R200_TXA_CLAMP_0_1 | 181 R200_TXA_OUTPUT_REG_R0)); 182 END_BATCH(); 183 break; 184 case MESA_FORMAT_A8B8G8R8_UNORM: 185 case MESA_FORMAT_R8G8B8A8_UNORM: 186 if ((dst_mesa_format == MESA_FORMAT_A8B8G8R8_UNORM && _mesa_little_endian()) || 187 (dst_mesa_format == MESA_FORMAT_R8G8B8A8_UNORM && !_mesa_little_endian())) { 188 BEGIN_BATCH(10); 189 OUT_BATCH_REGVAL(RADEON_PP_CNTL, (RADEON_TEX_0_ENABLE | 190 RADEON_TEX_BLEND_0_ENABLE)); 191 OUT_BATCH_REGVAL(R200_PP_TXCBLEND_0, (R200_TXC_ARG_A_ZERO | 192 R200_TXC_ARG_B_ZERO | 193 R200_TXC_ARG_C_R0_COLOR | 194 R200_TXC_OP_MADD)); 195 /* XXX I don't think this can work. This is output rotation, and alpha contains 196 * red, not alpha (we'd write gbrr). */ 197 OUT_BATCH_REGVAL(R200_PP_TXCBLEND2_0, (R200_TXC_CLAMP_0_1 | 198 R200_TXC_OUTPUT_ROTATE_GBA | 199 R200_TXC_OUTPUT_REG_R0)); 200 OUT_BATCH_REGVAL(R200_PP_TXABLEND_0, (R200_TXA_ARG_A_ZERO | 201 R200_TXA_ARG_B_ZERO | 202 R200_TXA_ARG_C_R0_ALPHA | 203 R200_TXA_OP_MADD)); 204 OUT_BATCH_REGVAL(R200_PP_TXABLEND2_0, (R200_TXA_CLAMP_0_1 | 205 (R200_TXA_REPL_RED << R200_TXA_REPL_ARG_C_SHIFT) | 206 R200_TXA_OUTPUT_REG_R0)); 207 END_BATCH(); 208 } 209 else { 210 /* XXX pretty sure could do this with just 2 instead of 4 instructions. 211 * Like so: 212 * 1st: use RGA output rotation, rgb arg replicate b, a arg r, write mask rb. 213 * That's just one instruction in fact but I'm not entirely sure it works 214 * if some of those incoming r0 components are never written (due to mask) 215 * in the shader itself to r0. 216 * In any case this case (and the one above) may not be reachable with 217 * disabled Choose8888TexFormat code. */ 218 BEGIN_BATCH(34); 219 OUT_BATCH_REGVAL(RADEON_PP_CNTL, (RADEON_TEX_0_ENABLE | 220 RADEON_TEX_BLEND_0_ENABLE | 221 RADEON_TEX_BLEND_1_ENABLE | 222 RADEON_TEX_BLEND_2_ENABLE | 223 RADEON_TEX_BLEND_3_ENABLE)); 224 /* r1.r = r0.b */ 225 OUT_BATCH_REGVAL(R200_PP_TXCBLEND_0, (R200_TXC_ARG_A_ZERO | 226 R200_TXC_ARG_B_ZERO | 227 R200_TXC_ARG_C_R0_COLOR | 228 R200_TXC_OP_MADD)); 229 OUT_BATCH_REGVAL(R200_PP_TXCBLEND2_0, (R200_TXC_CLAMP_0_1 | 230 R200_TXC_OUTPUT_MASK_R | 231 (R200_TXC_REPL_BLUE << R200_TXC_REPL_ARG_C_SHIFT) | 232 R200_TXC_OUTPUT_REG_R1)); 233 /* r1.a = r0.a */ 234 OUT_BATCH_REGVAL(R200_PP_TXABLEND_0, (R200_TXA_ARG_A_ZERO | 235 R200_TXA_ARG_B_ZERO | 236 R200_TXA_ARG_C_R0_ALPHA | 237 R200_TXA_OP_MADD)); 238 OUT_BATCH_REGVAL(R200_PP_TXABLEND2_0, (R200_TXA_CLAMP_0_1 | 239 R200_TXA_OUTPUT_REG_R1)); 240 /* r1.g = r0.g */ 241 OUT_BATCH_REGVAL(R200_PP_TXCBLEND_1, (R200_TXC_ARG_A_ZERO | 242 R200_TXC_ARG_B_ZERO | 243 R200_TXC_ARG_C_R0_COLOR | 244 R200_TXC_OP_MADD)); 245 OUT_BATCH_REGVAL(R200_PP_TXCBLEND2_1, (R200_TXC_CLAMP_0_1 | 246 R200_TXC_OUTPUT_MASK_G | 247 (R200_TXC_REPL_GREEN << R200_TXC_REPL_ARG_C_SHIFT) | 248 R200_TXC_OUTPUT_REG_R1)); 249 /* r1.a = r0.a */ 250 OUT_BATCH_REGVAL(R200_PP_TXABLEND_1, (R200_TXA_ARG_A_ZERO | 251 R200_TXA_ARG_B_ZERO | 252 R200_TXA_ARG_C_R0_ALPHA | 253 R200_TXA_OP_MADD)); 254 OUT_BATCH_REGVAL(R200_PP_TXABLEND2_1, (R200_TXA_CLAMP_0_1 | 255 R200_TXA_OUTPUT_REG_R1)); 256 /* r1.b = r0.r */ 257 OUT_BATCH_REGVAL(R200_PP_TXCBLEND_2, (R200_TXC_ARG_A_ZERO | 258 R200_TXC_ARG_B_ZERO | 259 R200_TXC_ARG_C_R0_COLOR | 260 R200_TXC_OP_MADD)); 261 OUT_BATCH_REGVAL(R200_PP_TXCBLEND2_2, (R200_TXC_CLAMP_0_1 | 262 R200_TXC_OUTPUT_MASK_B | 263 (R200_TXC_REPL_RED << R200_TXC_REPL_ARG_C_SHIFT) | 264 R200_TXC_OUTPUT_REG_R1)); 265 /* r1.a = r0.a */ 266 OUT_BATCH_REGVAL(R200_PP_TXABLEND_2, (R200_TXA_ARG_A_ZERO | 267 R200_TXA_ARG_B_ZERO | 268 R200_TXA_ARG_C_R0_ALPHA | 269 R200_TXA_OP_MADD)); 270 OUT_BATCH_REGVAL(R200_PP_TXABLEND2_2, (R200_TXA_CLAMP_0_1 | 271 R200_TXA_OUTPUT_REG_R1)); 272 /* r0.rgb = r1.rgb */ 273 OUT_BATCH_REGVAL(R200_PP_TXCBLEND_3, (R200_TXC_ARG_A_ZERO | 274 R200_TXC_ARG_B_ZERO | 275 R200_TXC_ARG_C_R1_COLOR | 276 R200_TXC_OP_MADD)); 277 OUT_BATCH_REGVAL(R200_PP_TXCBLEND2_3, (R200_TXC_CLAMP_0_1 | 278 R200_TXC_OUTPUT_REG_R0)); 279 /* r0.a = r1.a */ 280 OUT_BATCH_REGVAL(R200_PP_TXABLEND_3, (R200_TXA_ARG_A_ZERO | 281 R200_TXA_ARG_B_ZERO | 282 R200_TXA_ARG_C_R1_ALPHA | 283 R200_TXA_OP_MADD)); 284 OUT_BATCH_REGVAL(R200_PP_TXABLEND2_3, (R200_TXA_CLAMP_0_1 | 285 R200_TXA_OUTPUT_REG_R0)); 286 END_BATCH(); 287 } 288 break; 289 } 290 291 BEGIN_BATCH(18); 292 OUT_BATCH_REGVAL(R200_PP_CNTL_X, 0); 293 OUT_BATCH_REGVAL(R200_PP_TXMULTI_CTL_0, 0); 294 OUT_BATCH_REGVAL(R200_PP_TXFILTER_0, (R200_CLAMP_S_CLAMP_LAST | 295 R200_CLAMP_T_CLAMP_LAST | 296 R200_MAG_FILTER_NEAREST | 297 R200_MIN_FILTER_NEAREST)); 298 OUT_BATCH_REGVAL(R200_PP_TXFORMAT_0, txformat); 299 OUT_BATCH_REGVAL(R200_PP_TXFORMAT_X_0, 0); 300 OUT_BATCH_REGVAL(R200_PP_TXSIZE_0, ((width - 1) | 301 ((height - 1) << RADEON_TEX_VSIZE_SHIFT))); 302 OUT_BATCH_REGVAL(R200_PP_TXPITCH_0, pitch * _mesa_get_format_bytes(src_mesa_format) - 32); 303 304 OUT_BATCH_REGSEQ(R200_PP_TXOFFSET_0, 1); 305 OUT_BATCH_RELOC(offset, bo, offset, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); 306 307 END_BATCH(); 308} 309 310static inline void emit_cb_setup(struct r200_context *r200, 311 struct radeon_bo *bo, 312 intptr_t offset, 313 mesa_format mesa_format, 314 unsigned pitch, 315 unsigned width, 316 unsigned height) 317{ 318 uint32_t dst_pitch = pitch; 319 uint32_t dst_format = 0; 320 BATCH_LOCALS(&r200->radeon); 321 322 switch (mesa_format) { 323 /* The first of each pair is for little, the second for big endian */ 324 case MESA_FORMAT_B8G8R8A8_UNORM: 325 case MESA_FORMAT_A8R8G8B8_UNORM: 326 case MESA_FORMAT_B8G8R8X8_UNORM: 327 case MESA_FORMAT_X8R8G8B8_UNORM: 328 /* These two are valid both for little and big endian (swizzled) */ 329 case MESA_FORMAT_A8B8G8R8_UNORM: 330 case MESA_FORMAT_R8G8B8A8_UNORM: 331 dst_format = RADEON_COLOR_FORMAT_ARGB8888; 332 break; 333 case MESA_FORMAT_B5G6R5_UNORM: 334 case MESA_FORMAT_R5G6B5_UNORM: 335 dst_format = RADEON_COLOR_FORMAT_RGB565; 336 break; 337 case MESA_FORMAT_B4G4R4A4_UNORM: 338 case MESA_FORMAT_A4R4G4B4_UNORM: 339 dst_format = RADEON_COLOR_FORMAT_ARGB4444; 340 break; 341 case MESA_FORMAT_B5G5R5A1_UNORM: 342 case MESA_FORMAT_A1R5G5B5_UNORM: 343 dst_format = RADEON_COLOR_FORMAT_ARGB1555; 344 break; 345 case MESA_FORMAT_A_UNORM8: 346 case MESA_FORMAT_L_UNORM8: 347 case MESA_FORMAT_I_UNORM8: 348 dst_format = RADEON_COLOR_FORMAT_RGB8; 349 break; 350 default: 351 break; 352 } 353 354 if (bo->flags & RADEON_BO_FLAGS_MACRO_TILE) 355 dst_pitch |= R200_COLOR_TILE_ENABLE; 356 if (bo->flags & RADEON_BO_FLAGS_MICRO_TILE) 357 dst_pitch |= R200_COLOR_MICROTILE_ENABLE; 358 359 BEGIN_BATCH(22); 360 OUT_BATCH_REGVAL(R200_RE_AUX_SCISSOR_CNTL, 0); 361 OUT_BATCH_REGVAL(R200_RE_CNTL, 0); 362 OUT_BATCH_REGVAL(RADEON_RE_TOP_LEFT, 0); 363 OUT_BATCH_REGVAL(RADEON_RE_WIDTH_HEIGHT, (((width - 1) << RADEON_RE_WIDTH_SHIFT) | 364 ((height - 1) << RADEON_RE_HEIGHT_SHIFT))); 365 OUT_BATCH_REGVAL(RADEON_RB3D_PLANEMASK, 0xffffffff); 366 OUT_BATCH_REGVAL(RADEON_RB3D_BLENDCNTL, RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ZERO); 367 OUT_BATCH_REGVAL(RADEON_RB3D_CNTL, dst_format); 368 369 OUT_BATCH_REGSEQ(RADEON_RB3D_COLOROFFSET, 1); 370 OUT_BATCH_RELOC(offset, bo, offset, 0, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0); 371 OUT_BATCH_REGSEQ(RADEON_RB3D_COLORPITCH, 1); 372 OUT_BATCH_RELOC(dst_pitch, bo, dst_pitch, 0, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0); 373 374 END_BATCH(); 375} 376 377static GLboolean validate_buffers(struct r200_context *r200, 378 struct radeon_bo *src_bo, 379 struct radeon_bo *dst_bo) 380{ 381 int ret; 382 383 radeon_cs_space_reset_bos(r200->radeon.cmdbuf.cs); 384 385 ret = radeon_cs_space_check_with_bo(r200->radeon.cmdbuf.cs, 386 src_bo, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0); 387 if (ret) 388 return GL_FALSE; 389 390 ret = radeon_cs_space_check_with_bo(r200->radeon.cmdbuf.cs, 391 dst_bo, 0, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT); 392 if (ret) 393 return GL_FALSE; 394 395 return GL_TRUE; 396} 397 398/** 399 * Calculate texcoords for given image region. 400 * Output values are [minx, maxx, miny, maxy] 401 */ 402static inline void calc_tex_coords(float img_width, float img_height, 403 float x, float y, 404 float reg_width, float reg_height, 405 unsigned flip_y, float *buf) 406{ 407 buf[0] = x / img_width; 408 buf[1] = buf[0] + reg_width / img_width; 409 buf[2] = y / img_height; 410 buf[3] = buf[2] + reg_height / img_height; 411 if (flip_y) 412 { 413 buf[2] = 1.0 - buf[2]; 414 buf[3] = 1.0 - buf[3]; 415 } 416} 417 418static inline void emit_draw_packet(struct r200_context *r200, 419 unsigned src_width, unsigned src_height, 420 unsigned src_x_offset, unsigned src_y_offset, 421 unsigned dst_x_offset, unsigned dst_y_offset, 422 unsigned reg_width, unsigned reg_height, 423 unsigned flip_y) 424{ 425 float texcoords[4]; 426 float verts[12]; 427 BATCH_LOCALS(&r200->radeon); 428 429 calc_tex_coords(src_width, src_height, 430 src_x_offset, src_y_offset, 431 reg_width, reg_height, 432 flip_y, texcoords); 433 434 verts[0] = dst_x_offset; 435 verts[1] = dst_y_offset + reg_height; 436 verts[2] = texcoords[0]; 437 verts[3] = texcoords[3]; 438 439 verts[4] = dst_x_offset + reg_width; 440 verts[5] = dst_y_offset + reg_height; 441 verts[6] = texcoords[1]; 442 verts[7] = texcoords[3]; 443 444 verts[8] = dst_x_offset + reg_width; 445 verts[9] = dst_y_offset; 446 verts[10] = texcoords[1]; 447 verts[11] = texcoords[2]; 448 449 BEGIN_BATCH(14); 450 OUT_BATCH(R200_CP_CMD_3D_DRAW_IMMD_2 | (12 << 16)); 451 OUT_BATCH(RADEON_CP_VC_CNTL_PRIM_WALK_RING | 452 RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST | 453 (3 << 16)); 454 OUT_BATCH_TABLE(verts, 12); 455 END_BATCH(); 456} 457 458/** 459 * Copy a region of [@a width x @a height] pixels from source buffer 460 * to destination buffer. 461 * @param[in] r200 r200 context 462 * @param[in] src_bo source radeon buffer object 463 * @param[in] src_offset offset of the source image in the @a src_bo 464 * @param[in] src_mesaformat source image format 465 * @param[in] src_pitch aligned source image width 466 * @param[in] src_width source image width 467 * @param[in] src_height source image height 468 * @param[in] src_x_offset x offset in the source image 469 * @param[in] src_y_offset y offset in the source image 470 * @param[in] dst_bo destination radeon buffer object 471 * @param[in] dst_offset offset of the destination image in the @a dst_bo 472 * @param[in] dst_mesaformat destination image format 473 * @param[in] dst_pitch aligned destination image width 474 * @param[in] dst_width destination image width 475 * @param[in] dst_height destination image height 476 * @param[in] dst_x_offset x offset in the destination image 477 * @param[in] dst_y_offset y offset in the destination image 478 * @param[in] width region width 479 * @param[in] height region height 480 * @param[in] flip_y set if y coords of the source image need to be flipped 481 */ 482unsigned r200_blit(struct gl_context *ctx, 483 struct radeon_bo *src_bo, 484 intptr_t src_offset, 485 mesa_format src_mesaformat, 486 unsigned src_pitch, 487 unsigned src_width, 488 unsigned src_height, 489 unsigned src_x_offset, 490 unsigned src_y_offset, 491 struct radeon_bo *dst_bo, 492 intptr_t dst_offset, 493 mesa_format dst_mesaformat, 494 unsigned dst_pitch, 495 unsigned dst_width, 496 unsigned dst_height, 497 unsigned dst_x_offset, 498 unsigned dst_y_offset, 499 unsigned reg_width, 500 unsigned reg_height, 501 unsigned flip_y) 502{ 503 struct r200_context *r200 = R200_CONTEXT(ctx); 504 505 if (!r200_check_blit(dst_mesaformat, dst_pitch)) 506 return GL_FALSE; 507 508 /* Make sure that colorbuffer has even width - hw limitation */ 509 if (dst_pitch % 2 > 0) 510 ++dst_pitch; 511 512 /* Need to clamp the region size to make sure 513 * we don't read outside of the source buffer 514 * or write outside of the destination buffer. 515 */ 516 if (reg_width + src_x_offset > src_width) 517 reg_width = src_width - src_x_offset; 518 if (reg_height + src_y_offset > src_height) 519 reg_height = src_height - src_y_offset; 520 if (reg_width + dst_x_offset > dst_width) 521 reg_width = dst_width - dst_x_offset; 522 if (reg_height + dst_y_offset > dst_height) 523 reg_height = dst_height - dst_y_offset; 524 525 if (src_bo == dst_bo) { 526 return GL_FALSE; 527 } 528 529 if (src_offset % 32 || dst_offset % 32) { 530 return GL_FALSE; 531 } 532 533 if (0) { 534 fprintf(stderr, "src: size [%d x %d], pitch %d, " 535 "offset [%d x %d], format %s, bo %p\n", 536 src_width, src_height, src_pitch, 537 src_x_offset, src_y_offset, 538 _mesa_get_format_name(src_mesaformat), 539 src_bo); 540 fprintf(stderr, "dst: pitch %d, offset[%d x %d], format %s, bo %p\n", 541 dst_pitch, dst_x_offset, dst_y_offset, 542 _mesa_get_format_name(dst_mesaformat), dst_bo); 543 fprintf(stderr, "region: %d x %d\n", reg_width, reg_height); 544 } 545 546 /* Flush is needed to make sure that source buffer has correct data */ 547 radeonFlush(&r200->radeon.glCtx); 548 549 rcommonEnsureCmdBufSpace(&r200->radeon, 102, __func__); 550 551 if (!validate_buffers(r200, src_bo, dst_bo)) 552 return GL_FALSE; 553 554 /* 14 */ 555 emit_vtx_state(r200); 556 /* 52 */ 557 emit_tx_setup(r200, src_mesaformat, dst_mesaformat, src_bo, src_offset, src_width, src_height, src_pitch); 558 /* 22 */ 559 emit_cb_setup(r200, dst_bo, dst_offset, dst_mesaformat, dst_pitch, dst_width, dst_height); 560 /* 14 */ 561 emit_draw_packet(r200, src_width, src_height, 562 src_x_offset, src_y_offset, 563 dst_x_offset, dst_y_offset, 564 reg_width, reg_height, 565 flip_y); 566 567 radeonFlush(ctx); 568 569 /* We submitted those packets outside our state atom mechanism. Thus 570 * make sure the atoms are resubmitted the next time. */ 571 r200->hw.cst.dirty = GL_TRUE; 572 r200->hw.ctx.dirty = GL_TRUE; 573 r200->hw.vap.dirty = GL_TRUE; 574 r200->hw.msk.dirty = GL_TRUE; 575 r200->hw.pix[0].dirty = GL_TRUE; 576 r200->hw.pix[1].dirty = GL_TRUE; 577 r200->hw.pix[2].dirty = GL_TRUE; 578 r200->hw.pix[3].dirty = GL_TRUE; 579 r200->hw.sci.dirty = GL_TRUE; 580 r200->hw.set.dirty = GL_TRUE; 581 r200->hw.tex[0].dirty = GL_TRUE; 582 r200->hw.vte.dirty = GL_TRUE; 583 r200->hw.vtx.dirty = GL_TRUE; 584 585 return GL_TRUE; 586} 587