r200_context.c revision 083f66fdd6451648fe355b64b02b29a6a4389f0d 
1/*
2Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
3
4The Weather Channel (TM) funded Tungsten Graphics to develop the
5initial release of the Radeon 8500 driver under the XFree86 license.
6This notice must be preserved.
7
8Permission is hereby granted, free of charge, to any person obtaining
9a copy of this software and associated documentation files (the
10"Software"), to deal in the Software without restriction, including
11without limitation the rights to use, copy, modify, merge, publish,
12distribute, sublicense, and/or sell copies of the Software, and to
13permit persons to whom the Software is furnished to do so, subject to
14the following conditions:
15
16The above copyright notice and this permission notice (including the
17next paragraph) shall be included in all copies or substantial
18portions of the Software.
19
20THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27
28**************************************************************************/
29
30/*
31 * Authors:
32 *   Keith Whitwell <keith@tungstengraphics.com>
33 */
34
35#include <stdbool.h>
36#include "main/glheader.h"
37#include "main/api_arrayelt.h"
38#include "main/api_exec.h"
39#include "main/context.h"
40#include "main/simple_list.h"
41#include "main/imports.h"
42#include "main/extensions.h"
43#include "main/version.h"
44#include "main/vtxfmt.h"
45
46#include "swrast/swrast.h"
47#include "swrast_setup/swrast_setup.h"
48#include "vbo/vbo.h"
49
50#include "tnl/tnl.h"
51#include "tnl/t_pipeline.h"
52
53#include "drivers/common/driverfuncs.h"
54
55#include "r200_context.h"
56#include "r200_ioctl.h"
57#include "r200_state.h"
58#include "r200_tex.h"
59#include "r200_swtcl.h"
60#include "r200_tcl.h"
61#include "r200_vertprog.h"
62#include "radeon_queryobj.h"
63#include "r200_blit.h"
64#include "radeon_fog.h"
65
66#include "radeon_span.h"
67
68#include "utils.h"
69#include "xmlpool.h" /* for symbolic values of enum-type options */
70
71/* Return various strings for glGetString().
72 */
73static const GLubyte *r200GetString( struct gl_context *ctx, GLenum name )
74{
75   r200ContextPtr rmesa = R200_CONTEXT(ctx);
76   static char buffer[128];
77   unsigned   offset;
78   GLuint agp_mode = (rmesa->radeon.radeonScreen->card_type == RADEON_CARD_PCI)? 0 :
79      rmesa->radeon.radeonScreen->AGPMode;
80
81   switch ( name ) {
82   case GL_VENDOR:
83      return (GLubyte *)"Tungsten Graphics, Inc.";
84
85   case GL_RENDERER:
86      offset = driGetRendererString( buffer, "R200", agp_mode );
87
88      sprintf( & buffer[ offset ], " %sTCL",
89	       !(rmesa->radeon.TclFallback & R200_TCL_FALLBACK_TCL_DISABLE)
90	       ? "" : "NO-" );
91
92      return (GLubyte *)buffer;
93
94   default:
95      return NULL;
96   }
97}
98
99
100extern const struct tnl_pipeline_stage _r200_render_stage;
101extern const struct tnl_pipeline_stage _r200_tcl_stage;
102
103static const struct tnl_pipeline_stage *r200_pipeline[] = {
104
105   /* Try and go straight to t&l
106    */
107   &_r200_tcl_stage,
108
109   /* Catch any t&l fallbacks
110    */
111   &_tnl_vertex_transform_stage,
112   &_tnl_normal_transform_stage,
113   &_tnl_lighting_stage,
114   &_tnl_fog_coordinate_stage,
115   &_tnl_texgen_stage,
116   &_tnl_texture_transform_stage,
117   &_tnl_point_attenuation_stage,
118   &_tnl_vertex_program_stage,
119   /* Try again to go to tcl?
120    *     - no good for asymmetric-twoside (do with multipass)
121    *     - no good for asymmetric-unfilled (do with multipass)
122    *     - good for material
123    *     - good for texgen
124    *     - need to manipulate a bit of state
125    *
126    * - worth it/not worth it?
127    */
128
129   /* Else do them here.
130    */
131/*    &_r200_render_stage,  */ /* FIXME: bugs with ut2003 */
132   &_tnl_render_stage,		/* FALLBACK:  */
133   NULL,
134};
135
136
137
138/* Initialize the driver's misc functions.
139 */
140static void r200InitDriverFuncs( struct dd_function_table *functions )
141{
142    functions->GetString		= r200GetString;
143}
144
145
146static void r200_get_lock(radeonContextPtr radeon)
147{
148   r200ContextPtr rmesa = (r200ContextPtr)radeon;
149   drm_radeon_sarea_t *sarea = radeon->sarea;
150
151   R200_STATECHANGE( rmesa, ctx );
152   if (rmesa->radeon.sarea->tiling_enabled) {
153      rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= R200_COLOR_TILE_ENABLE;
154   }
155   else rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] &= ~R200_COLOR_TILE_ENABLE;
156
157   if ( sarea->ctx_owner != rmesa->radeon.dri.hwContext ) {
158      sarea->ctx_owner = rmesa->radeon.dri.hwContext;
159   }
160
161}
162
163static void r200_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmesa)
164{
165}
166
167static void r200_emit_query_finish(radeonContextPtr radeon)
168{
169   BATCH_LOCALS(radeon);
170   struct radeon_query_object *query = radeon->query.current;
171
172   BEGIN_BATCH_NO_AUTOSTATE(4);
173   OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZPASS_ADDR, 0));
174   OUT_BATCH_RELOC(0, query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
175   END_BATCH();
176   query->curr_offset += sizeof(uint32_t);
177   assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE);
178   query->emitted_begin = GL_FALSE;
179}
180
181static void r200_init_vtbl(radeonContextPtr radeon)
182{
183   radeon->vtbl.get_lock = r200_get_lock;
184   radeon->vtbl.update_viewport_offset = r200UpdateViewportOffset;
185   radeon->vtbl.emit_cs_header = r200_vtbl_emit_cs_header;
186   radeon->vtbl.swtcl_flush = r200_swtcl_flush;
187   radeon->vtbl.fallback = r200Fallback;
188   radeon->vtbl.update_scissor = r200_vtbl_update_scissor;
189   radeon->vtbl.emit_query_finish = r200_emit_query_finish;
190   radeon->vtbl.check_blit = r200_check_blit;
191   radeon->vtbl.blit = r200_blit;
192   radeon->vtbl.is_format_renderable = radeonIsFormatRenderable;
193}
194
195
196/* Create the device specific rendering context.
197 */
198GLboolean r200CreateContext( gl_api api,
199			     const struct gl_config *glVisual,
200			     __DRIcontext *driContextPriv,
201			     unsigned major_version,
202			     unsigned minor_version,
203			     uint32_t flags,
204			     unsigned *error,
205			     void *sharedContextPrivate)
206{
207   __DRIscreen *sPriv = driContextPriv->driScreenPriv;
208   radeonScreenPtr screen = (radeonScreenPtr)(sPriv->driverPrivate);
209   struct dd_function_table functions;
210   r200ContextPtr rmesa;
211   struct gl_context *ctx;
212   int i;
213   int tcl_mode;
214
215   /* Flag filtering is handled in dri2CreateContextAttribs.
216    */
217   (void) flags;
218
219   assert(glVisual);
220   assert(driContextPriv);
221   assert(screen);
222
223   /* Allocate the R200 context */
224   rmesa = calloc(1, sizeof(*rmesa));
225   if ( !rmesa ) {
226      *error = __DRI_CTX_ERROR_NO_MEMORY;
227      return GL_FALSE;
228   }
229
230   rmesa->radeon.radeonScreen = screen;
231   r200_init_vtbl(&rmesa->radeon);
232   /* init exp fog table data */
233   radeonInitStaticFogData();
234
235   /* Parse configuration files.
236    * Do this here so that initialMaxAnisotropy is set before we create
237    * the default textures.
238    */
239   driParseConfigFiles (&rmesa->radeon.optionCache, &screen->optionCache,
240			screen->driScreen->myNum, "r200");
241   rmesa->radeon.initialMaxAnisotropy = driQueryOptionf(&rmesa->radeon.optionCache,
242							"def_max_anisotropy");
243
244   if ( sPriv->drm_version.major == 1
245       && driQueryOptionb( &rmesa->radeon.optionCache, "hyperz" ) ) {
246      if ( sPriv->drm_version.minor < 13 )
247	 fprintf( stderr, "DRM version 1.%d too old to support HyperZ, "
248			  "disabling.\n", sPriv->drm_version.minor );
249      else
250	 rmesa->using_hyperz = GL_TRUE;
251   }
252
253   if ( sPriv->drm_version.minor >= 15 )
254      rmesa->texmicrotile = GL_TRUE;
255
256   /* Init default driver functions then plug in our R200-specific functions
257    * (the texture functions are especially important)
258    */
259   _mesa_init_driver_functions(&functions);
260   r200InitDriverFuncs(&functions);
261   r200InitIoctlFuncs(&functions);
262   r200InitStateFuncs(&rmesa->radeon, &functions);
263   r200InitTextureFuncs(&rmesa->radeon, &functions);
264   r200InitShaderFuncs(&functions);
265   radeonInitQueryObjFunctions(&functions);
266
267   if (!radeonInitContext(&rmesa->radeon, &functions,
268			  glVisual, driContextPriv,
269			  sharedContextPrivate)) {
270     free(rmesa);
271     *error = __DRI_CTX_ERROR_NO_MEMORY;
272     return GL_FALSE;
273   }
274
275   rmesa->radeon.swtcl.RenderIndex = ~0;
276   rmesa->radeon.hw.all_dirty = 1;
277
278   ctx = &rmesa->radeon.glCtx;
279   /* Initialize the software rasterizer and helper modules.
280    */
281   _swrast_CreateContext( ctx );
282   _vbo_CreateContext( ctx );
283   _tnl_CreateContext( ctx );
284   _swsetup_CreateContext( ctx );
285   _ae_create_context( ctx );
286
287   ctx->Const.MaxTextureUnits = driQueryOptioni (&rmesa->radeon.optionCache,
288						 "texture_units");
289   ctx->Const.FragmentProgram.MaxTextureImageUnits = ctx->Const.MaxTextureUnits;
290   ctx->Const.MaxTextureCoordUnits = ctx->Const.MaxTextureUnits;
291
292   ctx->Const.MaxCombinedTextureImageUnits = ctx->Const.MaxTextureUnits;
293
294   ctx->Const.StripTextureBorder = GL_TRUE;
295
296   /* FIXME: When no memory manager is available we should set this
297    * to some reasonable value based on texture memory pool size */
298   ctx->Const.MaxTextureLevels = 12;
299   ctx->Const.Max3DTextureLevels = 9;
300   ctx->Const.MaxCubeTextureLevels = 12;
301   ctx->Const.MaxTextureRectSize = 2048;
302   ctx->Const.MaxRenderbufferSize = 2048;
303
304   ctx->Const.MaxTextureMaxAnisotropy = 16.0;
305
306   /* No wide AA points.
307    */
308   ctx->Const.MinPointSize = 1.0;
309   ctx->Const.MinPointSizeAA = 1.0;
310   ctx->Const.MaxPointSizeAA = 1.0;
311   ctx->Const.PointSizeGranularity = 0.0625;
312   ctx->Const.MaxPointSize = 2047.0;
313
314   /* mesa initialization problem - _mesa_init_point was already called */
315   ctx->Point.MaxSize = ctx->Const.MaxPointSize;
316
317   ctx->Const.MinLineWidth = 1.0;
318   ctx->Const.MinLineWidthAA = 1.0;
319   ctx->Const.MaxLineWidth = 10.0;
320   ctx->Const.MaxLineWidthAA = 10.0;
321   ctx->Const.LineWidthGranularity = 0.0625;
322
323   ctx->Const.VertexProgram.MaxNativeInstructions = R200_VSF_MAX_INST;
324   ctx->Const.VertexProgram.MaxNativeAttribs = 12;
325   ctx->Const.VertexProgram.MaxNativeTemps = R200_VSF_MAX_TEMPS;
326   ctx->Const.VertexProgram.MaxNativeParameters = R200_VSF_MAX_PARAM;
327   ctx->Const.VertexProgram.MaxNativeAddressRegs = 1;
328
329   ctx->Const.MaxDrawBuffers = 1;
330   ctx->Const.MaxColorAttachments = 1;
331
332   ctx->ShaderCompilerOptions[MESA_SHADER_VERTEX].PreferDP4 = GL_TRUE;
333
334   /* Install the customized pipeline:
335    */
336   _tnl_destroy_pipeline( ctx );
337   _tnl_install_pipeline( ctx, r200_pipeline );
338
339   /* Try and keep materials and vertices separate:
340    */
341/*    _tnl_isolate_materials( ctx, GL_TRUE ); */
342
343
344   /* Configure swrast and TNL to match hardware characteristics:
345    */
346   _swrast_allow_pixel_fog( ctx, GL_FALSE );
347   _swrast_allow_vertex_fog( ctx, GL_TRUE );
348   _tnl_allow_pixel_fog( ctx, GL_FALSE );
349   _tnl_allow_vertex_fog( ctx, GL_TRUE );
350
351
352   for ( i = 0 ; i < R200_MAX_TEXTURE_UNITS ; i++ ) {
353      _math_matrix_ctr( &rmesa->TexGenMatrix[i] );
354      _math_matrix_set_identity( &rmesa->TexGenMatrix[i] );
355   }
356   _math_matrix_ctr( &rmesa->tmpmat );
357   _math_matrix_set_identity( &rmesa->tmpmat );
358
359   ctx->Extensions.ARB_half_float_pixel = true;
360   ctx->Extensions.ARB_occlusion_query = true;
361   ctx->Extensions.ARB_texture_border_clamp = true;
362   ctx->Extensions.ARB_texture_env_combine = true;
363   ctx->Extensions.ARB_texture_env_dot3 = true;
364   ctx->Extensions.ARB_texture_env_crossbar = true;
365   ctx->Extensions.EXT_blend_color = true;
366   ctx->Extensions.EXT_blend_minmax = true;
367   ctx->Extensions.EXT_packed_depth_stencil = true;
368   ctx->Extensions.EXT_texture_env_dot3 = true;
369   ctx->Extensions.EXT_texture_filter_anisotropic = true;
370   ctx->Extensions.EXT_texture_mirror_clamp = true;
371   ctx->Extensions.ATI_texture_env_combine3 = true;
372   ctx->Extensions.ATI_texture_mirror_once = true;
373   ctx->Extensions.MESA_pack_invert = true;
374   ctx->Extensions.NV_texture_rectangle = true;
375   ctx->Extensions.OES_EGL_image = true;
376   ctx->Extensions.ARB_occlusion_query = true;
377
378   if (!(rmesa->radeon.radeonScreen->chip_flags & R200_CHIPSET_YCBCR_BROKEN)) {
379     /* yuv textures don't work with some chips - R200 / rv280 okay so far
380	others get the bit ordering right but don't actually do YUV-RGB conversion */
381      ctx->Extensions.MESA_ycbcr_texture = true;
382   }
383   if (rmesa->radeon.glCtx.Mesa_DXTn) {
384      ctx->Extensions.EXT_texture_compression_s3tc = true;
385      ctx->Extensions.ANGLE_texture_compression_dxt = true;
386   }
387   else if (driQueryOptionb (&rmesa->radeon.optionCache, "force_s3tc_enable")) {
388      ctx->Extensions.EXT_texture_compression_s3tc = true;
389      ctx->Extensions.ANGLE_texture_compression_dxt = true;
390   }
391
392   ctx->Extensions.ARB_texture_cube_map = true;
393
394   ctx->Extensions.EXT_blend_equation_separate = true;
395   ctx->Extensions.EXT_blend_func_separate = true;
396
397   ctx->Extensions.ARB_vertex_program = true;
398   ctx->Extensions.EXT_gpu_program_parameters = true;
399
400   ctx->Extensions.ATI_fragment_shader = (ctx->Const.MaxTextureUnits == 6);
401
402   ctx->Extensions.ARB_point_sprite = true;
403   ctx->Extensions.EXT_point_parameters = true;
404
405#if 0
406   r200InitDriverFuncs( ctx );
407   r200InitIoctlFuncs( ctx );
408   r200InitStateFuncs( ctx );
409   r200InitTextureFuncs( ctx );
410#endif
411   /* plug in a few more device driver functions */
412   /* XXX these should really go right after _mesa_init_driver_functions() */
413   radeon_fbo_init(&rmesa->radeon);
414   radeonInitSpanFuncs( ctx );
415   r200InitTnlFuncs( ctx );
416   r200InitState( rmesa );
417   r200InitSwtcl( ctx );
418
419   rmesa->prefer_gart_client_texturing =
420      (getenv("R200_GART_CLIENT_TEXTURES") != 0);
421
422   tcl_mode = driQueryOptioni(&rmesa->radeon.optionCache, "tcl_mode");
423   if (driQueryOptionb(&rmesa->radeon.optionCache, "no_rast")) {
424      fprintf(stderr, "disabling 3D acceleration\n");
425      FALLBACK(rmesa, R200_FALLBACK_DISABLE, 1);
426   }
427   else if (tcl_mode == DRI_CONF_TCL_SW || getenv("R200_NO_TCL") ||
428	    !(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) {
429      if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
430	 rmesa->radeon.radeonScreen->chip_flags &= ~RADEON_CHIPSET_TCL;
431	 fprintf(stderr, "Disabling HW TCL support\n");
432      }
433      TCL_FALLBACK(&rmesa->radeon.glCtx, R200_TCL_FALLBACK_TCL_DISABLE, 1);
434   }
435
436   _mesa_compute_version(ctx);
437
438   /* Exec table initialization requires the version to be computed */
439   _mesa_initialize_dispatch_tables(ctx);
440   _mesa_initialize_vbo_vtxfmt(ctx);
441
442   *error = __DRI_CTX_ERROR_SUCCESS;
443   return GL_TRUE;
444}
445
446
447void r200DestroyContext( __DRIcontext *driContextPriv )
448{
449	int i;
450	r200ContextPtr rmesa = (r200ContextPtr)driContextPriv->driverPrivate;
451	if (rmesa)
452	{
453		for ( i = 0 ; i < R200_MAX_TEXTURE_UNITS ; i++ ) {
454			_math_matrix_dtr( &rmesa->TexGenMatrix[i] );
455		}
456	}
457	radeonDestroyContext(driContextPriv);
458}
459