r200_context.c revision bbf029f7cf006d86a5dd13bf3bdd43f660ce2e51
1/* 2Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. 3 4The Weather Channel (TM) funded Tungsten Graphics to develop the 5initial release of the Radeon 8500 driver under the XFree86 license. 6This notice must be preserved. 7 8Permission is hereby granted, free of charge, to any person obtaining 9a copy of this software and associated documentation files (the 10"Software"), to deal in the Software without restriction, including 11without limitation the rights to use, copy, modify, merge, publish, 12distribute, sublicense, and/or sell copies of the Software, and to 13permit persons to whom the Software is furnished to do so, subject to 14the following conditions: 15 16The above copyright notice and this permission notice (including the 17next paragraph) shall be included in all copies or substantial 18portions of the Software. 19 20THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 21EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 23IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 24LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 25OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 26WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 28**************************************************************************/ 29 30/* 31 * Authors: 32 * Keith Whitwell <keith@tungstengraphics.com> 33 */ 34 35#include <stdbool.h> 36#include "main/glheader.h" 37#include "main/api_arrayelt.h" 38#include "main/api_exec.h" 39#include "main/context.h" 40#include "main/simple_list.h" 41#include "main/imports.h" 42#include "main/extensions.h" 43#include "main/version.h" 44#include "main/vtxfmt.h" 45 46#include "swrast/swrast.h" 47#include "swrast_setup/swrast_setup.h" 48#include "vbo/vbo.h" 49 50#include "tnl/tnl.h" 51#include "tnl/t_pipeline.h" 52 53#include "drivers/common/driverfuncs.h" 54 55#include "r200_context.h" 56#include "r200_ioctl.h" 57#include "r200_state.h" 58#include "r200_tex.h" 59#include "r200_swtcl.h" 60#include "r200_tcl.h" 61#include "r200_vertprog.h" 62#include "radeon_queryobj.h" 63#include "r200_blit.h" 64#include "radeon_fog.h" 65 66#include "radeon_span.h" 67 68#include "utils.h" 69#include "xmlpool.h" /* for symbolic values of enum-type options */ 70 71/* Return various strings for glGetString(). 72 */ 73static const GLubyte *r200GetString( struct gl_context *ctx, GLenum name ) 74{ 75 r200ContextPtr rmesa = R200_CONTEXT(ctx); 76 static char buffer[128]; 77 unsigned offset; 78 GLuint agp_mode = (rmesa->radeon.radeonScreen->card_type == RADEON_CARD_PCI)? 0 : 79 rmesa->radeon.radeonScreen->AGPMode; 80 81 switch ( name ) { 82 case GL_VENDOR: 83 return (GLubyte *)"Tungsten Graphics, Inc."; 84 85 case GL_RENDERER: 86 offset = driGetRendererString( buffer, "R200", agp_mode ); 87 88 sprintf( & buffer[ offset ], " %sTCL", 89 !(rmesa->radeon.TclFallback & R200_TCL_FALLBACK_TCL_DISABLE) 90 ? "" : "NO-" ); 91 92 return (GLubyte *)buffer; 93 94 default: 95 return NULL; 96 } 97} 98 99 100extern const struct tnl_pipeline_stage _r200_render_stage; 101extern const struct tnl_pipeline_stage _r200_tcl_stage; 102 103static const struct tnl_pipeline_stage *r200_pipeline[] = { 104 105 /* Try and go straight to t&l 106 */ 107 &_r200_tcl_stage, 108 109 /* Catch any t&l fallbacks 110 */ 111 &_tnl_vertex_transform_stage, 112 &_tnl_normal_transform_stage, 113 &_tnl_lighting_stage, 114 &_tnl_fog_coordinate_stage, 115 &_tnl_texgen_stage, 116 &_tnl_texture_transform_stage, 117 &_tnl_point_attenuation_stage, 118 &_tnl_vertex_program_stage, 119 /* Try again to go to tcl? 120 * - no good for asymmetric-twoside (do with multipass) 121 * - no good for asymmetric-unfilled (do with multipass) 122 * - good for material 123 * - good for texgen 124 * - need to manipulate a bit of state 125 * 126 * - worth it/not worth it? 127 */ 128 129 /* Else do them here. 130 */ 131/* &_r200_render_stage, */ /* FIXME: bugs with ut2003 */ 132 &_tnl_render_stage, /* FALLBACK: */ 133 NULL, 134}; 135 136 137 138/* Initialize the driver's misc functions. 139 */ 140static void r200InitDriverFuncs( struct dd_function_table *functions ) 141{ 142 functions->GetBufferSize = NULL; /* OBSOLETE */ 143 functions->GetString = r200GetString; 144} 145 146 147static void r200_get_lock(radeonContextPtr radeon) 148{ 149 r200ContextPtr rmesa = (r200ContextPtr)radeon; 150 drm_radeon_sarea_t *sarea = radeon->sarea; 151 152 R200_STATECHANGE( rmesa, ctx ); 153 if (rmesa->radeon.sarea->tiling_enabled) { 154 rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= R200_COLOR_TILE_ENABLE; 155 } 156 else rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] &= ~R200_COLOR_TILE_ENABLE; 157 158 if ( sarea->ctx_owner != rmesa->radeon.dri.hwContext ) { 159 sarea->ctx_owner = rmesa->radeon.dri.hwContext; 160 } 161 162} 163 164static void r200_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmesa) 165{ 166} 167 168static void r200_emit_query_finish(radeonContextPtr radeon) 169{ 170 BATCH_LOCALS(radeon); 171 struct radeon_query_object *query = radeon->query.current; 172 173 BEGIN_BATCH_NO_AUTOSTATE(4); 174 OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZPASS_ADDR, 0)); 175 OUT_BATCH_RELOC(0, query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0); 176 END_BATCH(); 177 query->curr_offset += sizeof(uint32_t); 178 assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE); 179 query->emitted_begin = GL_FALSE; 180} 181 182static void r200_init_vtbl(radeonContextPtr radeon) 183{ 184 radeon->vtbl.get_lock = r200_get_lock; 185 radeon->vtbl.update_viewport_offset = r200UpdateViewportOffset; 186 radeon->vtbl.emit_cs_header = r200_vtbl_emit_cs_header; 187 radeon->vtbl.swtcl_flush = r200_swtcl_flush; 188 radeon->vtbl.fallback = r200Fallback; 189 radeon->vtbl.update_scissor = r200_vtbl_update_scissor; 190 radeon->vtbl.emit_query_finish = r200_emit_query_finish; 191 radeon->vtbl.check_blit = r200_check_blit; 192 radeon->vtbl.blit = r200_blit; 193 radeon->vtbl.is_format_renderable = radeonIsFormatRenderable; 194} 195 196 197/* Create the device specific rendering context. 198 */ 199GLboolean r200CreateContext( gl_api api, 200 const struct gl_config *glVisual, 201 __DRIcontext *driContextPriv, 202 unsigned major_version, 203 unsigned minor_version, 204 uint32_t flags, 205 unsigned *error, 206 void *sharedContextPrivate) 207{ 208 __DRIscreen *sPriv = driContextPriv->driScreenPriv; 209 radeonScreenPtr screen = (radeonScreenPtr)(sPriv->driverPrivate); 210 struct dd_function_table functions; 211 r200ContextPtr rmesa; 212 struct gl_context *ctx; 213 int i; 214 int tcl_mode; 215 216 switch (api) { 217 case API_OPENGL_COMPAT: 218 if (major_version > 1 || minor_version > 3) { 219 *error = __DRI_CTX_ERROR_BAD_VERSION; 220 return GL_FALSE; 221 } 222 break; 223 case API_OPENGLES: 224 break; 225 default: 226 *error = __DRI_CTX_ERROR_BAD_API; 227 return GL_FALSE; 228 } 229 230 /* Flag filtering is handled in dri2CreateContextAttribs. 231 */ 232 (void) flags; 233 234 assert(glVisual); 235 assert(driContextPriv); 236 assert(screen); 237 238 /* Allocate the R200 context */ 239 rmesa = calloc(1, sizeof(*rmesa)); 240 if ( !rmesa ) { 241 *error = __DRI_CTX_ERROR_NO_MEMORY; 242 return GL_FALSE; 243 } 244 245 rmesa->radeon.radeonScreen = screen; 246 r200_init_vtbl(&rmesa->radeon); 247 /* init exp fog table data */ 248 radeonInitStaticFogData(); 249 250 /* Parse configuration files. 251 * Do this here so that initialMaxAnisotropy is set before we create 252 * the default textures. 253 */ 254 driParseConfigFiles (&rmesa->radeon.optionCache, &screen->optionCache, 255 screen->driScreen->myNum, "r200"); 256 rmesa->radeon.initialMaxAnisotropy = driQueryOptionf(&rmesa->radeon.optionCache, 257 "def_max_anisotropy"); 258 259 if ( sPriv->drm_version.major == 1 260 && driQueryOptionb( &rmesa->radeon.optionCache, "hyperz" ) ) { 261 if ( sPriv->drm_version.minor < 13 ) 262 fprintf( stderr, "DRM version 1.%d too old to support HyperZ, " 263 "disabling.\n", sPriv->drm_version.minor ); 264 else 265 rmesa->using_hyperz = GL_TRUE; 266 } 267 268 if ( sPriv->drm_version.minor >= 15 ) 269 rmesa->texmicrotile = GL_TRUE; 270 271 /* Init default driver functions then plug in our R200-specific functions 272 * (the texture functions are especially important) 273 */ 274 _mesa_init_driver_functions(&functions); 275 r200InitDriverFuncs(&functions); 276 r200InitIoctlFuncs(&functions); 277 r200InitStateFuncs(&rmesa->radeon, &functions); 278 r200InitTextureFuncs(&rmesa->radeon, &functions); 279 r200InitShaderFuncs(&functions); 280 radeonInitQueryObjFunctions(&functions); 281 282 if (!radeonInitContext(&rmesa->radeon, &functions, 283 glVisual, driContextPriv, 284 sharedContextPrivate)) { 285 free(rmesa); 286 *error = __DRI_CTX_ERROR_NO_MEMORY; 287 return GL_FALSE; 288 } 289 290 rmesa->radeon.swtcl.RenderIndex = ~0; 291 rmesa->radeon.hw.all_dirty = 1; 292 293 ctx = &rmesa->radeon.glCtx; 294 /* Initialize the software rasterizer and helper modules. 295 */ 296 _swrast_CreateContext( ctx ); 297 _vbo_CreateContext( ctx ); 298 _tnl_CreateContext( ctx ); 299 _swsetup_CreateContext( ctx ); 300 _ae_create_context( ctx ); 301 302 /* Set the maximum texture size small enough that we can guarentee that 303 * all texture units can bind a maximal texture and have all of them in 304 * texturable memory at once. Depending on the allow_large_textures driconf 305 * setting allow larger textures. 306 */ 307 ctx->Const.MaxTextureUnits = driQueryOptioni (&rmesa->radeon.optionCache, 308 "texture_units"); 309 ctx->Const.FragmentProgram.MaxTextureImageUnits = ctx->Const.MaxTextureUnits; 310 ctx->Const.MaxTextureCoordUnits = ctx->Const.MaxTextureUnits; 311 312 ctx->Const.MaxCombinedTextureImageUnits = ctx->Const.MaxTextureUnits; 313 314 ctx->Const.StripTextureBorder = GL_TRUE; 315 316 i = driQueryOptioni( &rmesa->radeon.optionCache, "allow_large_textures"); 317 318 /* FIXME: When no memory manager is available we should set this 319 * to some reasonable value based on texture memory pool size */ 320 ctx->Const.MaxTextureLevels = 12; 321 ctx->Const.Max3DTextureLevels = 9; 322 ctx->Const.MaxCubeTextureLevels = 12; 323 ctx->Const.MaxTextureRectSize = 2048; 324 ctx->Const.MaxRenderbufferSize = 2048; 325 326 ctx->Const.MaxTextureMaxAnisotropy = 16.0; 327 328 /* No wide AA points. 329 */ 330 ctx->Const.MinPointSize = 1.0; 331 ctx->Const.MinPointSizeAA = 1.0; 332 ctx->Const.MaxPointSizeAA = 1.0; 333 ctx->Const.PointSizeGranularity = 0.0625; 334 ctx->Const.MaxPointSize = 2047.0; 335 336 /* mesa initialization problem - _mesa_init_point was already called */ 337 ctx->Point.MaxSize = ctx->Const.MaxPointSize; 338 339 ctx->Const.MinLineWidth = 1.0; 340 ctx->Const.MinLineWidthAA = 1.0; 341 ctx->Const.MaxLineWidth = 10.0; 342 ctx->Const.MaxLineWidthAA = 10.0; 343 ctx->Const.LineWidthGranularity = 0.0625; 344 345 ctx->Const.VertexProgram.MaxNativeInstructions = R200_VSF_MAX_INST; 346 ctx->Const.VertexProgram.MaxNativeAttribs = 12; 347 ctx->Const.VertexProgram.MaxNativeTemps = R200_VSF_MAX_TEMPS; 348 ctx->Const.VertexProgram.MaxNativeParameters = R200_VSF_MAX_PARAM; 349 ctx->Const.VertexProgram.MaxNativeAddressRegs = 1; 350 351 ctx->Const.MaxDrawBuffers = 1; 352 ctx->Const.MaxColorAttachments = 1; 353 354 ctx->ShaderCompilerOptions[MESA_SHADER_VERTEX].PreferDP4 = GL_TRUE; 355 356 /* Install the customized pipeline: 357 */ 358 _tnl_destroy_pipeline( ctx ); 359 _tnl_install_pipeline( ctx, r200_pipeline ); 360 361 /* Try and keep materials and vertices separate: 362 */ 363/* _tnl_isolate_materials( ctx, GL_TRUE ); */ 364 365 366 /* Configure swrast and TNL to match hardware characteristics: 367 */ 368 _swrast_allow_pixel_fog( ctx, GL_FALSE ); 369 _swrast_allow_vertex_fog( ctx, GL_TRUE ); 370 _tnl_allow_pixel_fog( ctx, GL_FALSE ); 371 _tnl_allow_vertex_fog( ctx, GL_TRUE ); 372 373 374 for ( i = 0 ; i < R200_MAX_TEXTURE_UNITS ; i++ ) { 375 _math_matrix_ctr( &rmesa->TexGenMatrix[i] ); 376 _math_matrix_set_identity( &rmesa->TexGenMatrix[i] ); 377 } 378 _math_matrix_ctr( &rmesa->tmpmat ); 379 _math_matrix_set_identity( &rmesa->tmpmat ); 380 381 ctx->Extensions.ARB_half_float_pixel = true; 382 ctx->Extensions.ARB_occlusion_query = true; 383 ctx->Extensions.ARB_texture_border_clamp = true; 384 ctx->Extensions.ARB_texture_env_combine = true; 385 ctx->Extensions.ARB_texture_env_dot3 = true; 386 ctx->Extensions.ARB_texture_env_crossbar = true; 387 ctx->Extensions.EXT_blend_color = true; 388 ctx->Extensions.EXT_blend_minmax = true; 389 ctx->Extensions.EXT_fog_coord = true; 390 ctx->Extensions.EXT_packed_depth_stencil = true; 391 ctx->Extensions.EXT_secondary_color = true; 392 ctx->Extensions.EXT_texture_env_dot3 = true; 393 ctx->Extensions.EXT_texture_filter_anisotropic = true; 394 ctx->Extensions.EXT_texture_mirror_clamp = true; 395 ctx->Extensions.ATI_texture_env_combine3 = true; 396 ctx->Extensions.ATI_texture_mirror_once = true; 397 ctx->Extensions.MESA_pack_invert = true; 398 ctx->Extensions.NV_blend_square = true; 399 ctx->Extensions.NV_texture_rectangle = true; 400 ctx->Extensions.OES_EGL_image = true; 401 ctx->Extensions.EXT_framebuffer_object = true; 402 ctx->Extensions.ARB_occlusion_query = true; 403 404 if (!(rmesa->radeon.radeonScreen->chip_flags & R200_CHIPSET_YCBCR_BROKEN)) { 405 /* yuv textures don't work with some chips - R200 / rv280 okay so far 406 others get the bit ordering right but don't actually do YUV-RGB conversion */ 407 ctx->Extensions.MESA_ycbcr_texture = true; 408 } 409 if (rmesa->radeon.glCtx.Mesa_DXTn) { 410 ctx->Extensions.EXT_texture_compression_s3tc = true; 411 ctx->Extensions.ANGLE_texture_compression_dxt = true; 412 } 413 else if (driQueryOptionb (&rmesa->radeon.optionCache, "force_s3tc_enable")) { 414 ctx->Extensions.EXT_texture_compression_s3tc = true; 415 ctx->Extensions.ANGLE_texture_compression_dxt = true; 416 } 417 418 ctx->Extensions.ARB_texture_cube_map = true; 419 420 ctx->Extensions.EXT_blend_equation_separate = true; 421 ctx->Extensions.EXT_blend_func_separate = true; 422 423 ctx->Extensions.ARB_vertex_program = true; 424 ctx->Extensions.EXT_gpu_program_parameters = true; 425 426 ctx->Extensions.ATI_fragment_shader = (ctx->Const.MaxTextureUnits == 6); 427 428 ctx->Extensions.ARB_point_sprite = true; 429 ctx->Extensions.EXT_point_parameters = true; 430 431#if 0 432 r200InitDriverFuncs( ctx ); 433 r200InitIoctlFuncs( ctx ); 434 r200InitStateFuncs( ctx ); 435 r200InitTextureFuncs( ctx ); 436#endif 437 /* plug in a few more device driver functions */ 438 /* XXX these should really go right after _mesa_init_driver_functions() */ 439 radeon_fbo_init(&rmesa->radeon); 440 radeonInitSpanFuncs( ctx ); 441 r200InitTnlFuncs( ctx ); 442 r200InitState( rmesa ); 443 r200InitSwtcl( ctx ); 444 445 rmesa->prefer_gart_client_texturing = 446 (getenv("R200_GART_CLIENT_TEXTURES") != 0); 447 448 tcl_mode = driQueryOptioni(&rmesa->radeon.optionCache, "tcl_mode"); 449 if (driQueryOptionb(&rmesa->radeon.optionCache, "no_rast")) { 450 fprintf(stderr, "disabling 3D acceleration\n"); 451 FALLBACK(rmesa, R200_FALLBACK_DISABLE, 1); 452 } 453 else if (tcl_mode == DRI_CONF_TCL_SW || getenv("R200_NO_TCL") || 454 !(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) { 455 if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) { 456 rmesa->radeon.radeonScreen->chip_flags &= ~RADEON_CHIPSET_TCL; 457 fprintf(stderr, "Disabling HW TCL support\n"); 458 } 459 TCL_FALLBACK(&rmesa->radeon.glCtx, R200_TCL_FALLBACK_TCL_DISABLE, 1); 460 } 461 462 _mesa_compute_version(ctx); 463 464 /* Exec table initialization requires the version to be computed */ 465 _mesa_initialize_dispatch_tables(ctx); 466 _mesa_initialize_vbo_vtxfmt(ctx); 467 468 *error = __DRI_CTX_ERROR_SUCCESS; 469 return GL_TRUE; 470} 471 472 473void r200DestroyContext( __DRIcontext *driContextPriv ) 474{ 475 int i; 476 r200ContextPtr rmesa = (r200ContextPtr)driContextPriv->driverPrivate; 477 if (rmesa) 478 { 479 for ( i = 0 ; i < R200_MAX_TEXTURE_UNITS ; i++ ) { 480 _math_matrix_dtr( &rmesa->TexGenMatrix[i] ); 481 } 482 } 483 radeonDestroyContext(driContextPriv); 484} 485