r200_context.h revision 8c7e30fb950c83f5e9e29e60735e999ac608145a
1/* 2Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. 3 4The Weather Channel (TM) funded Tungsten Graphics to develop the 5initial release of the Radeon 8500 driver under the XFree86 license. 6This notice must be preserved. 7 8Permission is hereby granted, free of charge, to any person obtaining 9a copy of this software and associated documentation files (the 10"Software"), to deal in the Software without restriction, including 11without limitation the rights to use, copy, modify, merge, publish, 12distribute, sublicense, and/or sell copies of the Software, and to 13permit persons to whom the Software is furnished to do so, subject to 14the following conditions: 15 16The above copyright notice and this permission notice (including the 17next paragraph) shall be included in all copies or substantial 18portions of the Software. 19 20THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 21EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 23IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 24LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 25OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 26WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 28**************************************************************************/ 29 30/* 31 * Authors: 32 * Keith Whitwell <keith@tungstengraphics.com> 33 */ 34 35#ifndef __R200_CONTEXT_H__ 36#define __R200_CONTEXT_H__ 37 38#include "tnl/t_vertex.h" 39#include "drm.h" 40#include "radeon_drm.h" 41#include "dri_util.h" 42#include "texmem.h" 43 44#include "main/macros.h" 45#include "main/mtypes.h" 46#include "main/colormac.h" 47#include "r200_reg.h" 48#include "r200_vertprog.h" 49 50#define ENABLE_HW_3D_TEXTURE 1 /* XXX this is temporary! */ 51 52#ifndef R200_EMIT_VAP_PVS_CNTL 53#error This driver requires a newer libdrm to compile 54#endif 55 56#include "radeon_screen.h" 57#include "radeon_common.h" 58 59#include "radeon_lock.h" 60 61struct r200_context; 62typedef struct r200_context r200ContextRec; 63typedef struct r200_context *r200ContextPtr; 64 65#include "main/mm.h" 66 67struct r200_vertex_program { 68 struct gl_vertex_program mesa_program; /* Must be first */ 69 int translated; 70 /* need excess instr: 1 for late loop checking, 2 for 71 additional instr due to instr/attr, 3 for fog */ 72 VERTEX_SHADER_INSTRUCTION instr[R200_VSF_MAX_INST + 6]; 73 int pos_end; 74 int inputs[VERT_ATTRIB_MAX]; 75 GLubyte inputmap_rev[16]; 76 int native; 77 int fogpidx; 78 int fogmode; 79}; 80 81#define R200_TEX_ALL 0x3f 82 83 84struct r200_texture_env_state { 85 radeonTexObjPtr texobj; 86 GLuint outputreg; 87 GLuint unitneeded; 88}; 89 90#define R200_MAX_TEXTURE_UNITS 6 91 92struct r200_texture_state { 93 struct r200_texture_env_state unit[R200_MAX_TEXTURE_UNITS]; 94}; 95 96 97/* Trying to keep these relatively short as the variables are becoming 98 * extravagently long. Drop the driver name prefix off the front of 99 * everything - I think we know which driver we're in by now, and keep the 100 * prefix to 3 letters unless absolutely impossible. 101 */ 102 103#define CTX_CMD_0 0 104#define CTX_PP_MISC 1 105#define CTX_PP_FOG_COLOR 2 106#define CTX_RE_SOLID_COLOR 3 107#define CTX_RB3D_BLENDCNTL 4 108#define CTX_RB3D_DEPTHOFFSET 5 109#define CTX_RB3D_DEPTHPITCH 6 110#define CTX_RB3D_ZSTENCILCNTL 7 111#define CTX_CMD_1 8 112#define CTX_PP_CNTL 9 113#define CTX_RB3D_CNTL 10 114#define CTX_RB3D_COLOROFFSET 11 115#define CTX_CMD_2 12 /* why */ 116#define CTX_RB3D_COLORPITCH 13 /* why */ 117#define CTX_STATE_SIZE_OLDDRM 14 118#define CTX_CMD_3 14 119#define CTX_RB3D_BLENDCOLOR 15 120#define CTX_RB3D_ABLENDCNTL 16 121#define CTX_RB3D_CBLENDCNTL 17 122#define CTX_STATE_SIZE_NEWDRM 18 123 124#define SET_CMD_0 0 125#define SET_SE_CNTL 1 126#define SET_RE_CNTL 2 /* replace se_coord_fmt */ 127#define SET_STATE_SIZE 3 128 129#define VTE_CMD_0 0 130#define VTE_SE_VTE_CNTL 1 131#define VTE_STATE_SIZE 2 132 133#define LIN_CMD_0 0 134#define LIN_RE_LINE_PATTERN 1 135#define LIN_RE_LINE_STATE 2 136#define LIN_CMD_1 3 137#define LIN_SE_LINE_WIDTH 4 138#define LIN_STATE_SIZE 5 139 140#define MSK_CMD_0 0 141#define MSK_RB3D_STENCILREFMASK 1 142#define MSK_RB3D_ROPCNTL 2 143#define MSK_RB3D_PLANEMASK 3 144#define MSK_STATE_SIZE 4 145 146#define VPT_CMD_0 0 147#define VPT_SE_VPORT_XSCALE 1 148#define VPT_SE_VPORT_XOFFSET 2 149#define VPT_SE_VPORT_YSCALE 3 150#define VPT_SE_VPORT_YOFFSET 4 151#define VPT_SE_VPORT_ZSCALE 5 152#define VPT_SE_VPORT_ZOFFSET 6 153#define VPT_STATE_SIZE 7 154 155#define ZBS_CMD_0 0 156#define ZBS_SE_ZBIAS_FACTOR 1 157#define ZBS_SE_ZBIAS_CONSTANT 2 158#define ZBS_STATE_SIZE 3 159 160#define MSC_CMD_0 0 161#define MSC_RE_MISC 1 162#define MSC_STATE_SIZE 2 163 164#define TAM_CMD_0 0 165#define TAM_DEBUG3 1 166#define TAM_STATE_SIZE 2 167 168#define TEX_CMD_0 0 169#define TEX_PP_TXFILTER 1 /*2c00*/ 170#define TEX_PP_TXFORMAT 2 /*2c04*/ 171#define TEX_PP_TXFORMAT_X 3 /*2c08*/ 172#define TEX_PP_TXSIZE 4 /*2c0c*/ 173#define TEX_PP_TXPITCH 5 /*2c10*/ 174#define TEX_PP_BORDER_COLOR 6 /*2c14*/ 175#define TEX_CMD_1_OLDDRM 7 176#define TEX_PP_TXOFFSET_OLDDRM 8 /*2d00 */ 177#define TEX_STATE_SIZE_OLDDRM 9 178#define TEX_PP_CUBIC_FACES 7 179#define TEX_PP_TXMULTI_CTL 8 180#define TEX_CMD_1_NEWDRM 9 181#define TEX_PP_TXOFFSET_NEWDRM 10 182#define TEX_STATE_SIZE_NEWDRM 11 183 184#define CUBE_CMD_0 0 /* 1 register follows */ /* this command unnecessary */ 185#define CUBE_PP_CUBIC_FACES 1 /* 0x2c18 */ /* with new enough drm */ 186#define CUBE_CMD_1 2 /* 5 registers follow */ 187#define CUBE_PP_CUBIC_OFFSET_F1 3 /* 0x2d04 */ 188#define CUBE_PP_CUBIC_OFFSET_F2 4 /* 0x2d08 */ 189#define CUBE_PP_CUBIC_OFFSET_F3 5 /* 0x2d0c */ 190#define CUBE_PP_CUBIC_OFFSET_F4 6 /* 0x2d10 */ 191#define CUBE_PP_CUBIC_OFFSET_F5 7 /* 0x2d14 */ 192#define CUBE_STATE_SIZE 8 193 194#define PIX_CMD_0 0 195#define PIX_PP_TXCBLEND 1 196#define PIX_PP_TXCBLEND2 2 197#define PIX_PP_TXABLEND 3 198#define PIX_PP_TXABLEND2 4 199#define PIX_STATE_SIZE 5 200 201#define TF_CMD_0 0 202#define TF_TFACTOR_0 1 203#define TF_TFACTOR_1 2 204#define TF_TFACTOR_2 3 205#define TF_TFACTOR_3 4 206#define TF_TFACTOR_4 5 207#define TF_TFACTOR_5 6 208#define TF_STATE_SIZE 7 209 210#define ATF_CMD_0 0 211#define ATF_TFACTOR_0 1 212#define ATF_TFACTOR_1 2 213#define ATF_TFACTOR_2 3 214#define ATF_TFACTOR_3 4 215#define ATF_TFACTOR_4 5 216#define ATF_TFACTOR_5 6 217#define ATF_TFACTOR_6 7 218#define ATF_TFACTOR_7 8 219#define ATF_STATE_SIZE 9 220 221/* ATI_FRAGMENT_SHADER */ 222#define AFS_CMD_0 0 223#define AFS_IC0 1 /* 2f00 */ 224#define AFS_IC1 2 /* 2f04 */ 225#define AFS_IA0 3 /* 2f08 */ 226#define AFS_IA1 4 /* 2f0c */ 227#define AFS_STATE_SIZE 33 228 229#define PVS_CMD_0 0 230#define PVS_CNTL_1 1 231#define PVS_CNTL_2 2 232#define PVS_STATE_SIZE 3 233 234/* those are quite big... */ 235#define VPI_CMD_0 0 236#define VPI_OPDST_0 1 237#define VPI_SRC0_0 2 238#define VPI_SRC1_0 3 239#define VPI_SRC2_0 4 240#define VPI_OPDST_63 253 241#define VPI_SRC0_63 254 242#define VPI_SRC1_63 255 243#define VPI_SRC2_63 256 244#define VPI_STATE_SIZE 257 245 246#define VPP_CMD_0 0 247#define VPP_PARAM0_0 1 248#define VPP_PARAM1_0 2 249#define VPP_PARAM2_0 3 250#define VPP_PARAM3_0 4 251#define VPP_PARAM0_95 381 252#define VPP_PARAM1_95 382 253#define VPP_PARAM2_95 383 254#define VPP_PARAM3_95 384 255#define VPP_STATE_SIZE 385 256 257#define TCL_CMD_0 0 258#define TCL_LIGHT_MODEL_CTL_0 1 259#define TCL_LIGHT_MODEL_CTL_1 2 260#define TCL_PER_LIGHT_CTL_0 3 261#define TCL_PER_LIGHT_CTL_1 4 262#define TCL_PER_LIGHT_CTL_2 5 263#define TCL_PER_LIGHT_CTL_3 6 264#define TCL_CMD_1 7 265#define TCL_UCP_VERT_BLEND_CTL 8 266#define TCL_STATE_SIZE 9 267 268#define MSL_CMD_0 0 269#define MSL_MATRIX_SELECT_0 1 270#define MSL_MATRIX_SELECT_1 2 271#define MSL_MATRIX_SELECT_2 3 272#define MSL_MATRIX_SELECT_3 4 273#define MSL_MATRIX_SELECT_4 5 274#define MSL_STATE_SIZE 6 275 276#define TCG_CMD_0 0 277#define TCG_TEX_PROC_CTL_2 1 278#define TCG_TEX_PROC_CTL_3 2 279#define TCG_TEX_PROC_CTL_0 3 280#define TCG_TEX_PROC_CTL_1 4 281#define TCG_TEX_CYL_WRAP_CTL 5 282#define TCG_STATE_SIZE 6 283 284#define MTL_CMD_0 0 285#define MTL_EMMISSIVE_RED 1 286#define MTL_EMMISSIVE_GREEN 2 287#define MTL_EMMISSIVE_BLUE 3 288#define MTL_EMMISSIVE_ALPHA 4 289#define MTL_AMBIENT_RED 5 290#define MTL_AMBIENT_GREEN 6 291#define MTL_AMBIENT_BLUE 7 292#define MTL_AMBIENT_ALPHA 8 293#define MTL_DIFFUSE_RED 9 294#define MTL_DIFFUSE_GREEN 10 295#define MTL_DIFFUSE_BLUE 11 296#define MTL_DIFFUSE_ALPHA 12 297#define MTL_SPECULAR_RED 13 298#define MTL_SPECULAR_GREEN 14 299#define MTL_SPECULAR_BLUE 15 300#define MTL_SPECULAR_ALPHA 16 301#define MTL_CMD_1 17 302#define MTL_SHININESS 18 303#define MTL_STATE_SIZE 19 304 305#define VAP_CMD_0 0 306#define VAP_SE_VAP_CNTL 1 307#define VAP_STATE_SIZE 2 308 309/* Replaces a lot of packet info from radeon 310 */ 311#define VTX_CMD_0 0 312#define VTX_VTXFMT_0 1 313#define VTX_VTXFMT_1 2 314#define VTX_TCL_OUTPUT_VTXFMT_0 3 315#define VTX_TCL_OUTPUT_VTXFMT_1 4 316#define VTX_CMD_1 5 317#define VTX_TCL_OUTPUT_COMPSEL 6 318#define VTX_CMD_2 7 319#define VTX_STATE_CNTL 8 320#define VTX_STATE_SIZE 9 321 322/* SPR - point sprite state 323 */ 324#define SPR_CMD_0 0 325#define SPR_POINT_SPRITE_CNTL 1 326#define SPR_STATE_SIZE 2 327 328#define PTP_CMD_0 0 329#define PTP_VPORT_SCALE_0 1 330#define PTP_VPORT_SCALE_1 2 331#define PTP_VPORT_SCALE_PTSIZE 3 332#define PTP_VPORT_SCALE_3 4 333#define PTP_CMD_1 5 334#define PTP_ATT_CONST_QUAD 6 335#define PTP_ATT_CONST_LIN 7 336#define PTP_ATT_CONST_CON 8 337#define PTP_ATT_CONST_3 9 338#define PTP_EYE_X 10 339#define PTP_EYE_Y 11 340#define PTP_EYE_Z 12 341#define PTP_EYE_3 13 342#define PTP_CLAMP_MIN 14 343#define PTP_CLAMP_MAX 15 344#define PTP_CLAMP_2 16 345#define PTP_CLAMP_3 17 346#define PTP_STATE_SIZE 18 347 348#define VTX_COLOR(v,n) (((v)>>(R200_VTX_COLOR_0_SHIFT+(n)*2))&\ 349 R200_VTX_COLOR_MASK) 350 351/** 352 * Given the \c R200_SE_VTX_FMT_1 for the current vertex state, determine 353 * how many components are in texture coordinate \c n. 354 */ 355#define VTX_TEXn_COUNT(v,n) (((v) >> (3 * n)) & 0x07) 356 357#define MAT_CMD_0 0 358#define MAT_ELT_0 1 359#define MAT_STATE_SIZE 17 360 361#define GRD_CMD_0 0 362#define GRD_VERT_GUARD_CLIP_ADJ 1 363#define GRD_VERT_GUARD_DISCARD_ADJ 2 364#define GRD_HORZ_GUARD_CLIP_ADJ 3 365#define GRD_HORZ_GUARD_DISCARD_ADJ 4 366#define GRD_STATE_SIZE 5 367 368/* position changes frequently when lighting in modelpos - separate 369 * out to new state item? 370 */ 371#define LIT_CMD_0 0 372#define LIT_AMBIENT_RED 1 373#define LIT_AMBIENT_GREEN 2 374#define LIT_AMBIENT_BLUE 3 375#define LIT_AMBIENT_ALPHA 4 376#define LIT_DIFFUSE_RED 5 377#define LIT_DIFFUSE_GREEN 6 378#define LIT_DIFFUSE_BLUE 7 379#define LIT_DIFFUSE_ALPHA 8 380#define LIT_SPECULAR_RED 9 381#define LIT_SPECULAR_GREEN 10 382#define LIT_SPECULAR_BLUE 11 383#define LIT_SPECULAR_ALPHA 12 384#define LIT_POSITION_X 13 385#define LIT_POSITION_Y 14 386#define LIT_POSITION_Z 15 387#define LIT_POSITION_W 16 388#define LIT_DIRECTION_X 17 389#define LIT_DIRECTION_Y 18 390#define LIT_DIRECTION_Z 19 391#define LIT_DIRECTION_W 20 392#define LIT_ATTEN_QUADRATIC 21 393#define LIT_ATTEN_LINEAR 22 394#define LIT_ATTEN_CONST 23 395#define LIT_ATTEN_XXX 24 396#define LIT_CMD_1 25 397#define LIT_SPOT_DCD 26 398#define LIT_SPOT_DCM 27 399#define LIT_SPOT_EXPONENT 28 400#define LIT_SPOT_CUTOFF 29 401#define LIT_SPECULAR_THRESH 30 402#define LIT_RANGE_CUTOFF 31 /* ? */ 403#define LIT_ATTEN_CONST_INV 32 404#define LIT_STATE_SIZE 33 405 406/* Fog 407 */ 408#define FOG_CMD_0 0 409#define FOG_R 1 410#define FOG_C 2 411#define FOG_D 3 412#define FOG_PAD 4 413#define FOG_STATE_SIZE 5 414 415/* UCP 416 */ 417#define UCP_CMD_0 0 418#define UCP_X 1 419#define UCP_Y 2 420#define UCP_Z 3 421#define UCP_W 4 422#define UCP_STATE_SIZE 5 423 424/* GLT - Global ambient 425 */ 426#define GLT_CMD_0 0 427#define GLT_RED 1 428#define GLT_GREEN 2 429#define GLT_BLUE 3 430#define GLT_ALPHA 4 431#define GLT_STATE_SIZE 5 432 433/* EYE 434 */ 435#define EYE_CMD_0 0 436#define EYE_X 1 437#define EYE_Y 2 438#define EYE_Z 3 439#define EYE_RESCALE_FACTOR 4 440#define EYE_STATE_SIZE 5 441 442/* CST - constant state 443 */ 444#define CST_CMD_0 0 445#define CST_PP_CNTL_X 1 446#define CST_CMD_1 2 447#define CST_RB3D_DEPTHXY_OFFSET 3 448#define CST_CMD_2 4 449#define CST_RE_AUX_SCISSOR_CNTL 5 450#define CST_CMD_3 6 451#define CST_RE_SCISSOR_TL_0 7 452#define CST_RE_SCISSOR_BR_0 8 453#define CST_CMD_4 9 454#define CST_SE_VAP_CNTL_STATUS 10 455#define CST_CMD_5 11 456#define CST_RE_POINTSIZE 12 457#define CST_CMD_6 13 458#define CST_SE_TCL_INPUT_VTX_0 14 459#define CST_SE_TCL_INPUT_VTX_1 15 460#define CST_SE_TCL_INPUT_VTX_2 16 461#define CST_SE_TCL_INPUT_VTX_3 17 462#define CST_STATE_SIZE 18 463 464#define PRF_CMD_0 0 465#define PRF_PP_TRI_PERF 1 466#define PRF_PP_PERF_CNTL 2 467#define PRF_STATE_SIZE 3 468 469 470struct r200_hw_state { 471 /* Hardware state, stored as cmdbuf commands: 472 * -- Need to doublebuffer for 473 * - reviving state after loss of context 474 * - eliding noop statechange loops? (except line stipple count) 475 */ 476 struct radeon_state_atom ctx; 477 struct radeon_state_atom set; 478 struct radeon_state_atom vte; 479 struct radeon_state_atom lin; 480 struct radeon_state_atom msk; 481 struct radeon_state_atom vpt; 482 struct radeon_state_atom vap; 483 struct radeon_state_atom vtx; 484 struct radeon_state_atom tcl; 485 struct radeon_state_atom msl; 486 struct radeon_state_atom tcg; 487 struct radeon_state_atom msc; 488 struct radeon_state_atom cst; 489 struct radeon_state_atom tam; 490 struct radeon_state_atom tf; 491 struct radeon_state_atom tex[6]; 492 struct radeon_state_atom cube[6]; 493 struct radeon_state_atom zbs; 494 struct radeon_state_atom mtl[2]; 495 struct radeon_state_atom mat[9]; 496 struct radeon_state_atom lit[8]; /* includes vec, scl commands */ 497 struct radeon_state_atom ucp[6]; 498 struct radeon_state_atom pix[6]; /* pixshader stages */ 499 struct radeon_state_atom eye; /* eye pos */ 500 struct radeon_state_atom grd; /* guard band clipping */ 501 struct radeon_state_atom fog; 502 struct radeon_state_atom glt; 503 struct radeon_state_atom prf; 504 struct radeon_state_atom afs[2]; 505 struct radeon_state_atom pvs; 506 struct radeon_state_atom vpi[2]; 507 struct radeon_state_atom vpp[2]; 508 struct radeon_state_atom atf; 509 struct radeon_state_atom spr; 510 struct radeon_state_atom ptp; 511}; 512 513struct r200_state { 514 /* Derived state for internal purposes: 515 */ 516 struct radeon_stipple_state stipple; 517 struct r200_texture_state texture; 518 GLuint envneeded; 519}; 520 521#define R200_CMD_BUF_SZ (16*1024) 522 523#define R200_ELT_BUF_SZ (16*1024) 524/* r200_tcl.c 525 */ 526struct r200_tcl_info { 527 GLuint hw_primitive; 528 529/* hw can handle 12 components max */ 530 struct radeon_aos aos[12]; 531 GLuint nr_aos_components; 532 533 GLuint *Elts; 534 535 struct radeon_bo *elt_dma_bo; 536 int elt_dma_offset; /** Offset into this buffer object, in bytes */ 537 int elt_used; 538 539}; 540 541 542/* r200_swtcl.c 543 */ 544struct r200_swtcl_info { 545 546 547 radeon_point_func draw_point; 548 radeon_line_func draw_line; 549 radeon_tri_func draw_tri; 550 551 /** 552 * Offset of the 4UB color data within a hardware (swtcl) vertex. 553 */ 554 GLuint coloroffset; 555 556 /** 557 * Offset of the 3UB specular color data within a hardware (swtcl) vertex. 558 */ 559 GLuint specoffset; 560 561 /** 562 * Should Mesa project vertex data or will the hardware do it? 563 */ 564 GLboolean needproj; 565}; 566 567 568 569 570 /* A maximum total of 29 elements per vertex: 3 floats for position, 3 571 * floats for normal, 4 floats for color, 4 bytes for secondary color, 572 * 3 floats for each texture unit (18 floats total). 573 * 574 * we maybe need add. 4 to prevent segfault if someone specifies 575 * GL_TEXTURE6/GL_TEXTURE7 (esp. for the codegen-path) (FIXME: ) 576 * 577 * The position data is never actually stored here, so 3 elements could be 578 * trimmed out of the buffer. 579 */ 580 581#define R200_MAX_VERTEX_SIZE ((3*6)+11) 582 583struct r200_context { 584 struct radeon_context radeon; 585 586 /* Driver and hardware state management 587 */ 588 struct r200_hw_state hw; 589 struct r200_state state; 590 struct r200_vertex_program *curr_vp_hw; 591 592 /* Vertex buffers 593 */ 594 struct radeon_ioctl ioctl; 595 struct radeon_store store; 596 597 /* Clientdata textures; 598 */ 599 GLuint prefer_gart_client_texturing; 600 601 /* TCL stuff 602 */ 603 GLmatrix TexGenMatrix[R200_MAX_TEXTURE_UNITS]; 604 GLboolean recheck_texgen[R200_MAX_TEXTURE_UNITS]; 605 GLboolean TexGenNeedNormals[R200_MAX_TEXTURE_UNITS]; 606 GLuint TexMatEnabled; 607 GLuint TexMatCompSel; 608 GLuint TexGenEnabled; 609 GLuint TexGenCompSel; 610 GLmatrix tmpmat; 611 612 /* r200_tcl.c 613 */ 614 struct r200_tcl_info tcl; 615 616 /* r200_swtcl.c 617 */ 618 struct r200_swtcl_info swtcl; 619 620 GLboolean using_hyperz; 621 GLboolean texmicrotile; 622 623 struct ati_fragment_shader *afs_loaded; 624}; 625 626#define R200_CONTEXT(ctx) ((r200ContextPtr)(ctx->DriverCtx)) 627 628 629extern void r200DestroyContext( __DRIcontextPrivate *driContextPriv ); 630extern GLboolean r200CreateContext( const __GLcontextModes *glVisual, 631 __DRIcontextPrivate *driContextPriv, 632 void *sharedContextPrivate); 633extern GLboolean r200MakeCurrent( __DRIcontextPrivate *driContextPriv, 634 __DRIdrawablePrivate *driDrawPriv, 635 __DRIdrawablePrivate *driReadPriv ); 636extern GLboolean r200UnbindContext( __DRIcontextPrivate *driContextPriv ); 637 638/* ================================================================ 639 * Debugging: 640 */ 641 642#define R200_DEBUG RADEON_DEBUG 643 644 645 646#endif /* __R200_CONTEXT_H__ */ 647