radeon_context.h revision 6ddfdff659196cf4eeb0e5fed70ddd1ced0d16fc
1/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_context.h,v 1.6 2002/12/16 16:18:58 dawes Exp $ */ 2/************************************************************************** 3 4Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and 5 VA Linux Systems Inc., Fremont, California. 6 7All Rights Reserved. 8 9Permission is hereby granted, free of charge, to any person obtaining 10a copy of this software and associated documentation files (the 11"Software"), to deal in the Software without restriction, including 12without limitation the rights to use, copy, modify, merge, publish, 13distribute, sublicense, and/or sell copies of the Software, and to 14permit persons to whom the Software is furnished to do so, subject to 15the following conditions: 16 17The above copyright notice and this permission notice (including the 18next paragraph) shall be included in all copies or substantial 19portions of the Software. 20 21THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 22EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 23MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 24IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 25LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 26OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 27WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 28 29**************************************************************************/ 30 31/* 32 * Authors: 33 * Kevin E. Martin <martin@valinux.com> 34 * Gareth Hughes <gareth@valinux.com> 35 * Keith Whitwell <keith@tungstengraphics.com> 36 */ 37 38#ifndef __RADEON_CONTEXT_H__ 39#define __RADEON_CONTEXT_H__ 40 41#ifdef GLX_DIRECT_RENDERING 42 43#include <inttypes.h> 44#include "dri_util.h" 45#include "drm.h" 46#include "radeon_drm.h" 47#include "texmem.h" 48 49#include "macros.h" 50#include "mtypes.h" 51#include "colormac.h" 52 53struct radeon_context; 54typedef struct radeon_context radeonContextRec; 55typedef struct radeon_context *radeonContextPtr; 56 57#include "radeon_lock.h" 58#include "radeon_screen.h" 59#include "mm.h" 60 61#include "math/m_vector.h" 62 63/* Flags for software fallback cases */ 64/* See correponding strings in radeon_swtcl.c */ 65#define RADEON_FALLBACK_TEXTURE 0x0001 66#define RADEON_FALLBACK_DRAW_BUFFER 0x0002 67#define RADEON_FALLBACK_STENCIL 0x0004 68#define RADEON_FALLBACK_RENDER_MODE 0x0008 69#define RADEON_FALLBACK_BLEND_EQ 0x0010 70#define RADEON_FALLBACK_BLEND_FUNC 0x0020 71#define RADEON_FALLBACK_DISABLE 0x0040 72#define RADEON_FALLBACK_BORDER_MODE 0x0080 73 74/* The blit width for texture uploads 75 */ 76#define BLIT_WIDTH_BYTES 1024 77 78/* Use the templated vertex format: 79 */ 80#define COLOR_IS_RGBA 81#define TAG(x) radeon##x 82#include "tnl_dd/t_dd_vertex.h" 83#undef TAG 84 85typedef void (*radeon_tri_func)( radeonContextPtr, 86 radeonVertex *, 87 radeonVertex *, 88 radeonVertex * ); 89 90typedef void (*radeon_line_func)( radeonContextPtr, 91 radeonVertex *, 92 radeonVertex * ); 93 94typedef void (*radeon_point_func)( radeonContextPtr, 95 radeonVertex * ); 96 97 98struct radeon_colorbuffer_state { 99 GLuint clear; 100 GLint drawOffset, drawPitch; 101 int roundEnable; 102}; 103 104 105struct radeon_depthbuffer_state { 106 GLuint clear; 107 GLfloat scale; 108}; 109 110struct radeon_pixel_state { 111 GLint readOffset, readPitch; 112}; 113 114struct radeon_scissor_state { 115 drm_clip_rect_t rect; 116 GLboolean enabled; 117 118 GLuint numClipRects; /* Cliprects active */ 119 GLuint numAllocedClipRects; /* Cliprects available */ 120 drm_clip_rect_t *pClipRects; 121}; 122 123struct radeon_stencilbuffer_state { 124 GLboolean hwBuffer; 125 GLuint clear; /* rb3d_stencilrefmask value */ 126}; 127 128struct radeon_stipple_state { 129 GLuint mask[32]; 130}; 131 132 133 134#define TEX_0 0x1 135#define TEX_1 0x2 136#define TEX_ALL 0x3 137 138typedef struct radeon_tex_obj radeonTexObj, *radeonTexObjPtr; 139 140/* Texture object in locally shared texture space. 141 */ 142struct radeon_tex_obj { 143 driTextureObject base; 144 145 GLuint bufAddr; /* Offset to start of locally 146 shared texture block */ 147 148 GLuint dirty_state; /* Flags (1 per texunit) for 149 whether or not this texobj 150 has dirty hardware state 151 (pp_*) that needs to be 152 brought into the 153 texunit. */ 154 155 drm_radeon_tex_image_t image[6][RADEON_MAX_TEXTURE_LEVELS]; 156 /* Six, for the cube faces */ 157 158 GLuint pp_txfilter; /* hardware register values */ 159 GLuint pp_txformat; 160 GLuint pp_txoffset; /* Image location in texmem. 161 All cube faces follow. */ 162 GLuint pp_txsize; /* npot only */ 163 GLuint pp_txpitch; /* npot only */ 164 GLuint pp_border_color; 165 GLuint pp_cubic_faces; /* cube face 1,2,3,4 log2 sizes */ 166 167 GLboolean border_fallback; 168}; 169 170 171struct radeon_texture_env_state { 172 radeonTexObjPtr texobj; 173 GLenum format; 174 GLenum envMode; 175}; 176 177struct radeon_texture_state { 178 struct radeon_texture_env_state unit[RADEON_MAX_TEXTURE_UNITS]; 179}; 180 181 182struct radeon_state_atom { 183 struct radeon_state_atom *next, *prev; 184 const char *name; /* for debug */ 185 int cmd_size; /* size in bytes */ 186 GLuint is_tcl; 187 int *cmd; /* one or more cmd's */ 188 int *lastcmd; /* one or more cmd's */ 189 GLboolean dirty; /* dirty-mark in emit_state_list */ 190 GLboolean (*check)( GLcontext * ); /* is this state active? */ 191}; 192 193 194 195/* Trying to keep these relatively short as the variables are becoming 196 * extravagently long. Drop the driver name prefix off the front of 197 * everything - I think we know which driver we're in by now, and keep the 198 * prefix to 3 letters unless absolutely impossible. 199 */ 200 201#define CTX_CMD_0 0 202#define CTX_PP_MISC 1 203#define CTX_PP_FOG_COLOR 2 204#define CTX_RE_SOLID_COLOR 3 205#define CTX_RB3D_BLENDCNTL 4 206#define CTX_RB3D_DEPTHOFFSET 5 207#define CTX_RB3D_DEPTHPITCH 6 208#define CTX_RB3D_ZSTENCILCNTL 7 209#define CTX_CMD_1 8 210#define CTX_PP_CNTL 9 211#define CTX_RB3D_CNTL 10 212#define CTX_RB3D_COLOROFFSET 11 213#define CTX_CMD_2 12 214#define CTX_RB3D_COLORPITCH 13 215#define CTX_STATE_SIZE 14 216 217#define SET_CMD_0 0 218#define SET_SE_CNTL 1 219#define SET_SE_COORDFMT 2 220#define SET_CMD_1 3 221#define SET_SE_CNTL_STATUS 4 222#define SET_STATE_SIZE 5 223 224#define LIN_CMD_0 0 225#define LIN_RE_LINE_PATTERN 1 226#define LIN_RE_LINE_STATE 2 227#define LIN_CMD_1 3 228#define LIN_SE_LINE_WIDTH 4 229#define LIN_STATE_SIZE 5 230 231#define MSK_CMD_0 0 232#define MSK_RB3D_STENCILREFMASK 1 233#define MSK_RB3D_ROPCNTL 2 234#define MSK_RB3D_PLANEMASK 3 235#define MSK_STATE_SIZE 4 236 237#define VPT_CMD_0 0 238#define VPT_SE_VPORT_XSCALE 1 239#define VPT_SE_VPORT_XOFFSET 2 240#define VPT_SE_VPORT_YSCALE 3 241#define VPT_SE_VPORT_YOFFSET 4 242#define VPT_SE_VPORT_ZSCALE 5 243#define VPT_SE_VPORT_ZOFFSET 6 244#define VPT_STATE_SIZE 7 245 246#define MSC_CMD_0 0 247#define MSC_RE_MISC 1 248#define MSC_STATE_SIZE 2 249 250#define TEX_CMD_0 0 251#define TEX_PP_TXFILTER 1 252#define TEX_PP_TXFORMAT 2 253#define TEX_PP_TXOFFSET 3 254#define TEX_PP_TXCBLEND 4 255#define TEX_PP_TXABLEND 5 256#define TEX_PP_TFACTOR 6 257#define TEX_CMD_1 7 258#define TEX_PP_BORDER_COLOR 8 259#define TEX_STATE_SIZE 9 260 261#define TXR_CMD_0 0 /* rectangle textures */ 262#define TXR_PP_TEX_SIZE 1 /* 0x1d04, 0x1d0c for NPOT! */ 263#define TXR_PP_TEX_PITCH 2 /* 0x1d08, 0x1d10 for NPOT! */ 264#define TXR_STATE_SIZE 3 265 266#define ZBS_CMD_0 0 267#define ZBS_SE_ZBIAS_FACTOR 1 268#define ZBS_SE_ZBIAS_CONSTANT 2 269#define ZBS_STATE_SIZE 3 270 271#define TCL_CMD_0 0 272#define TCL_OUTPUT_VTXFMT 1 273#define TCL_OUTPUT_VTXSEL 2 274#define TCL_MATRIX_SELECT_0 3 275#define TCL_MATRIX_SELECT_1 4 276#define TCL_UCP_VERT_BLEND_CTL 5 277#define TCL_TEXTURE_PROC_CTL 6 278#define TCL_LIGHT_MODEL_CTL 7 279#define TCL_PER_LIGHT_CTL_0 8 280#define TCL_PER_LIGHT_CTL_1 9 281#define TCL_PER_LIGHT_CTL_2 10 282#define TCL_PER_LIGHT_CTL_3 11 283#define TCL_STATE_SIZE 12 284 285#define MTL_CMD_0 0 286#define MTL_EMMISSIVE_RED 1 287#define MTL_EMMISSIVE_GREEN 2 288#define MTL_EMMISSIVE_BLUE 3 289#define MTL_EMMISSIVE_ALPHA 4 290#define MTL_AMBIENT_RED 5 291#define MTL_AMBIENT_GREEN 6 292#define MTL_AMBIENT_BLUE 7 293#define MTL_AMBIENT_ALPHA 8 294#define MTL_DIFFUSE_RED 9 295#define MTL_DIFFUSE_GREEN 10 296#define MTL_DIFFUSE_BLUE 11 297#define MTL_DIFFUSE_ALPHA 12 298#define MTL_SPECULAR_RED 13 299#define MTL_SPECULAR_GREEN 14 300#define MTL_SPECULAR_BLUE 15 301#define MTL_SPECULAR_ALPHA 16 302#define MTL_SHININESS 17 303#define MTL_STATE_SIZE 18 304 305#define VTX_CMD_0 0 306#define VTX_SE_COORD_FMT 1 307#define VTX_STATE_SIZE 2 308 309#define MAT_CMD_0 0 310#define MAT_ELT_0 1 311#define MAT_STATE_SIZE 17 312 313#define GRD_CMD_0 0 314#define GRD_VERT_GUARD_CLIP_ADJ 1 315#define GRD_VERT_GUARD_DISCARD_ADJ 2 316#define GRD_HORZ_GUARD_CLIP_ADJ 3 317#define GRD_HORZ_GUARD_DISCARD_ADJ 4 318#define GRD_STATE_SIZE 5 319 320/* position changes frequently when lighting in modelpos - separate 321 * out to new state item? 322 */ 323#define LIT_CMD_0 0 324#define LIT_AMBIENT_RED 1 325#define LIT_AMBIENT_GREEN 2 326#define LIT_AMBIENT_BLUE 3 327#define LIT_AMBIENT_ALPHA 4 328#define LIT_DIFFUSE_RED 5 329#define LIT_DIFFUSE_GREEN 6 330#define LIT_DIFFUSE_BLUE 7 331#define LIT_DIFFUSE_ALPHA 8 332#define LIT_SPECULAR_RED 9 333#define LIT_SPECULAR_GREEN 10 334#define LIT_SPECULAR_BLUE 11 335#define LIT_SPECULAR_ALPHA 12 336#define LIT_POSITION_X 13 337#define LIT_POSITION_Y 14 338#define LIT_POSITION_Z 15 339#define LIT_POSITION_W 16 340#define LIT_DIRECTION_X 17 341#define LIT_DIRECTION_Y 18 342#define LIT_DIRECTION_Z 19 343#define LIT_DIRECTION_W 20 344#define LIT_ATTEN_QUADRATIC 21 345#define LIT_ATTEN_LINEAR 22 346#define LIT_ATTEN_CONST 23 347#define LIT_ATTEN_XXX 24 348#define LIT_CMD_1 25 349#define LIT_SPOT_DCD 26 350#define LIT_SPOT_EXPONENT 27 351#define LIT_SPOT_CUTOFF 28 352#define LIT_SPECULAR_THRESH 29 353#define LIT_RANGE_CUTOFF 30 /* ? */ 354#define LIT_ATTEN_CONST_INV 31 355#define LIT_STATE_SIZE 32 356 357/* Fog 358 */ 359#define FOG_CMD_0 0 360#define FOG_R 1 361#define FOG_C 2 362#define FOG_D 3 363#define FOG_PAD 4 364#define FOG_STATE_SIZE 5 365 366/* UCP 367 */ 368#define UCP_CMD_0 0 369#define UCP_X 1 370#define UCP_Y 2 371#define UCP_Z 3 372#define UCP_W 4 373#define UCP_STATE_SIZE 5 374 375/* GLT - Global ambient 376 */ 377#define GLT_CMD_0 0 378#define GLT_RED 1 379#define GLT_GREEN 2 380#define GLT_BLUE 3 381#define GLT_ALPHA 4 382#define GLT_STATE_SIZE 5 383 384/* EYE 385 */ 386#define EYE_CMD_0 0 387#define EYE_X 1 388#define EYE_Y 2 389#define EYE_Z 3 390#define EYE_RESCALE_FACTOR 4 391#define EYE_STATE_SIZE 5 392 393#define SHN_CMD_0 0 394#define SHN_SHININESS 1 395#define SHN_STATE_SIZE 2 396 397 398 399 400 401struct radeon_hw_state { 402 /* All state should be on one of these lists: 403 */ 404 struct radeon_state_atom dirty; /* dirty list head placeholder */ 405 struct radeon_state_atom clean; /* clean list head placeholder */ 406 407 /* Hardware state, stored as cmdbuf commands: 408 * -- Need to doublebuffer for 409 * - reviving state after loss of context 410 * - eliding noop statechange loops? (except line stipple count) 411 */ 412 struct radeon_state_atom ctx; 413 struct radeon_state_atom set; 414 struct radeon_state_atom lin; 415 struct radeon_state_atom msk; 416 struct radeon_state_atom vpt; 417 struct radeon_state_atom tcl; 418 struct radeon_state_atom msc; 419 struct radeon_state_atom tex[2]; 420 struct radeon_state_atom zbs; 421 struct radeon_state_atom mtl; 422 struct radeon_state_atom mat[5]; 423 struct radeon_state_atom lit[8]; /* includes vec, scl commands */ 424 struct radeon_state_atom ucp[6]; 425 struct radeon_state_atom eye; /* eye pos */ 426 struct radeon_state_atom grd; /* guard band clipping */ 427 struct radeon_state_atom fog; 428 struct radeon_state_atom glt; 429 struct radeon_state_atom txr[2]; /* for NPOT */ 430}; 431 432struct radeon_state { 433 /* Derived state for internal purposes: 434 */ 435 struct radeon_colorbuffer_state color; 436 struct radeon_depthbuffer_state depth; 437 struct radeon_pixel_state pixel; 438 struct radeon_scissor_state scissor; 439 struct radeon_stencilbuffer_state stencil; 440 struct radeon_stipple_state stipple; 441 struct radeon_texture_state texture; 442}; 443 444 445/* Need refcounting on dma buffers: 446 */ 447struct radeon_dma_buffer { 448 int refcount; /* the number of retained regions in buf */ 449 drmBufPtr buf; 450}; 451 452#define GET_START(rvb) (rmesa->radeonScreen->gart_buffer_offset + \ 453 (rvb)->address - rmesa->dma.buf0_address + \ 454 (rvb)->start) 455 456/* A retained region, eg vertices for indexed vertices. 457 */ 458struct radeon_dma_region { 459 struct radeon_dma_buffer *buf; 460 char *address; /* == buf->address */ 461 int start, end, ptr; /* offsets from start of buf */ 462 int aos_start; 463 int aos_stride; 464 int aos_size; 465}; 466 467 468struct radeon_dma { 469 /* Active dma region. Allocations for vertices and retained 470 * regions come from here. Also used for emitting random vertices, 471 * these may be flushed by calling flush_current(); 472 */ 473 struct radeon_dma_region current; 474 475 void (*flush)( radeonContextPtr ); 476 477 char *buf0_address; /* start of buf[0], for index calcs */ 478 GLuint nr_released_bufs; /* flush after so many buffers released */ 479}; 480 481struct radeon_dri_mirror { 482 __DRIcontextPrivate *context; /* DRI context */ 483 __DRIscreenPrivate *screen; /* DRI screen */ 484 __DRIdrawablePrivate *drawable; /* DRI drawable bound to this ctx */ 485 486 drmContext hwContext; 487 drm_hw_lock_t *hwLock; 488 int fd; 489 int drmMinor; 490}; 491 492 493#define RADEON_CMD_BUF_SZ (8*1024) 494 495struct radeon_store { 496 GLuint statenr; 497 GLuint primnr; 498 char cmd_buf[RADEON_CMD_BUF_SZ]; 499 int cmd_used; 500 int elts_start; 501}; 502 503 504/* radeon_tcl.c 505 */ 506struct radeon_tcl_info { 507 GLuint vertex_format; 508 GLint last_offset; 509 GLuint hw_primitive; 510 511 /* Temporary for cases where incoming vertex data is incompatible 512 * with maos code. 513 */ 514 GLvector4f ObjClean; 515 516 struct radeon_dma_region *aos_components[8]; 517 GLuint nr_aos_components; 518 519 GLuint *Elts; 520 521 struct radeon_dma_region indexed_verts; 522 struct radeon_dma_region obj; 523 struct radeon_dma_region rgba; 524 struct radeon_dma_region spec; 525 struct radeon_dma_region fog; 526 struct radeon_dma_region tex[RADEON_MAX_TEXTURE_UNITS]; 527 struct radeon_dma_region norm; 528}; 529 530 531/* radeon_swtcl.c 532 */ 533struct radeon_swtcl_info { 534 GLuint SetupIndex; 535 GLuint SetupNewInputs; 536 GLuint RenderIndex; 537 GLuint vertex_size; 538 GLuint vertex_stride_shift; 539 GLuint vertex_format; 540 GLubyte *verts; 541 542 /* Fallback rasterization functions 543 */ 544 radeon_point_func draw_point; 545 radeon_line_func draw_line; 546 radeon_tri_func draw_tri; 547 548 GLuint hw_primitive; 549 GLenum render_primitive; 550 GLuint numverts; 551 552 struct radeon_dma_region indexed_verts; 553}; 554 555 556struct radeon_ioctl { 557 GLuint vertex_offset; 558 GLuint vertex_size; 559}; 560 561 562 563#define RADEON_MAX_PRIMS 64 564 565 566/* Want to keep a cache of these around. Each is parameterized by 567 * only a single value which has only a small range. Only expect a 568 * few, so just rescan the list each time? 569 */ 570struct dynfn { 571 struct dynfn *next, *prev; 572 int key; 573 char *code; 574}; 575 576struct dfn_lists { 577 struct dynfn Vertex2f; 578 struct dynfn Vertex2fv; 579 struct dynfn Vertex3f; 580 struct dynfn Vertex3fv; 581 struct dynfn Color4ub; 582 struct dynfn Color4ubv; 583 struct dynfn Color3ub; 584 struct dynfn Color3ubv; 585 struct dynfn Color4f; 586 struct dynfn Color4fv; 587 struct dynfn Color3f; 588 struct dynfn Color3fv; 589 struct dynfn SecondaryColor3ubEXT; 590 struct dynfn SecondaryColor3ubvEXT; 591 struct dynfn SecondaryColor3fEXT; 592 struct dynfn SecondaryColor3fvEXT; 593 struct dynfn Normal3f; 594 struct dynfn Normal3fv; 595 struct dynfn TexCoord2f; 596 struct dynfn TexCoord2fv; 597 struct dynfn TexCoord1f; 598 struct dynfn TexCoord1fv; 599 struct dynfn MultiTexCoord2fARB; 600 struct dynfn MultiTexCoord2fvARB; 601 struct dynfn MultiTexCoord1fARB; 602 struct dynfn MultiTexCoord1fvARB; 603}; 604 605struct dfn_generators { 606 struct dynfn *(*Vertex2f)( GLcontext *, int ); 607 struct dynfn *(*Vertex2fv)( GLcontext *, int ); 608 struct dynfn *(*Vertex3f)( GLcontext *, int ); 609 struct dynfn *(*Vertex3fv)( GLcontext *, int ); 610 struct dynfn *(*Color4ub)( GLcontext *, int ); 611 struct dynfn *(*Color4ubv)( GLcontext *, int ); 612 struct dynfn *(*Color3ub)( GLcontext *, int ); 613 struct dynfn *(*Color3ubv)( GLcontext *, int ); 614 struct dynfn *(*Color4f)( GLcontext *, int ); 615 struct dynfn *(*Color4fv)( GLcontext *, int ); 616 struct dynfn *(*Color3f)( GLcontext *, int ); 617 struct dynfn *(*Color3fv)( GLcontext *, int ); 618 struct dynfn *(*SecondaryColor3ubEXT)( GLcontext *, int ); 619 struct dynfn *(*SecondaryColor3ubvEXT)( GLcontext *, int ); 620 struct dynfn *(*SecondaryColor3fEXT)( GLcontext *, int ); 621 struct dynfn *(*SecondaryColor3fvEXT)( GLcontext *, int ); 622 struct dynfn *(*Normal3f)( GLcontext *, int ); 623 struct dynfn *(*Normal3fv)( GLcontext *, int ); 624 struct dynfn *(*TexCoord2f)( GLcontext *, int ); 625 struct dynfn *(*TexCoord2fv)( GLcontext *, int ); 626 struct dynfn *(*TexCoord1f)( GLcontext *, int ); 627 struct dynfn *(*TexCoord1fv)( GLcontext *, int ); 628 struct dynfn *(*MultiTexCoord2fARB)( GLcontext *, int ); 629 struct dynfn *(*MultiTexCoord2fvARB)( GLcontext *, int ); 630 struct dynfn *(*MultiTexCoord1fARB)( GLcontext *, int ); 631 struct dynfn *(*MultiTexCoord1fvARB)( GLcontext *, int ); 632}; 633 634 635 636struct radeon_prim { 637 GLuint start; 638 GLuint end; 639 GLuint prim; 640}; 641 642struct radeon_vbinfo { 643 GLint counter, initial_counter; 644 GLint *dmaptr; 645 void (*notify)( void ); 646 GLint vertex_size; 647 648 /* A maximum total of 15 elements per vertex: 3 floats for position, 3 649 * floats for normal, 4 floats for color, 4 bytes for secondary color, 650 * 2 floats for each texture unit (4 floats total). 651 * 652 * As soon as the 3rd TMU is supported or cube maps (or 3D textures) are 653 * supported, this value will grow. 654 * 655 * The position data is never actually stored here, so 3 elements could be 656 * trimmed out of the buffer. 657 */ 658 union { float f; int i; radeon_color_t color; } vertex[15]; 659 660 GLfloat *normalptr; 661 GLfloat *floatcolorptr; 662 radeon_color_t *colorptr; 663 GLfloat *floatspecptr; 664 radeon_color_t *specptr; 665 GLfloat *texcoordptr[2]; 666 667 GLenum *prim; /* &ctx->Driver.CurrentExecPrimitive */ 668 GLuint primflags; 669 GLboolean enabled; /* *_NO_VTXFMT / *_NO_TCL env vars */ 670 GLboolean installed; 671 GLboolean fell_back; 672 GLboolean recheck; 673 GLint nrverts; 674 GLuint vertex_format; 675 676 GLuint installed_vertex_format; 677 GLuint installed_color_3f_sz; 678 679 struct radeon_prim primlist[RADEON_MAX_PRIMS]; 680 int nrprims; 681 682 struct dfn_lists dfn_cache; 683 struct dfn_generators codegen; 684 GLvertexformat vtxfmt; 685}; 686 687 688 689 690struct radeon_context { 691 GLcontext *glCtx; /* Mesa context */ 692 693 /* Driver and hardware state management 694 */ 695 struct radeon_hw_state hw; 696 struct radeon_state state; 697 698 /* Texture object bookkeeping 699 */ 700 unsigned nr_heaps; 701 driTexHeap * texture_heaps[ RADEON_NR_TEX_HEAPS ]; 702 driTextureObject swapped; 703 int texture_depth; 704 float initialMaxAnisotropy; 705 706 /* Rasterization and vertex state: 707 */ 708 GLuint TclFallback; 709 GLuint Fallback; 710 GLuint NewGLState; 711 712 /* Vertex buffers 713 */ 714 struct radeon_ioctl ioctl; 715 struct radeon_dma dma; 716 struct radeon_store store; 717 718 /* Page flipping 719 */ 720 GLuint doPageFlip; 721 722 /* Busy waiting 723 */ 724 GLuint do_usleeps; 725 GLuint do_irqs; 726 GLuint irqsEmitted; 727 drm_radeon_irq_wait_t iw; 728 729 /* Drawable, cliprect and scissor information 730 */ 731 GLuint numClipRects; /* Cliprects for the draw buffer */ 732 drm_clip_rect_t *pClipRects; 733 unsigned int lastStamp; 734 GLboolean lost_context; 735 radeonScreenPtr radeonScreen; /* Screen private DRI data */ 736 drm_radeon_sarea_t *sarea; /* Private SAREA data */ 737 738 /* TCL stuff 739 */ 740 GLmatrix TexGenMatrix[RADEON_MAX_TEXTURE_UNITS]; 741 GLboolean recheck_texgen[RADEON_MAX_TEXTURE_UNITS]; 742 GLboolean TexGenNeedNormals[RADEON_MAX_TEXTURE_UNITS]; 743 GLuint TexMatEnabled; 744 GLuint TexGenEnabled; 745 GLmatrix tmpmat; 746 GLuint last_ReallyEnabled; 747 748 /* VBI 749 */ 750 GLuint vbl_seq; 751 GLuint vblank_flags; 752 753 int64_t swap_ust; 754 int64_t swap_missed_ust; 755 756 GLuint swap_count; 757 GLuint swap_missed_count; 758 759 PFNGLXGETUSTPROC get_ust; 760 761 /* radeon_tcl.c 762 */ 763 struct radeon_tcl_info tcl; 764 765 /* radeon_swtcl.c 766 */ 767 struct radeon_swtcl_info swtcl; 768 769 /* radeon_vtxfmt.c 770 */ 771 struct radeon_vbinfo vb; 772 773 /* Mirrors of some DRI state 774 */ 775 struct radeon_dri_mirror dri; 776 777 /* Configuration cache 778 */ 779 driOptionCache optionCache; 780 781 782 /* Performance counters 783 */ 784 GLuint boxes; /* Draw performance boxes */ 785 GLuint hardwareWentIdle; 786 GLuint c_clears; 787 GLuint c_drawWaits; 788 GLuint c_textureSwaps; 789 GLuint c_textureBytes; 790 GLuint c_vertexBuffers; 791}; 792 793#define RADEON_CONTEXT(ctx) ((radeonContextPtr)(ctx->DriverCtx)) 794 795 796static __inline GLuint radeonPackColor( GLuint cpp, 797 GLubyte r, GLubyte g, 798 GLubyte b, GLubyte a ) 799{ 800 switch ( cpp ) { 801 case 2: 802 return PACK_COLOR_565( r, g, b ); 803 case 4: 804 return PACK_COLOR_8888( a, r, g, b ); 805 default: 806 return 0; 807 } 808} 809 810#define RADEON_OLD_PACKETS 1 811 812 813extern void radeonDestroyContext( __DRIcontextPrivate *driContextPriv ); 814extern GLboolean radeonCreateContext(const __GLcontextModes *glVisual, 815 __DRIcontextPrivate *driContextPriv, 816 void *sharedContextPrivate); 817extern void radeonSwapBuffers( __DRIdrawablePrivate *dPriv ); 818extern GLboolean radeonMakeCurrent( __DRIcontextPrivate *driContextPriv, 819 __DRIdrawablePrivate *driDrawPriv, 820 __DRIdrawablePrivate *driReadPriv ); 821extern GLboolean radeonUnbindContext( __DRIcontextPrivate *driContextPriv ); 822 823/* ================================================================ 824 * Debugging: 825 */ 826#define DO_DEBUG 1 827 828#if DO_DEBUG 829extern int RADEON_DEBUG; 830#else 831#define RADEON_DEBUG 0 832#endif 833 834#define DEBUG_TEXTURE 0x001 835#define DEBUG_STATE 0x002 836#define DEBUG_IOCTL 0x004 837#define DEBUG_PRIMS 0x008 838#define DEBUG_VERTS 0x010 839#define DEBUG_FALLBACKS 0x020 840#define DEBUG_VFMT 0x040 841#define DEBUG_CODEGEN 0x080 842#define DEBUG_VERBOSE 0x100 843#define DEBUG_DRI 0x200 844#define DEBUG_DMA 0x400 845#define DEBUG_SANITY 0x800 846 847#endif 848#endif /* __RADEON_CONTEXT_H__ */ 849