176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com> 376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org> 476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Copyright (c) 2007-2008 Michael Taylor <mike.taylor@apprion.com> 576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Permission to use, copy, modify, and distribute this software for any 776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * purpose with or without fee is hereby granted, provided that the above 876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * copyright notice and this permission notice appear in all copies. 976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 1076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 1176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 1276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 1376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 1476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 1576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 1676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 1776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 1876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 1976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 2076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 2176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Register values for Atheros 5210/5211/5212 cards from OpenBSD's ar5k 2276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * maintained by Reyk Floeter 2376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 2476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * I tried to document those registers by looking at ar5k code, some 2576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 802.11 (802.11e mostly) papers and by reading various public available 2676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Atheros presentations and papers like these: 2776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 2876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 5210 - http://nova.stanford.edu/~bbaas/ps/isscc2002_slides.pdf 2976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * http://www.it.iitb.ac.in/~janak/wifire/01222734.pdf 3076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 3176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 5211 - http://www.hotchips.org/archives/hc14/3_Tue/16_mcfarland.pdf 3276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 3376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * This file also contains register values found on a memory dump of 3476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Atheros's ART program (Atheros Radio Test), on ath9k, on legacy-hal 3576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * released by Atheros and on various debug messages found on the net. 3676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 3776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 3876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 3976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 4076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/*====MAC DMA REGISTERS====*/ 4176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 4276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 4376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * AR5210-Specific TXDP registers 4476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 5210 has only 2 transmit queues so no DCU/QCU, just 4576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 2 transmit descriptor pointers... 4676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 4776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_NOQCU_TXDP0 0x0000 /* Queue 0 - data */ 4876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_NOQCU_TXDP1 0x0004 /* Queue 1 - beacons */ 4976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 5076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 5176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Mac Control Register 5276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 5376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_CR 0x0008 /* Register Address */ 5476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_CR_TXE0 0x00000001 /* TX Enable for queue 0 on 5210 */ 5576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_CR_TXE1 0x00000002 /* TX Enable for queue 1 on 5210 */ 5676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_CR_RXE 0x00000004 /* RX Enable */ 5776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_CR_TXD0 0x00000008 /* TX Disable for queue 0 on 5210 */ 5876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_CR_TXD1 0x00000010 /* TX Disable for queue 1 on 5210 */ 5976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_CR_RXD 0x00000020 /* RX Disable */ 6076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_CR_SWI 0x00000040 /* Software Interrupt */ 6176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 6276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 6376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * RX Descriptor Pointer register 6476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 6576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RXDP 0x000c 6676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 6776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 6876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Configuration and status register 6976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 7076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_CFG 0x0014 /* Register Address */ 7176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_CFG_SWTD 0x00000001 /* Byte-swap TX descriptor (for big endian archs) */ 7276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_CFG_SWTB 0x00000002 /* Byte-swap TX buffer */ 7376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_CFG_SWRD 0x00000004 /* Byte-swap RX descriptor */ 7476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_CFG_SWRB 0x00000008 /* Byte-swap RX buffer */ 7576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_CFG_SWRG 0x00000010 /* Byte-swap Register access */ 7676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_CFG_IBSS 0x00000020 /* 0-BSS, 1-IBSS [5211+] */ 7776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_CFG_PHY_OK 0x00000100 /* [5211+] */ 7876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_CFG_EEBS 0x00000200 /* EEPROM is busy */ 7976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_CFG_CLKGD 0x00000400 /* Clock gated (Disable dynamic clock) */ 8076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_CFG_TXCNT 0x00007800 /* Tx frame count (?) [5210] */ 8176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_CFG_TXCNT_S 11 8276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_CFG_TXFSTAT 0x00008000 /* Tx frame status (?) [5210] */ 8376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_CFG_TXFSTRT 0x00010000 /* [5210] */ 8476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_CFG_PCI_THRES 0x00060000 /* PCI Master req q threshold [5211+] */ 8576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_CFG_PCI_THRES_S 17 8676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 8776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 8876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Interrupt enable register 8976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 9076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_IER 0x0024 /* Register Address */ 9176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_IER_DISABLE 0x00000000 /* Disable card interrupts */ 9276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_IER_ENABLE 0x00000001 /* Enable card interrupts */ 9376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 9476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 9576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 9676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 0x0028 is Beacon Control Register on 5210 9776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * and first RTS duration register on 5211 9876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 9976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 10076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 10176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Beacon control register [5210] 10276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 10376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_BCR 0x0028 /* Register Address */ 10476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_BCR_AP 0x00000000 /* AP mode */ 10576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_BCR_ADHOC 0x00000001 /* Ad-Hoc mode */ 10676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_BCR_BDMAE 0x00000002 /* DMA enable */ 10776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_BCR_TQ1FV 0x00000004 /* Use Queue1 for CAB traffic */ 10876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_BCR_TQ1V 0x00000008 /* Use Queue1 for Beacon traffic */ 10976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_BCR_BCGET 0x00000010 11076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 11176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 11276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * First RTS duration register [5211] 11376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 11476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RTSD0 0x0028 /* Register Address */ 11576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RTSD0_6 0x000000ff /* 6Mb RTS duration mask (?) */ 11676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RTSD0_6_S 0 /* 6Mb RTS duration shift (?) */ 11776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RTSD0_9 0x0000ff00 /* 9Mb*/ 11876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RTSD0_9_S 8 11976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RTSD0_12 0x00ff0000 /* 12Mb*/ 12076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RTSD0_12_S 16 12176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RTSD0_18 0xff000000 /* 16Mb*/ 12276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RTSD0_18_S 24 12376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 12476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 12576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 12676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 0x002c is Beacon Status Register on 5210 12776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * and second RTS duration register on 5211 12876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 12976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 13076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 13176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Beacon status register [5210] 13276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 13376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * As i can see in ar5k_ar5210_tx_start Reyk uses some of the values of BCR 13476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * for this register, so i guess TQ1V,TQ1FV and BDMAE have the same meaning 13576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * here and SNP/SNAP means "snapshot" (so this register gets synced with BCR). 13676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * So SNAPPEDBCRVALID sould also stand for "snapped BCR -values- valid", so i 13776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * renamed it to SNAPSHOTSVALID to make more sense. I realy have no idea what 13876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * else can it be. I also renamed SNPBCMD to SNPADHOC to match BCR. 13976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 14076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_BSR 0x002c /* Register Address */ 14176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_BSR_BDLYSW 0x00000001 /* SW Beacon delay (?) */ 14276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_BSR_BDLYDMA 0x00000002 /* DMA Beacon delay (?) */ 14376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_BSR_TXQ1F 0x00000004 /* Beacon queue (1) finished */ 14476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_BSR_ATIMDLY 0x00000008 /* ATIM delay (?) */ 14576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_BSR_SNPADHOC 0x00000100 /* Ad-hoc mode set (?) */ 14676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_BSR_SNPBDMAE 0x00000200 /* Beacon DMA enabled (?) */ 14776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_BSR_SNPTQ1FV 0x00000400 /* Queue1 is used for CAB traffic (?) */ 14876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_BSR_SNPTQ1V 0x00000800 /* Queue1 is used for Beacon traffic (?) */ 14976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_BSR_SNAPSHOTSVALID 0x00001000 /* BCR snapshots are valid (?) */ 15076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_BSR_SWBA_CNT 0x00ff0000 15176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 15276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 15376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Second RTS duration register [5211] 15476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 15576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RTSD1 0x002c /* Register Address */ 15676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RTSD1_24 0x000000ff /* 24Mb */ 15776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RTSD1_24_S 0 15876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RTSD1_36 0x0000ff00 /* 36Mb */ 15976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RTSD1_36_S 8 16076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RTSD1_48 0x00ff0000 /* 48Mb */ 16176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RTSD1_48_S 16 16276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RTSD1_54 0xff000000 /* 54Mb */ 16376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RTSD1_54_S 24 16476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 16576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 16676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 16776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Transmit configuration register 16876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 16976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TXCFG 0x0030 /* Register Address */ 17076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TXCFG_SDMAMR 0x00000007 /* DMA size (read) */ 17176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TXCFG_SDMAMR_S 0 17276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TXCFG_B_MODE 0x00000008 /* Set b mode for 5111 (enable 2111) */ 17376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TXCFG_TXFSTP 0x00000008 /* TX DMA full Stop [5210] */ 17476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TXCFG_TXFULL 0x000003f0 /* TX Triger level mask */ 17576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TXCFG_TXFULL_S 4 17676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TXCFG_TXFULL_0B 0x00000000 17776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TXCFG_TXFULL_64B 0x00000010 17876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TXCFG_TXFULL_128B 0x00000020 17976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TXCFG_TXFULL_192B 0x00000030 18076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TXCFG_TXFULL_256B 0x00000040 18176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TXCFG_TXCONT_EN 0x00000080 18276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TXCFG_DMASIZE 0x00000100 /* Flag for passing DMA size [5210] */ 18376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TXCFG_JUMBO_DESC_EN 0x00000400 /* Enable jumbo tx descriptors [5211+] */ 18476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TXCFG_ADHOC_BCN_ATIM 0x00000800 /* Adhoc Beacon ATIM Policy */ 18576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TXCFG_ATIM_WINDOW_DEF_DIS 0x00001000 /* Disable ATIM window defer [5211+] */ 18676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TXCFG_RTSRND 0x00001000 /* [5211+] */ 18776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TXCFG_FRMPAD_DIS 0x00002000 /* [5211+] */ 18876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TXCFG_RDY_CBR_DIS 0x00004000 /* Ready time CBR disable [5211+] */ 18976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TXCFG_JUMBO_FRM_MODE 0x00008000 /* Jumbo frame mode [5211+] */ 19076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TXCFG_DCU_DBL_BUF_DIS 0x00008000 /* Disable double buffering on DCU */ 19176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TXCFG_DCU_CACHING_DIS 0x00010000 /* Disable DCU caching */ 19276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 19376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 19476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Receive configuration register 19576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 19676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RXCFG 0x0034 /* Register Address */ 19776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RXCFG_SDMAMW 0x00000007 /* DMA size (write) */ 19876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RXCFG_SDMAMW_S 0 19976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RXCFG_ZLFDMA 0x00000008 /* Enable Zero-length frame DMA */ 20076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RXCFG_DEF_ANTENNA 0x00000010 /* Default antenna (?) */ 20176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RXCFG_JUMBO_RXE 0x00000020 /* Enable jumbo rx descriptors [5211+] */ 20276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RXCFG_JUMBO_WRAP 0x00000040 /* Wrap jumbo frames [5211+] */ 20376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RXCFG_SLE_ENTRY 0x00000080 /* Sleep entry policy */ 20476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 20576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 20676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Receive jumbo descriptor last address register 20776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Only found in 5211 (?) 20876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 20976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RXJLA 0x0038 21076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 21176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 21276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * MIB control register 21376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 21476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_MIBC 0x0040 /* Register Address */ 21576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_MIBC_COW 0x00000001 /* Warn test indicator */ 21676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_MIBC_FMC 0x00000002 /* Freeze MIB Counters */ 21776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_MIBC_CMC 0x00000004 /* Clean MIB Counters */ 21876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_MIBC_MCS 0x00000008 /* MIB counter strobe */ 21976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 22076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 22176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Timeout prescale register 22276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 22376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TOPS 0x0044 22476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TOPS_M 0x0000ffff 22576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 22676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 22776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Receive timeout register (no frame received) 22876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 22976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RXNOFRM 0x0048 23076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RXNOFRM_M 0x000003ff 23176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 23276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 23376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Transmit timeout register (no frame sent) 23476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 23576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TXNOFRM 0x004c 23676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TXNOFRM_M 0x000003ff 23776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TXNOFRM_QCU 0x000ffc00 23876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TXNOFRM_QCU_S 10 23976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 24076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 24176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Receive frame gap timeout register 24276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 24376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RPGTO 0x0050 24476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RPGTO_M 0x000003ff 24576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 24676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 24776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Receive frame count limit register 24876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 24976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RFCNT 0x0054 25076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RFCNT_M 0x0000001f /* [5211+] (?) */ 25176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RFCNT_RFCL 0x0000000f /* [5210] */ 25276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 25376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 25476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Misc settings register 25576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * (reserved0-3) 25676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 25776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_MISC 0x0058 /* Register Address */ 25876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_MISC_DMA_OBS_M 0x000001e0 25976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_MISC_DMA_OBS_S 5 26076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_MISC_MISC_OBS_M 0x00000e00 26176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_MISC_MISC_OBS_S 9 26276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_MISC_MAC_OBS_LSB_M 0x00007000 26376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_MISC_MAC_OBS_LSB_S 12 26476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_MISC_MAC_OBS_MSB_M 0x00038000 26576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_MISC_MAC_OBS_MSB_S 15 26676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_MISC_LED_DECAY 0x001c0000 /* [5210] */ 26776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_MISC_LED_BLINK 0x00e00000 /* [5210] */ 26876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 26976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 27076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * QCU/DCU clock gating register (5311) 27176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * (reserved4-5) 27276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 27376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QCUDCU_CLKGT 0x005c /* Register Address (?) */ 27476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QCUDCU_CLKGT_QCU 0x0000ffff /* Mask for QCU clock */ 27576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QCUDCU_CLKGT_DCU 0x07ff0000 /* Mask for DCU clock */ 27676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 27776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 27876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Interrupt Status Registers 27976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 28076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * For 5210 there is only one status register but for 28176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 5211/5212 we have one primary and 4 secondary registers. 28276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * So we have AR5K_ISR for 5210 and AR5K_PISR /SISRx for 5211/5212. 28376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Most of these bits are common for all chipsets. 28476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 28576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_ISR 0x001c /* Register Address [5210] */ 28676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PISR 0x0080 /* Register Address [5211+] */ 28776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_ISR_RXOK 0x00000001 /* Frame successfuly recieved */ 28876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_ISR_RXDESC 0x00000002 /* RX descriptor request */ 28976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_ISR_RXERR 0x00000004 /* Receive error */ 29076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_ISR_RXNOFRM 0x00000008 /* No frame received (receive timeout) */ 29176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_ISR_RXEOL 0x00000010 /* Empty RX descriptor */ 29276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_ISR_RXORN 0x00000020 /* Receive FIFO overrun */ 29376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_ISR_TXOK 0x00000040 /* Frame successfuly transmited */ 29476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_ISR_TXDESC 0x00000080 /* TX descriptor request */ 29576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_ISR_TXERR 0x00000100 /* Transmit error */ 29676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_ISR_TXNOFRM 0x00000200 /* No frame transmited (transmit timeout) */ 29776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_ISR_TXEOL 0x00000400 /* Empty TX descriptor */ 29876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_ISR_TXURN 0x00000800 /* Transmit FIFO underrun */ 29976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_ISR_MIB 0x00001000 /* Update MIB counters */ 30076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_ISR_SWI 0x00002000 /* Software interrupt */ 30176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_ISR_RXPHY 0x00004000 /* PHY error */ 30276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_ISR_RXKCM 0x00008000 /* RX Key cache miss */ 30376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_ISR_SWBA 0x00010000 /* Software beacon alert */ 30476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_ISR_BRSSI 0x00020000 /* Beacon rssi below threshold (?) */ 30576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_ISR_BMISS 0x00040000 /* Beacon missed */ 30676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_ISR_HIUERR 0x00080000 /* Host Interface Unit error [5211+] */ 30776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_ISR_BNR 0x00100000 /* Beacon not ready [5211+] */ 30876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_ISR_MCABT 0x00100000 /* Master Cycle Abort [5210] */ 30976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_ISR_RXCHIRP 0x00200000 /* CHIRP Received [5212+] */ 31076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_ISR_SSERR 0x00200000 /* Signaled System Error [5210] */ 31176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_ISR_DPERR 0x00400000 /* Det par Error (?) [5210] */ 31276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_ISR_RXDOPPLER 0x00400000 /* Doppler chirp received [5212+] */ 31376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_ISR_TIM 0x00800000 /* [5211+] */ 31476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_ISR_BCNMISC 0x00800000 /* 'or' of TIM, CAB_END, DTIM_SYNC, BCN_TIMEOUT, 31576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman CAB_TIMEOUT and DTIM bits from SISR2 [5212+] */ 31676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_ISR_GPIO 0x01000000 /* GPIO (rf kill) */ 31776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_ISR_QCBRORN 0x02000000 /* QCU CBR overrun [5211+] */ 31876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_ISR_QCBRURN 0x04000000 /* QCU CBR underrun [5211+] */ 31976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_ISR_QTRIG 0x08000000 /* QCU scheduling trigger [5211+] */ 32076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 32176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 32276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Secondary status registers [5211+] (0 - 4) 32376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 32476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * These give the status for each QCU, only QCUs 0-9 are 32576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * represented. 32676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 32776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SISR0 0x0084 /* Register Address [5211+] */ 32876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SISR0_QCU_TXOK 0x000003ff /* Mask for QCU_TXOK */ 32976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SISR0_QCU_TXOK_S 0 33076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SISR0_QCU_TXDESC 0x03ff0000 /* Mask for QCU_TXDESC */ 33176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SISR0_QCU_TXDESC_S 16 33276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 33376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SISR1 0x0088 /* Register Address [5211+] */ 33476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SISR1_QCU_TXERR 0x000003ff /* Mask for QCU_TXERR */ 33576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SISR1_QCU_TXERR_S 0 33676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SISR1_QCU_TXEOL 0x03ff0000 /* Mask for QCU_TXEOL */ 33776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SISR1_QCU_TXEOL_S 16 33876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 33976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SISR2 0x008c /* Register Address [5211+] */ 34076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SISR2_QCU_TXURN 0x000003ff /* Mask for QCU_TXURN */ 34176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SISR2_QCU_TXURN_S 0 34276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SISR2_MCABT 0x00100000 /* Master Cycle Abort */ 34376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SISR2_SSERR 0x00200000 /* Signaled System Error */ 34476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SISR2_DPERR 0x00400000 /* Bus parity error */ 34576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SISR2_TIM 0x01000000 /* [5212+] */ 34676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SISR2_CAB_END 0x02000000 /* [5212+] */ 34776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SISR2_DTIM_SYNC 0x04000000 /* DTIM sync lost [5212+] */ 34876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SISR2_BCN_TIMEOUT 0x08000000 /* Beacon Timeout [5212+] */ 34976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SISR2_CAB_TIMEOUT 0x10000000 /* CAB Timeout [5212+] */ 35076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SISR2_DTIM 0x20000000 /* [5212+] */ 35176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SISR2_TSFOOR 0x80000000 /* TSF OOR (?) */ 35276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 35376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SISR3 0x0090 /* Register Address [5211+] */ 35476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SISR3_QCBRORN 0x000003ff /* Mask for QCBRORN */ 35576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SISR3_QCBRORN_S 0 35676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SISR3_QCBRURN 0x03ff0000 /* Mask for QCBRURN */ 35776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SISR3_QCBRURN_S 16 35876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 35976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SISR4 0x0094 /* Register Address [5211+] */ 36076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SISR4_QTRIG 0x000003ff /* Mask for QTRIG */ 36176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SISR4_QTRIG_S 0 36276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 36376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 36476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Shadow read-and-clear interrupt status registers [5211+] 36576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 36676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RAC_PISR 0x00c0 /* Read and clear PISR */ 36776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RAC_SISR0 0x00c4 /* Read and clear SISR0 */ 36876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RAC_SISR1 0x00c8 /* Read and clear SISR1 */ 36976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RAC_SISR2 0x00cc /* Read and clear SISR2 */ 37076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RAC_SISR3 0x00d0 /* Read and clear SISR3 */ 37176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RAC_SISR4 0x00d4 /* Read and clear SISR4 */ 37276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 37376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 37476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Interrupt Mask Registers 37576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 37676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * As whith ISRs 5210 has one IMR (AR5K_IMR) and 5211/5212 has one primary 37776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * (AR5K_PIMR) and 4 secondary IMRs (AR5K_SIMRx). Note that ISR/IMR flags match. 37876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 37976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_IMR 0x0020 /* Register Address [5210] */ 38076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PIMR 0x00a0 /* Register Address [5211+] */ 38176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_IMR_RXOK 0x00000001 /* Frame successfuly recieved*/ 38276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_IMR_RXDESC 0x00000002 /* RX descriptor request*/ 38376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_IMR_RXERR 0x00000004 /* Receive error*/ 38476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_IMR_RXNOFRM 0x00000008 /* No frame received (receive timeout)*/ 38576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_IMR_RXEOL 0x00000010 /* Empty RX descriptor*/ 38676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_IMR_RXORN 0x00000020 /* Receive FIFO overrun*/ 38776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_IMR_TXOK 0x00000040 /* Frame successfuly transmited*/ 38876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_IMR_TXDESC 0x00000080 /* TX descriptor request*/ 38976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_IMR_TXERR 0x00000100 /* Transmit error*/ 39076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_IMR_TXNOFRM 0x00000200 /* No frame transmited (transmit timeout)*/ 39176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_IMR_TXEOL 0x00000400 /* Empty TX descriptor*/ 39276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_IMR_TXURN 0x00000800 /* Transmit FIFO underrun*/ 39376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_IMR_MIB 0x00001000 /* Update MIB counters*/ 39476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_IMR_SWI 0x00002000 /* Software interrupt */ 39576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_IMR_RXPHY 0x00004000 /* PHY error*/ 39676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_IMR_RXKCM 0x00008000 /* RX Key cache miss */ 39776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_IMR_SWBA 0x00010000 /* Software beacon alert*/ 39876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_IMR_BRSSI 0x00020000 /* Beacon rssi below threshold (?) */ 39976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_IMR_BMISS 0x00040000 /* Beacon missed*/ 40076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_IMR_HIUERR 0x00080000 /* Host Interface Unit error [5211+] */ 40176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_IMR_BNR 0x00100000 /* Beacon not ready [5211+] */ 40276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_IMR_MCABT 0x00100000 /* Master Cycle Abort [5210] */ 40376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_IMR_RXCHIRP 0x00200000 /* CHIRP Received [5212+]*/ 40476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_IMR_SSERR 0x00200000 /* Signaled System Error [5210] */ 40576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_IMR_DPERR 0x00400000 /* Det par Error (?) [5210] */ 40676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_IMR_RXDOPPLER 0x00400000 /* Doppler chirp received [5212+] */ 40776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_IMR_TIM 0x00800000 /* [5211+] */ 40876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_IMR_BCNMISC 0x00800000 /* 'or' of TIM, CAB_END, DTIM_SYNC, BCN_TIMEOUT, 40976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman CAB_TIMEOUT and DTIM bits from SISR2 [5212+] */ 41076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_IMR_GPIO 0x01000000 /* GPIO (rf kill)*/ 41176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_IMR_QCBRORN 0x02000000 /* QCU CBR overrun (?) [5211+] */ 41276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_IMR_QCBRURN 0x04000000 /* QCU CBR underrun (?) [5211+] */ 41376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_IMR_QTRIG 0x08000000 /* QCU scheduling trigger [5211+] */ 41476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 41576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 41676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Secondary interrupt mask registers [5211+] (0 - 4) 41776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 41876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SIMR0 0x00a4 /* Register Address [5211+] */ 41976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SIMR0_QCU_TXOK 0x000003ff /* Mask for QCU_TXOK */ 42076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SIMR0_QCU_TXOK_S 0 42176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SIMR0_QCU_TXDESC 0x03ff0000 /* Mask for QCU_TXDESC */ 42276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SIMR0_QCU_TXDESC_S 16 42376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 42476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SIMR1 0x00a8 /* Register Address [5211+] */ 42576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SIMR1_QCU_TXERR 0x000003ff /* Mask for QCU_TXERR */ 42676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SIMR1_QCU_TXERR_S 0 42776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SIMR1_QCU_TXEOL 0x03ff0000 /* Mask for QCU_TXEOL */ 42876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SIMR1_QCU_TXEOL_S 16 42976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 43076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SIMR2 0x00ac /* Register Address [5211+] */ 43176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SIMR2_QCU_TXURN 0x000003ff /* Mask for QCU_TXURN */ 43276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SIMR2_QCU_TXURN_S 0 43376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SIMR2_MCABT 0x00100000 /* Master Cycle Abort */ 43476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SIMR2_SSERR 0x00200000 /* Signaled System Error */ 43576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SIMR2_DPERR 0x00400000 /* Bus parity error */ 43676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SIMR2_TIM 0x01000000 /* [5212+] */ 43776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SIMR2_CAB_END 0x02000000 /* [5212+] */ 43876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SIMR2_DTIM_SYNC 0x04000000 /* DTIM Sync lost [5212+] */ 43976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SIMR2_BCN_TIMEOUT 0x08000000 /* Beacon Timeout [5212+] */ 44076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SIMR2_CAB_TIMEOUT 0x10000000 /* CAB Timeout [5212+] */ 44176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SIMR2_DTIM 0x20000000 /* [5212+] */ 44276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SIMR2_TSFOOR 0x80000000 /* TSF OOR (?) */ 44376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 44476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SIMR3 0x00b0 /* Register Address [5211+] */ 44576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SIMR3_QCBRORN 0x000003ff /* Mask for QCBRORN */ 44676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SIMR3_QCBRORN_S 0 44776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SIMR3_QCBRURN 0x03ff0000 /* Mask for QCBRURN */ 44876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SIMR3_QCBRURN_S 16 44976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 45076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SIMR4 0x00b4 /* Register Address [5211+] */ 45176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SIMR4_QTRIG 0x000003ff /* Mask for QTRIG */ 45276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SIMR4_QTRIG_S 0 45376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 45476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 45576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * DMA Debug registers 0-7 45676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 0xe0 - 0xfc 45776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 45876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 45976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 46076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Decompression mask registers [5212+] 46176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 46276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCM_ADDR 0x0400 /*Decompression mask address (index) */ 46376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCM_DATA 0x0404 /*Decompression mask data */ 46476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 46576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 46676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Wake On Wireless pattern control register [5212+] 46776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 46876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_WOW_PCFG 0x0410 /* Register Address */ 46976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_WOW_PCFG_PAT_MATCH_EN 0x00000001 /* Pattern match enable */ 47076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_WOW_PCFG_LONG_FRAME_POL 0x00000002 /* Long frame policy */ 47176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_WOW_PCFG_WOBMISS 0x00000004 /* Wake on bea(con) miss (?) */ 47276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_WOW_PCFG_PAT_0_EN 0x00000100 /* Enable pattern 0 */ 47376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_WOW_PCFG_PAT_1_EN 0x00000200 /* Enable pattern 1 */ 47476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_WOW_PCFG_PAT_2_EN 0x00000400 /* Enable pattern 2 */ 47576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_WOW_PCFG_PAT_3_EN 0x00000800 /* Enable pattern 3 */ 47676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_WOW_PCFG_PAT_4_EN 0x00001000 /* Enable pattern 4 */ 47776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_WOW_PCFG_PAT_5_EN 0x00002000 /* Enable pattern 5 */ 47876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 47976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 48076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Wake On Wireless pattern index register (?) [5212+] 48176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 48276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_WOW_PAT_IDX 0x0414 48376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 48476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 48576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Wake On Wireless pattern data register [5212+] 48676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 48776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_WOW_PAT_DATA 0x0418 /* Register Address */ 48876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_WOW_PAT_DATA_0_3_V 0x00000001 /* Pattern 0, 3 value */ 48976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_WOW_PAT_DATA_1_4_V 0x00000100 /* Pattern 1, 4 value */ 49076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_WOW_PAT_DATA_2_5_V 0x00010000 /* Pattern 2, 5 value */ 49176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_WOW_PAT_DATA_0_3_M 0x01000000 /* Pattern 0, 3 mask */ 49276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_WOW_PAT_DATA_1_4_M 0x04000000 /* Pattern 1, 4 mask */ 49376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_WOW_PAT_DATA_2_5_M 0x10000000 /* Pattern 2, 5 mask */ 49476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 49576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 49676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Decompression configuration registers [5212+] 49776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 49876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCCFG 0x0420 /* Register Address */ 49976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCCFG_GLOBAL_EN 0x00000001 /* Enable decompression on all queues */ 50076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCCFG_BYPASS_EN 0x00000002 /* Bypass decompression */ 50176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCCFG_BCAST_EN 0x00000004 /* Enable decompression for bcast frames */ 50276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCCFG_MCAST_EN 0x00000008 /* Enable decompression for mcast frames */ 50376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 50476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 50576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Compression configuration registers [5212+] 50676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 50776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_CCFG 0x0600 /* Register Address */ 50876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_CCFG_WINDOW_SIZE 0x00000007 /* Compression window size */ 50976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_CCFG_CPC_EN 0x00000008 /* Enable performance counters */ 51076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 51176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_CCFG_CCU 0x0604 /* Register Address */ 51276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_CCFG_CCU_CUP_EN 0x00000001 /* CCU Catchup enable */ 51376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_CCFG_CCU_CREDIT 0x00000002 /* CCU Credit (field) */ 51476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_CCFG_CCU_CD_THRES 0x00000080 /* CCU Cyc(lic?) debt threshold (field) */ 51576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_CCFG_CCU_CUP_LCNT 0x00010000 /* CCU Catchup lit(?) count */ 51676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_CCFG_CCU_INIT 0x00100200 /* Initial value during reset */ 51776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 51876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 51976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Compression performance counter registers [5212+] 52076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 52176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_CPC0 0x0610 /* Compression performance counter 0 */ 52276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_CPC1 0x0614 /* Compression performance counter 1*/ 52376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_CPC2 0x0618 /* Compression performance counter 2 */ 52476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_CPC3 0x061c /* Compression performance counter 3 */ 52576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_CPCOVF 0x0620 /* Compression performance overflow */ 52676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 52776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 52876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 52976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Queue control unit (QCU) registers [5211+] 53076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 53176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Card has 12 TX Queues but i see that only 0-9 are used (?) 53276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * both in binary HAL (see ah.h) and ar5k. Each queue has it's own 53376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * TXDP at addresses 0x0800 - 0x082c, a CBR (Constant Bit Rate) 53476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * configuration register (0x08c0 - 0x08ec), a ready time configuration 53576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * register (0x0900 - 0x092c), a misc configuration register (0x09c0 - 53676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 0x09ec) and a status register (0x0a00 - 0x0a2c). We also have some 53776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * global registers, QCU transmit enable/disable and "one shot arm (?)" 53876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * set/clear, which contain status for all queues (we shift by 1 for each 53976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * queue). To access these registers easily we define some macros here 54076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * that are used inside HAL. For more infos check out *_tx_queue functs. 54176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 54276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 54376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 54476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Generic QCU Register access macros 54576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 54676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QUEUE_REG(_r, _q) (((_q) << 2) + _r) 54776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QCU_GLOBAL_READ(_r, _q) (AR5K_REG_READ(_r) & (1 << _q)) 54876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QCU_GLOBAL_WRITE(_r, _q) AR5K_REG_WRITE(_r, (1 << _q)) 54976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 55076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 55176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * QCU Transmit descriptor pointer registers 55276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 55376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QCU_TXDP_BASE 0x0800 /* Register Address - Queue0 TXDP */ 55476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QUEUE_TXDP(_q) AR5K_QUEUE_REG(AR5K_QCU_TXDP_BASE, _q) 55576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 55676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 55776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * QCU Transmit enable register 55876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 55976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QCU_TXE 0x0840 56076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_ENABLE_QUEUE(_q) AR5K_QCU_GLOBAL_WRITE(AR5K_QCU_TXE, _q) 56176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QUEUE_ENABLED(_q) AR5K_QCU_GLOBAL_READ(AR5K_QCU_TXE, _q) 56276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 56376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 56476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * QCU Transmit disable register 56576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 56676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QCU_TXD 0x0880 56776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DISABLE_QUEUE(_q) AR5K_QCU_GLOBAL_WRITE(AR5K_QCU_TXD, _q) 56876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QUEUE_DISABLED(_q) AR5K_QCU_GLOBAL_READ(AR5K_QCU_TXD, _q) 56976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 57076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 57176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * QCU Constant Bit Rate configuration registers 57276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 57376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QCU_CBRCFG_BASE 0x08c0 /* Register Address - Queue0 CBRCFG */ 57476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QCU_CBRCFG_INTVAL 0x00ffffff /* CBR Interval mask */ 57576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QCU_CBRCFG_INTVAL_S 0 57676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QCU_CBRCFG_ORN_THRES 0xff000000 /* CBR overrun threshold mask */ 57776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QCU_CBRCFG_ORN_THRES_S 24 57876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QUEUE_CBRCFG(_q) AR5K_QUEUE_REG(AR5K_QCU_CBRCFG_BASE, _q) 57976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 58076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 58176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * QCU Ready time configuration registers 58276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 58376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QCU_RDYTIMECFG_BASE 0x0900 /* Register Address - Queue0 RDYTIMECFG */ 58476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QCU_RDYTIMECFG_INTVAL 0x00ffffff /* Ready time interval mask */ 58576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QCU_RDYTIMECFG_INTVAL_S 0 58676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QCU_RDYTIMECFG_ENABLE 0x01000000 /* Ready time enable mask */ 58776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QUEUE_RDYTIMECFG(_q) AR5K_QUEUE_REG(AR5K_QCU_RDYTIMECFG_BASE, _q) 58876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 58976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 59076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * QCU one shot arm set registers 59176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 59276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QCU_ONESHOTARM_SET 0x0940 /* Register Address -QCU "one shot arm set (?)" */ 59376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QCU_ONESHOTARM_SET_M 0x0000ffff 59476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 59576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 59676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * QCU one shot arm clear registers 59776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 59876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QCU_ONESHOTARM_CLEAR 0x0980 /* Register Address -QCU "one shot arm clear (?)" */ 59976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QCU_ONESHOTARM_CLEAR_M 0x0000ffff 60076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 60176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 60276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * QCU misc registers 60376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 60476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QCU_MISC_BASE 0x09c0 /* Register Address -Queue0 MISC */ 60576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QCU_MISC_FRSHED_M 0x0000000f /* Frame sheduling mask */ 60676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QCU_MISC_FRSHED_ASAP 0 /* ASAP */ 60776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QCU_MISC_FRSHED_CBR 1 /* Constant Bit Rate */ 60876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QCU_MISC_FRSHED_DBA_GT 2 /* DMA Beacon alert gated */ 60976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QCU_MISC_FRSHED_TIM_GT 3 /* TIMT gated */ 61076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QCU_MISC_FRSHED_BCN_SENT_GT 4 /* Beacon sent gated */ 61176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QCU_MISC_ONESHOT_ENABLE 0x00000010 /* Oneshot enable */ 61276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QCU_MISC_CBREXP_DIS 0x00000020 /* Disable CBR expired counter (normal queue) */ 61376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QCU_MISC_CBREXP_BCN_DIS 0x00000040 /* Disable CBR expired counter (beacon queue) */ 61476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QCU_MISC_BCN_ENABLE 0x00000080 /* Enable Beacon use */ 61576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QCU_MISC_CBR_THRES_ENABLE 0x00000100 /* CBR expired threshold enabled */ 61676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QCU_MISC_RDY_VEOL_POLICY 0x00000200 /* TXE reset when RDYTIME expired or VEOL */ 61776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QCU_MISC_CBR_RESET_CNT 0x00000400 /* CBR threshold (counter) reset */ 61876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QCU_MISC_DCU_EARLY 0x00000800 /* DCU early termination */ 61976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QCU_MISC_DCU_CMP_EN 0x00001000 /* Enable frame compression */ 62076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QUEUE_MISC(_q) AR5K_QUEUE_REG(AR5K_QCU_MISC_BASE, _q) 62176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 62276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 62376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 62476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * QCU status registers 62576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 62676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QCU_STS_BASE 0x0a00 /* Register Address - Queue0 STS */ 62776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QCU_STS_FRMPENDCNT 0x00000003 /* Frames pending counter */ 62876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QCU_STS_CBREXPCNT 0x0000ff00 /* CBR expired counter */ 62976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QUEUE_STATUS(_q) AR5K_QUEUE_REG(AR5K_QCU_STS_BASE, _q) 63076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 63176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 63276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * QCU ready time shutdown register 63376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 63476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QCU_RDYTIMESHDN 0x0a40 63576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QCU_RDYTIMESHDN_M 0x000003ff 63676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 63776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 63876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * QCU compression buffer base registers [5212+] 63976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 64076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QCU_CBB_SELECT 0x0b00 64176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QCU_CBB_ADDR 0x0b04 64276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QCU_CBB_ADDR_S 9 64376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 64476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 64576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * QCU compression buffer configuration register [5212+] 64676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * (buffer size) 64776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 64876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QCU_CBCFG 0x0b08 64976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 65076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 65176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 65276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 65376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Distributed Coordination Function (DCF) control unit (DCU) 65476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * registers [5211+] 65576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 65676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * These registers control the various characteristics of each queue 65776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * for 802.11e (WME) combatibility so they go together with 65876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * QCU registers in pairs. For each queue we have a QCU mask register, 65976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * (0x1000 - 0x102c), a local-IFS settings register (0x1040 - 0x106c), 66076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * a retry limit register (0x1080 - 0x10ac), a channel time register 66176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * (0x10c0 - 0x10ec), a misc-settings register (0x1100 - 0x112c) and 66276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * a sequence number register (0x1140 - 0x116c). It seems that "global" 66376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * registers here afect all queues (see use of DCU_GBL_IFS_SLOT in ar5k). 66476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * We use the same macros here for easier register access. 66576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 66676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 66776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 66876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 66976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * DCU QCU mask registers 67076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 67176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_QCUMASK_BASE 0x1000 /* Register Address -Queue0 DCU_QCUMASK */ 67276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_QCUMASK_M 0x000003ff 67376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QUEUE_QCUMASK(_q) AR5K_QUEUE_REG(AR5K_DCU_QCUMASK_BASE, _q) 67476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 67576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 67676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * DCU local Inter Frame Space settings register 67776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 67876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_LCL_IFS_BASE 0x1040 /* Register Address -Queue0 DCU_LCL_IFS */ 67976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_LCL_IFS_CW_MIN 0x000003ff /* Minimum Contention Window */ 68076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_LCL_IFS_CW_MIN_S 0 68176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_LCL_IFS_CW_MAX 0x000ffc00 /* Maximum Contention Window */ 68276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_LCL_IFS_CW_MAX_S 10 68376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_LCL_IFS_AIFS 0x0ff00000 /* Arbitrated Interframe Space */ 68476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_LCL_IFS_AIFS_S 20 68576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_LCL_IFS_AIFS_MAX 0xfc /* Anything above that can cause DCU to hang */ 68676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QUEUE_DFS_LOCAL_IFS(_q) AR5K_QUEUE_REG(AR5K_DCU_LCL_IFS_BASE, _q) 68776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 68876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 68976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * DCU retry limit registers 69076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 69176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_RETRY_LMT_BASE 0x1080 /* Register Address -Queue0 DCU_RETRY_LMT */ 69276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_RETRY_LMT_SH_RETRY 0x0000000f /* Short retry limit mask */ 69376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_RETRY_LMT_SH_RETRY_S 0 69476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_RETRY_LMT_LG_RETRY 0x000000f0 /* Long retry limit mask */ 69576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_RETRY_LMT_LG_RETRY_S 4 69676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_RETRY_LMT_SSH_RETRY 0x00003f00 /* Station short retry limit mask (?) */ 69776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_RETRY_LMT_SSH_RETRY_S 8 69876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_RETRY_LMT_SLG_RETRY 0x000fc000 /* Station long retry limit mask (?) */ 69976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_RETRY_LMT_SLG_RETRY_S 14 70076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QUEUE_DFS_RETRY_LIMIT(_q) AR5K_QUEUE_REG(AR5K_DCU_RETRY_LMT_BASE, _q) 70176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 70276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 70376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * DCU channel time registers 70476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 70576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_CHAN_TIME_BASE 0x10c0 /* Register Address -Queue0 DCU_CHAN_TIME */ 70676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_CHAN_TIME_DUR 0x000fffff /* Channel time duration */ 70776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_CHAN_TIME_DUR_S 0 70876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_CHAN_TIME_ENABLE 0x00100000 /* Enable channel time */ 70976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QUEUE_DFS_CHANNEL_TIME(_q) AR5K_QUEUE_REG(AR5K_DCU_CHAN_TIME_BASE, _q) 71076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 71176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 71276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * DCU misc registers [5211+] 71376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 71476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Note: Arbiter lockout control controls the 71576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * behaviour on low priority queues when we have multiple queues 71676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * with pending frames. Intra-frame lockout means we wait until 71776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * the queue's current frame transmits (with post frame backoff and bursting) 71876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * before we transmit anything else and global lockout means we 71976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * wait for the whole queue to finish before higher priority queues 72076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * can transmit (this is used on beacon and CAB queues). 72176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * No lockout means there is no special handling. 72276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 72376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_MISC_BASE 0x1100 /* Register Address -Queue0 DCU_MISC */ 72476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_MISC_BACKOFF 0x0000003f /* Mask for backoff threshold */ 72576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_MISC_ETS_RTS_POL 0x00000040 /* End of transmission series 72676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman station RTS/data failure count 72776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman reset policy (?) */ 72876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_MISC_ETS_CW_POL 0x00000080 /* End of transmission series 72976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman CW reset policy */ 73076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_MISC_FRAG_WAIT 0x00000100 /* Wait for next fragment */ 73176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_MISC_BACKOFF_FRAG 0x00000200 /* Enable backoff while bursting */ 73276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_MISC_HCFPOLL_ENABLE 0x00000800 /* CF - Poll enable */ 73376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_MISC_BACKOFF_PERSIST 0x00001000 /* Persistent backoff */ 73476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_MISC_FRMPRFTCH_ENABLE 0x00002000 /* Enable frame pre-fetch */ 73576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_MISC_VIRTCOL 0x0000c000 /* Mask for Virtual Collision (?) */ 73676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_MISC_VIRTCOL_NORMAL 0 73776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_MISC_VIRTCOL_IGNORE 1 73876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_MISC_BCN_ENABLE 0x00010000 /* Enable Beacon use */ 73976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_MISC_ARBLOCK_CTL 0x00060000 /* Arbiter lockout control mask */ 74076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_MISC_ARBLOCK_CTL_S 17 74176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_MISC_ARBLOCK_CTL_NONE 0 /* No arbiter lockout */ 74276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_MISC_ARBLOCK_CTL_INTFRM 1 /* Intra-frame lockout */ 74376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL 2 /* Global lockout */ 74476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_MISC_ARBLOCK_IGNORE 0x00080000 /* Ignore Arbiter lockout */ 74576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_MISC_SEQ_NUM_INCR_DIS 0x00100000 /* Disable sequence number increment */ 74676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_MISC_POST_FR_BKOFF_DIS 0x00200000 /* Disable post-frame backoff */ 74776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_MISC_VIRT_COLL_POLICY 0x00400000 /* Virtual Collision cw policy */ 74876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_MISC_BLOWN_IFS_POLICY 0x00800000 /* Blown IFS policy (?) */ 74976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_MISC_SEQNUM_CTL 0x01000000 /* Sequence number control (?) */ 75076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QUEUE_DFS_MISC(_q) AR5K_QUEUE_REG(AR5K_DCU_MISC_BASE, _q) 75176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 75276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 75376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * DCU frame sequence number registers 75476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 75576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_SEQNUM_BASE 0x1140 75676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_SEQNUM_M 0x00000fff 75776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QUEUE_DCU_SEQNUM(_q) AR5K_QUEUE_REG(AR5K_DCU_SEQNUM_BASE, _q) 75876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 75976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 76076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * DCU global IFS SIFS register 76176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 76276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_GBL_IFS_SIFS 0x1030 76376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_GBL_IFS_SIFS_M 0x0000ffff 76476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 76576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 76676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * DCU global IFS slot interval register 76776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 76876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_GBL_IFS_SLOT 0x1070 76976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_GBL_IFS_SLOT_M 0x0000ffff 77076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 77176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 77276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * DCU global IFS EIFS register 77376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 77476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_GBL_IFS_EIFS 0x10b0 77576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_GBL_IFS_EIFS_M 0x0000ffff 77676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 77776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 77876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * DCU global IFS misc register 77976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 78076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * LFSR stands for Linear Feedback Shift Register 78176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * and it's used for generating pseudo-random 78276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * number sequences. 78376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 78476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * (If i understand corectly, random numbers are 78576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * used for idle sensing -multiplied with cwmin/max etc-) 78676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 78776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_GBL_IFS_MISC 0x10f0 /* Register Address */ 78876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_GBL_IFS_MISC_LFSR_SLICE 0x00000007 /* LFSR Slice Select */ 78976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_GBL_IFS_MISC_TURBO_MODE 0x00000008 /* Turbo mode */ 79076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_GBL_IFS_MISC_SIFS_DUR_USEC 0x000003f0 /* SIFS Duration mask */ 79176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_GBL_IFS_MISC_USEC_DUR 0x000ffc00 /* USEC Duration mask */ 79276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_GBL_IFS_MISC_USEC_DUR_S 10 79376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_GBL_IFS_MISC_DCU_ARB_DELAY 0x00300000 /* DCU Arbiter delay mask */ 79476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_GBL_IFS_MISC_SIFS_CNT_RST 0x00400000 /* SIFS cnt reset policy (?) */ 79576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_GBL_IFS_MISC_AIFS_CNT_RST 0x00800000 /* AIFS cnt reset policy (?) */ 79676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_GBL_IFS_MISC_RND_LFSR_SL_DIS 0x01000000 /* Disable random LFSR slice */ 79776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 79876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 79976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * DCU frame prefetch control register 80076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 80176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_FP 0x1230 /* Register Address */ 80276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_FP_NOBURST_DCU_EN 0x00000001 /* Enable non-burst prefetch on DCU (?) */ 80376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_FP_NOBURST_EN 0x00000010 /* Enable non-burst prefetch (?) */ 80476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_FP_BURST_DCU_EN 0x00000020 /* Enable burst prefetch on DCU (?) */ 80576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 80676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 80776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * DCU transmit pause control/status register 80876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 80976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_TXP 0x1270 /* Register Address */ 81076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_TXP_M 0x000003ff /* Tx pause mask */ 81176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_TXP_STATUS 0x00010000 /* Tx pause status */ 81276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 81376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 81476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * DCU transmit filter table 0 (32 entries) 81576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * each entry contains a 32bit slice of the 81676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 128bit tx filter for each DCU (4 slices per DCU) 81776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 81876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_TX_FILTER_0_BASE 0x1038 81976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_TX_FILTER_0(_n) (AR5K_DCU_TX_FILTER_0_BASE + (_n * 64)) 82076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 82176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 82276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * DCU transmit filter table 1 (16 entries) 82376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 82476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_TX_FILTER_1_BASE 0x103c 82576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_TX_FILTER_1(_n) (AR5K_DCU_TX_FILTER_1_BASE + (_n * 64)) 82676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 82776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 82876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * DCU clear transmit filter register 82976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 83076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_TX_FILTER_CLR 0x143c 83176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 83276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 83376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * DCU set transmit filter register 83476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 83576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DCU_TX_FILTER_SET 0x147c 83676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 83776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 83876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Reset control register 83976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 84076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RESET_CTL 0x4000 /* Register Address */ 84176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RESET_CTL_PCU 0x00000001 /* Protocol Control Unit reset */ 84276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RESET_CTL_DMA 0x00000002 /* DMA (Rx/Tx) reset [5210] */ 84376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RESET_CTL_BASEBAND 0x00000002 /* Baseband reset [5211+] */ 84476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RESET_CTL_MAC 0x00000004 /* MAC reset (PCU+Baseband ?) [5210] */ 84576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RESET_CTL_PHY 0x00000008 /* PHY reset [5210] */ 84676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RESET_CTL_PCI 0x00000010 /* PCI Core reset (interrupts etc) */ 84776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 84876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 84976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Sleep control register 85076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 85176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SLEEP_CTL 0x4004 /* Register Address */ 85276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SLEEP_CTL_SLDUR 0x0000ffff /* Sleep duration mask */ 85376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SLEEP_CTL_SLDUR_S 0 85476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SLEEP_CTL_SLE 0x00030000 /* Sleep enable mask */ 85576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SLEEP_CTL_SLE_S 16 85676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SLEEP_CTL_SLE_WAKE 0x00000000 /* Force chip awake */ 85776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SLEEP_CTL_SLE_SLP 0x00010000 /* Force chip sleep */ 85876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SLEEP_CTL_SLE_ALLOW 0x00020000 /* Normal sleep policy */ 85976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SLEEP_CTL_SLE_UNITS 0x00000008 /* [5211+] */ 86076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SLEEP_CTL_DUR_TIM_POL 0x00040000 /* Sleep duration timing policy */ 86176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SLEEP_CTL_DUR_WRITE_POL 0x00080000 /* Sleep duration write policy */ 86276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SLEEP_CTL_SLE_POL 0x00100000 /* Sleep policy mode */ 86376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 86476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 86576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Interrupt pending register 86676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 86776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_INTPEND 0x4008 86876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_INTPEND_M 0x00000001 86976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 87076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 87176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Sleep force register 87276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 87376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SFR 0x400c 87476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SFR_EN 0x00000001 87576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 87676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 87776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * PCI configuration register 87876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * TODO: Fix LED stuff 87976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 88076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PCICFG 0x4010 /* Register Address */ 88176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PCICFG_EEAE 0x00000001 /* Eeprom access enable [5210] */ 88276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PCICFG_SLEEP_CLOCK_EN 0x00000002 /* Enable sleep clock */ 88376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PCICFG_CLKRUNEN 0x00000004 /* CLKRUN enable [5211+] */ 88476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PCICFG_EESIZE 0x00000018 /* Mask for EEPROM size [5211+] */ 88576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PCICFG_EESIZE_S 3 88676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PCICFG_EESIZE_4K 0 /* 4K */ 88776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PCICFG_EESIZE_8K 1 /* 8K */ 88876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PCICFG_EESIZE_16K 2 /* 16K */ 88976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PCICFG_EESIZE_FAIL 3 /* Failed to get size [5211+] */ 89076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PCICFG_LED 0x00000060 /* Led status [5211+] */ 89176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PCICFG_LED_NONE 0x00000000 /* Default [5211+] */ 89276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PCICFG_LED_PEND 0x00000020 /* Scan / Auth pending */ 89376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PCICFG_LED_ASSOC 0x00000040 /* Associated */ 89476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PCICFG_BUS_SEL 0x00000380 /* Mask for "bus select" [5211+] (?) */ 89576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PCICFG_CBEFIX_DIS 0x00000400 /* Disable CBE fix */ 89676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PCICFG_SL_INTEN 0x00000800 /* Enable interrupts when asleep */ 89776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PCICFG_LED_BCTL 0x00001000 /* Led blink (?) [5210] */ 89876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PCICFG_RETRY_FIX 0x00001000 /* Enable pci core retry fix */ 89976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PCICFG_SL_INPEN 0x00002000 /* Sleep even whith pending interrupts*/ 90076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PCICFG_SPWR_DN 0x00010000 /* Mask for power status */ 90176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PCICFG_LEDMODE 0x000e0000 /* Ledmode [5211+] */ 90276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PCICFG_LEDMODE_PROP 0x00000000 /* Blink on standard traffic [5211+] */ 90376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PCICFG_LEDMODE_PROM 0x00020000 /* Default mode (blink on any traffic) [5211+] */ 90476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PCICFG_LEDMODE_PWR 0x00040000 /* Some other blinking mode (?) [5211+] */ 90576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PCICFG_LEDMODE_RAND 0x00060000 /* Random blinking (?) [5211+] */ 90676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PCICFG_LEDBLINK 0x00700000 /* Led blink rate */ 90776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PCICFG_LEDBLINK_S 20 90876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PCICFG_LEDSLOW 0x00800000 /* Slowest led blink rate [5211+] */ 90976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PCICFG_LEDSTATE \ 91076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman (AR5K_PCICFG_LED | AR5K_PCICFG_LEDMODE | \ 91176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman AR5K_PCICFG_LEDBLINK | AR5K_PCICFG_LEDSLOW) 91276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PCICFG_SLEEP_CLOCK_RATE 0x03000000 /* Sleep clock rate */ 91376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PCICFG_SLEEP_CLOCK_RATE_S 24 91476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 91576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 91676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * "General Purpose Input/Output" (GPIO) control register 91776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 91876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * I'm not sure about this but after looking at the code 91976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * for all chipsets here is what i got. 92076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 92176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * We have 6 GPIOs (pins), each GPIO has 4 modes (2 bits) 92276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Mode 0 -> always input 92376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Mode 1 -> output when GPIODO for this GPIO is set to 0 92476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Mode 2 -> output when GPIODO for this GPIO is set to 1 92576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Mode 3 -> always output 92676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 92776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * For more infos check out get_gpio/set_gpio and 92876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * set_gpio_input/set_gpio_output functs. 92976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * For more infos on gpio interrupt check out set_gpio_intr. 93076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 93176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_NUM_GPIO 6 93276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 93376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_GPIOCR 0x4014 /* Register Address */ 93476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_GPIOCR_INT_ENA 0x00008000 /* Enable GPIO interrupt */ 93576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_GPIOCR_INT_SELL 0x00000000 /* Generate interrupt when pin is low */ 93676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_GPIOCR_INT_SELH 0x00010000 /* Generate interrupt when pin is high */ 93776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_GPIOCR_IN(n) (0 << ((n) * 2)) /* Mode 0 for pin n */ 93876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_GPIOCR_OUT0(n) (1 << ((n) * 2)) /* Mode 1 for pin n */ 93976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_GPIOCR_OUT1(n) (2 << ((n) * 2)) /* Mode 2 for pin n */ 94076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_GPIOCR_OUT(n) (3 << ((n) * 2)) /* Mode 3 for pin n */ 94176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_GPIOCR_INT_SEL(n) ((n) << 12) /* Interrupt for GPIO pin n */ 94276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 94376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 94476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * "General Purpose Input/Output" (GPIO) data output register 94576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 94676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_GPIODO 0x4018 94776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 94876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 94976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * "General Purpose Input/Output" (GPIO) data input register 95076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 95176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_GPIODI 0x401c 95276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_GPIODI_M 0x0000002f 95376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 95476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 95576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Silicon revision register 95676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 95776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SREV 0x4020 /* Register Address */ 95876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SREV_REV 0x0000000f /* Mask for revision */ 95976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SREV_REV_S 0 96076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SREV_VER 0x000000ff /* Mask for version */ 96176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SREV_VER_S 4 96276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 96376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 96476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * TXE write posting register 96576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 96676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TXEPOST 0x4028 96776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 96876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 96976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * QCU sleep mask 97076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 97176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QCU_SLEEP_MASK 0x402c 97276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 97376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 0x4068 is compression buffer configuration 97476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * register on 5414 and pm configuration register 97576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * on 5424 and newer pci-e chips. */ 97676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 97776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 97876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Compression buffer configuration 97976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * register (enable/disable) [5414] 98076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 98176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_5414_CBCFG 0x4068 98276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_5414_CBCFG_BUF_DIS 0x10 /* Disable buffer */ 98376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 98476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 98576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * PCI-E Power managment configuration 98676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * and status register [5424+] 98776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 98876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PCIE_PM_CTL 0x4068 /* Register address */ 98976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Only 5424 */ 99076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PCIE_PM_CTL_L1_WHEN_D2 0x00000001 /* enable PCIe core enter L1 99176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman when d2_sleep_en is asserted */ 99276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PCIE_PM_CTL_L0_L0S_CLEAR 0x00000002 /* Clear L0 and L0S counters */ 99376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PCIE_PM_CTL_L0_L0S_EN 0x00000004 /* Start L0 nd L0S counters */ 99476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PCIE_PM_CTL_LDRESET_EN 0x00000008 /* Enable reset when link goes 99576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman down */ 99676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Wake On Wireless */ 99776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PCIE_PM_CTL_PME_EN 0x00000010 /* PME Enable */ 99876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PCIE_PM_CTL_AUX_PWR_DET 0x00000020 /* Aux power detect */ 99976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PCIE_PM_CTL_PME_CLEAR 0x00000040 /* Clear PME */ 100076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PCIE_PM_CTL_PSM_D0 0x00000080 100176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PCIE_PM_CTL_PSM_D1 0x00000100 100276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PCIE_PM_CTL_PSM_D2 0x00000200 100376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PCIE_PM_CTL_PSM_D3 0x00000400 100476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 100576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 100676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * PCI-E Workaround enable register 100776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 100876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PCIE_WAEN 0x407c 100976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 101076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 101176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * PCI-E Serializer/Desirializer 101276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * registers 101376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 101476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PCIE_SERDES 0x4080 101576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PCIE_SERDES_RESET 0x4084 101676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 101776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/*====EEPROM REGISTERS====*/ 101876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 101976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 102076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * EEPROM access registers 102176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 102276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Here we got a difference between 5210/5211-12 102376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * read data register for 5210 is at 0x6800 and 102476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * status register is at 0x6c00. There is also 102576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * no eeprom command register on 5210 and the 102676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * offsets are different. 102776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 102876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * To read eeprom data for a specific offset: 102976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 5210 - enable eeprom access (AR5K_PCICFG_EEAE) 103076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * read AR5K_EEPROM_BASE +(4 * offset) 103176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * check the eeprom status register 103276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * and read eeprom data register. 103376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 103476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 5211 - write offset to AR5K_EEPROM_BASE 103576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 5212 write AR5K_EEPROM_CMD_READ on AR5K_EEPROM_CMD 103676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * check the eeprom status register 103776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * and read eeprom data register. 103876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 103976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * To write eeprom data for a specific offset: 104076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 5210 - enable eeprom access (AR5K_PCICFG_EEAE) 104176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * write data to AR5K_EEPROM_BASE +(4 * offset) 104276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * check the eeprom status register 104376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 5211 - write AR5K_EEPROM_CMD_RESET on AR5K_EEPROM_CMD 104476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 5212 write offset to AR5K_EEPROM_BASE 104576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * write data to data register 104676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * write AR5K_EEPROM_CMD_WRITE on AR5K_EEPROM_CMD 104776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * check the eeprom status register 104876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 104976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * For more infos check eeprom_* functs and the ar5k.c 105076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * file posted in madwifi-devel mailing list. 105176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * http://sourceforge.net/mailarchive/message.php?msg_id=8966525 105276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 105376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 105476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_EEPROM_BASE 0x6000 105576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 105676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 105776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * EEPROM data register 105876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 105976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_EEPROM_DATA_5211 0x6004 106076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_EEPROM_DATA_5210 0x6800 106176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_EEPROM_DATA (ah->ah_version == AR5K_AR5210 ? \ 106276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman AR5K_EEPROM_DATA_5210 : AR5K_EEPROM_DATA_5211) 106376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 106476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 106576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * EEPROM command register 106676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 106776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_EEPROM_CMD 0x6008 /* Register Addres */ 106876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_EEPROM_CMD_READ 0x00000001 /* EEPROM read */ 106976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_EEPROM_CMD_WRITE 0x00000002 /* EEPROM write */ 107076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_EEPROM_CMD_RESET 0x00000004 /* EEPROM reset */ 107176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 107276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 107376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * EEPROM status register 107476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 107576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_EEPROM_STAT_5210 0x6c00 /* Register Address [5210] */ 107676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_EEPROM_STAT_5211 0x600c /* Register Address [5211+] */ 107776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_EEPROM_STATUS (ah->ah_version == AR5K_AR5210 ? \ 107876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman AR5K_EEPROM_STAT_5210 : AR5K_EEPROM_STAT_5211) 107976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_EEPROM_STAT_RDERR 0x00000001 /* EEPROM read failed */ 108076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_EEPROM_STAT_RDDONE 0x00000002 /* EEPROM read successful */ 108176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_EEPROM_STAT_WRERR 0x00000004 /* EEPROM write failed */ 108276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_EEPROM_STAT_WRDONE 0x00000008 /* EEPROM write successful */ 108376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 108476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 108576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * EEPROM config register 108676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 108776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_EEPROM_CFG 0x6010 /* Register Addres */ 108876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_EEPROM_CFG_SIZE 0x00000003 /* Size determination override */ 108976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_EEPROM_CFG_SIZE_AUTO 0 109076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_EEPROM_CFG_SIZE_4KBIT 1 109176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_EEPROM_CFG_SIZE_8KBIT 2 109276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_EEPROM_CFG_SIZE_16KBIT 3 109376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_EEPROM_CFG_WR_WAIT_DIS 0x00000004 /* Disable write wait */ 109476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_EEPROM_CFG_CLK_RATE 0x00000018 /* Clock rate */ 109576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_EEPROM_CFG_CLK_RATE_S 3 109676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_EEPROM_CFG_CLK_RATE_156KHZ 0 109776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_EEPROM_CFG_CLK_RATE_312KHZ 1 109876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_EEPROM_CFG_CLK_RATE_625KHZ 2 109976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_EEPROM_CFG_PROT_KEY 0x00ffff00 /* Protection key */ 110076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_EEPROM_CFG_PROT_KEY_S 8 110176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_EEPROM_CFG_LIND_EN 0x01000000 /* Enable length indicator (?) */ 110276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 110376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 110476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 110576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * TODO: Wake On Wireless registers 110676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Range 0x7000 - 0x7ce0 110776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 110876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 110976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 111076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Protocol Control Unit (PCU) registers 111176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 111276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 111376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Used for checking initial register writes 111476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * during channel reset (see reset func) 111576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 111676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PCU_MIN 0x8000 111776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PCU_MAX 0x8fff 111876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 111976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 112076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * First station id register (Lower 32 bits of MAC address) 112176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 112276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_STA_ID0 0x8000 112376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_STA_ID0_ARRD_L32 0xffffffff 112476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 112576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 112676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Second station id register (Upper 16 bits of MAC address + PCU settings) 112776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 112876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_STA_ID1 0x8004 /* Register Address */ 112976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_STA_ID1_ADDR_U16 0x0000ffff /* Upper 16 bits of MAC addres */ 113076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_STA_ID1_AP 0x00010000 /* Set AP mode */ 113176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_STA_ID1_ADHOC 0x00020000 /* Set Ad-Hoc mode */ 113276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_STA_ID1_PWR_SV 0x00040000 /* Power save reporting */ 113376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_STA_ID1_NO_KEYSRCH 0x00080000 /* No key search */ 113476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_STA_ID1_NO_PSPOLL 0x00100000 /* No power save polling [5210] */ 113576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_STA_ID1_PCF_5211 0x00100000 /* Enable PCF on [5211+] */ 113676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_STA_ID1_PCF_5210 0x00200000 /* Enable PCF on [5210]*/ 113776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_STA_ID1_PCF (ah->ah_version == AR5K_AR5210 ? \ 113876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman AR5K_STA_ID1_PCF_5210 : AR5K_STA_ID1_PCF_5211) 113976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_STA_ID1_DEFAULT_ANTENNA 0x00200000 /* Use default antenna */ 114076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_STA_ID1_DESC_ANTENNA 0x00400000 /* Update antenna from descriptor */ 114176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_STA_ID1_RTS_DEF_ANTENNA 0x00800000 /* Use default antenna for RTS */ 114276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_STA_ID1_ACKCTS_6MB 0x01000000 /* Use 6Mbit/s for ACK/CTS */ 114376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_STA_ID1_BASE_RATE_11B 0x02000000 /* Use 11b base rate for ACK/CTS [5211+] */ 114476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_STA_ID1_SELFGEN_DEF_ANT 0x04000000 /* Use def. antenna for self generated frames */ 114576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_STA_ID1_CRYPT_MIC_EN 0x08000000 /* Enable MIC */ 114676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_STA_ID1_KEYSRCH_MODE 0x10000000 /* Look up key when key id != 0 */ 114776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_STA_ID1_PRESERVE_SEQ_NUM 0x20000000 /* Preserve sequence number */ 114876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_STA_ID1_CBCIV_ENDIAN 0x40000000 /* ??? */ 114976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_STA_ID1_KEYSRCH_MCAST 0x80000000 /* Do key cache search for mcast frames */ 115076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 115176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 115276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * First BSSID register (MAC address, lower 32bits) 115376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 115476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_BSS_ID0 0x8008 115576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 115676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 115776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Second BSSID register (MAC address in upper 16 bits) 115876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 115976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * AID: Association ID 116076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 116176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_BSS_ID1 0x800c 116276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_BSS_ID1_AID 0xffff0000 116376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_BSS_ID1_AID_S 16 116476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 116576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 116676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Backoff slot time register 116776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 116876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SLOT_TIME 0x8010 116976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 117076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 117176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * ACK/CTS timeout register 117276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 117376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TIME_OUT 0x8014 /* Register Address */ 117476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TIME_OUT_ACK 0x00001fff /* ACK timeout mask */ 117576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TIME_OUT_ACK_S 0 117676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TIME_OUT_CTS 0x1fff0000 /* CTS timeout mask */ 117776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TIME_OUT_CTS_S 16 117876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 117976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 118076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * RSSI threshold register 118176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 118276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RSSI_THR 0x8018 /* Register Address */ 118376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RSSI_THR_M 0x000000ff /* Mask for RSSI threshold [5211+] */ 118476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RSSI_THR_BMISS_5210 0x00000700 /* Mask for Beacon Missed threshold [5210] */ 118576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RSSI_THR_BMISS_5210_S 8 118676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RSSI_THR_BMISS_5211 0x0000ff00 /* Mask for Beacon Missed threshold [5211+] */ 118776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RSSI_THR_BMISS_5211_S 8 118876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RSSI_THR_BMISS (ah->ah_version == AR5K_AR5210 ? \ 118976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman AR5K_RSSI_THR_BMISS_5210 : AR5K_RSSI_THR_BMISS_5211) 119076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RSSI_THR_BMISS_S 8 119176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 119276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 119376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 5210 has more PCU registers because there is no QCU/DCU 119476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * so queue parameters are set here, this way a lot common 119576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * registers have different address for 5210. To make things 119676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * easier we define a macro based on ah->ah_version for common 119776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * registers with different addresses and common flags. 119876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 119976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 120076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 120176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Retry limit register 120276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 120376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Retry limit register for 5210 (no QCU/DCU so it's done in PCU) 120476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 120576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_NODCU_RETRY_LMT 0x801c /* Register Address */ 120676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_NODCU_RETRY_LMT_SH_RETRY 0x0000000f /* Short retry limit mask */ 120776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_NODCU_RETRY_LMT_SH_RETRY_S 0 120876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_NODCU_RETRY_LMT_LG_RETRY 0x000000f0 /* Long retry mask */ 120976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_NODCU_RETRY_LMT_LG_RETRY_S 4 121076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_NODCU_RETRY_LMT_SSH_RETRY 0x00003f00 /* Station short retry limit mask */ 121176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_NODCU_RETRY_LMT_SSH_RETRY_S 8 121276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_NODCU_RETRY_LMT_SLG_RETRY 0x000fc000 /* Station long retry limit mask */ 121376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_NODCU_RETRY_LMT_SLG_RETRY_S 14 121476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_NODCU_RETRY_LMT_CW_MIN 0x3ff00000 /* Minimum contention window mask */ 121576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_NODCU_RETRY_LMT_CW_MIN_S 20 121676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 121776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 121876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Transmit latency register 121976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 122076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_USEC_5210 0x8020 /* Register Address [5210] */ 122176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_USEC_5211 0x801c /* Register Address [5211+] */ 122276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_USEC (ah->ah_version == AR5K_AR5210 ? \ 122376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman AR5K_USEC_5210 : AR5K_USEC_5211) 122476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_USEC_1 0x0000007f /* clock cycles for 1us */ 122576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_USEC_1_S 0 122676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_USEC_32 0x00003f80 /* clock cycles for 1us while on 32Mhz clock */ 122776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_USEC_32_S 7 122876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_USEC_TX_LATENCY_5211 0x007fc000 122976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_USEC_TX_LATENCY_5211_S 14 123076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_USEC_RX_LATENCY_5211 0x1f800000 123176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_USEC_RX_LATENCY_5211_S 23 123276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_USEC_TX_LATENCY_5210 0x000fc000 /* also for 5311 */ 123376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_USEC_TX_LATENCY_5210_S 14 123476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_USEC_RX_LATENCY_5210 0x03f00000 /* also for 5311 */ 123576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_USEC_RX_LATENCY_5210_S 20 123676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 123776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 123876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * PCU beacon control register 123976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 124076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_BEACON_5210 0x8024 /*Register Address [5210] */ 124176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_BEACON_5211 0x8020 /*Register Address [5211+] */ 124276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_BEACON (ah->ah_version == AR5K_AR5210 ? \ 124376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman AR5K_BEACON_5210 : AR5K_BEACON_5211) 124476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_BEACON_PERIOD 0x0000ffff /* Mask for beacon period */ 124576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_BEACON_PERIOD_S 0 124676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_BEACON_TIM 0x007f0000 /* Mask for TIM offset */ 124776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_BEACON_TIM_S 16 124876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_BEACON_ENABLE 0x00800000 /* Enable beacons */ 124976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_BEACON_RESET_TSF 0x01000000 /* Force TSF reset */ 125076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 125176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 125276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * CFP period register 125376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 125476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_CFP_PERIOD_5210 0x8028 125576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_CFP_PERIOD_5211 0x8024 125676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_CFP_PERIOD (ah->ah_version == AR5K_AR5210 ? \ 125776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman AR5K_CFP_PERIOD_5210 : AR5K_CFP_PERIOD_5211) 125876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 125976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 126076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Next beacon time register 126176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 126276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TIMER0_5210 0x802c 126376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TIMER0_5211 0x8028 126476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TIMER0 (ah->ah_version == AR5K_AR5210 ? \ 126576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman AR5K_TIMER0_5210 : AR5K_TIMER0_5211) 126676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 126776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 126876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Next DMA beacon alert register 126976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 127076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TIMER1_5210 0x8030 127176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TIMER1_5211 0x802c 127276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TIMER1 (ah->ah_version == AR5K_AR5210 ? \ 127376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman AR5K_TIMER1_5210 : AR5K_TIMER1_5211) 127476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 127576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 127676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Next software beacon alert register 127776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 127876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TIMER2_5210 0x8034 127976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TIMER2_5211 0x8030 128076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TIMER2 (ah->ah_version == AR5K_AR5210 ? \ 128176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman AR5K_TIMER2_5210 : AR5K_TIMER2_5211) 128276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 128376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 128476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Next ATIM window time register 128576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 128676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TIMER3_5210 0x8038 128776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TIMER3_5211 0x8034 128876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TIMER3 (ah->ah_version == AR5K_AR5210 ? \ 128976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman AR5K_TIMER3_5210 : AR5K_TIMER3_5211) 129076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 129176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 129276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 129376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 5210 First inter frame spacing register (IFS) 129476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 129576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_IFS0 0x8040 129676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_IFS0_SIFS 0x000007ff 129776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_IFS0_SIFS_S 0 129876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_IFS0_DIFS 0x007ff800 129976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_IFS0_DIFS_S 11 130076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 130176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 130276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 5210 Second inter frame spacing register (IFS) 130376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 130476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_IFS1 0x8044 130576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_IFS1_PIFS 0x00000fff 130676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_IFS1_PIFS_S 0 130776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_IFS1_EIFS 0x03fff000 130876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_IFS1_EIFS_S 12 130976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_IFS1_CS_EN 0x04000000 131076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 131176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 131276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 131376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * CFP duration register 131476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 131576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_CFP_DUR_5210 0x8048 131676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_CFP_DUR_5211 0x8038 131776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_CFP_DUR (ah->ah_version == AR5K_AR5210 ? \ 131876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman AR5K_CFP_DUR_5210 : AR5K_CFP_DUR_5211) 131976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 132076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 132176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Receive filter register 132276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 132376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RX_FILTER_5210 0x804c /* Register Address [5210] */ 132476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RX_FILTER_5211 0x803c /* Register Address [5211+] */ 132576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RX_FILTER (ah->ah_version == AR5K_AR5210 ? \ 132676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman AR5K_RX_FILTER_5210 : AR5K_RX_FILTER_5211) 132776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RX_FILTER_UCAST 0x00000001 /* Don't filter unicast frames */ 132876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RX_FILTER_MCAST 0x00000002 /* Don't filter multicast frames */ 132976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RX_FILTER_BCAST 0x00000004 /* Don't filter broadcast frames */ 133076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RX_FILTER_CONTROL 0x00000008 /* Don't filter control frames */ 133176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RX_FILTER_BEACON 0x00000010 /* Don't filter beacon frames */ 133276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RX_FILTER_PROM 0x00000020 /* Set promiscuous mode */ 133376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RX_FILTER_XRPOLL 0x00000040 /* Don't filter XR poll frame [5212+] */ 133476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RX_FILTER_PROBEREQ 0x00000080 /* Don't filter probe requests [5212+] */ 133576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RX_FILTER_PHYERR_5212 0x00000100 /* Don't filter phy errors [5212+] */ 133676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RX_FILTER_RADARERR_5212 0x00000200 /* Don't filter phy radar errors [5212+] */ 133776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RX_FILTER_PHYERR_5211 0x00000040 /* [5211] */ 133876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RX_FILTER_RADARERR_5211 0x00000080 /* [5211] */ 133976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RX_FILTER_PHYERR \ 134076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman ((ah->ah_version == AR5K_AR5211 ? \ 134176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman AR5K_RX_FILTER_PHYERR_5211 : AR5K_RX_FILTER_PHYERR_5212)) 134276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RX_FILTER_RADARERR \ 134376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman ((ah->ah_version == AR5K_AR5211 ? \ 134476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman AR5K_RX_FILTER_RADARERR_5211 : AR5K_RX_FILTER_RADARERR_5212)) 134576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 134676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 134776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Multicast filter register (lower 32 bits) 134876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 134976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_MCAST_FILTER0_5210 0x8050 135076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_MCAST_FILTER0_5211 0x8040 135176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_MCAST_FILTER0 (ah->ah_version == AR5K_AR5210 ? \ 135276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman AR5K_MCAST_FILTER0_5210 : AR5K_MCAST_FILTER0_5211) 135376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 135476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 135576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Multicast filter register (higher 16 bits) 135676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 135776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_MCAST_FILTER1_5210 0x8054 135876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_MCAST_FILTER1_5211 0x8044 135976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_MCAST_FILTER1 (ah->ah_version == AR5K_AR5210 ? \ 136076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman AR5K_MCAST_FILTER1_5210 : AR5K_MCAST_FILTER1_5211) 136176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 136276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 136376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 136476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Transmit mask register (lower 32 bits) [5210] 136576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 136676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TX_MASK0 0x8058 136776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 136876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 136976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Transmit mask register (higher 16 bits) [5210] 137076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 137176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TX_MASK1 0x805c 137276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 137376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 137476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Clear transmit mask [5210] 137576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 137676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_CLR_TMASK 0x8060 137776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 137876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 137976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Trigger level register (before transmission) [5210] 138076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 138176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TRIG_LVL 0x8064 138276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 138376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 138476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 138576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * PCU control register 138676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 138776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Only DIS_RX is used in the code, the rest i guess are 138876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * for tweaking/diagnostics. 138976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 139076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DIAG_SW_5210 0x8068 /* Register Address [5210] */ 139176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DIAG_SW_5211 0x8048 /* Register Address [5211+] */ 139276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DIAG_SW (ah->ah_version == AR5K_AR5210 ? \ 139376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman AR5K_DIAG_SW_5210 : AR5K_DIAG_SW_5211) 139476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DIAG_SW_DIS_WEP_ACK 0x00000001 /* Disable ACKs if WEP key is invalid */ 139576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DIAG_SW_DIS_ACK 0x00000002 /* Disable ACKs */ 139676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DIAG_SW_DIS_CTS 0x00000004 /* Disable CTSs */ 139776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DIAG_SW_DIS_ENC 0x00000008 /* Disable encryption */ 139876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DIAG_SW_DIS_DEC 0x00000010 /* Disable decryption */ 139976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DIAG_SW_DIS_TX 0x00000020 /* Disable transmit [5210] */ 140076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DIAG_SW_DIS_RX_5210 0x00000040 /* Disable recieve */ 140176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DIAG_SW_DIS_RX_5211 0x00000020 140276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DIAG_SW_DIS_RX (ah->ah_version == AR5K_AR5210 ? \ 140376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman AR5K_DIAG_SW_DIS_RX_5210 : AR5K_DIAG_SW_DIS_RX_5211) 140476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DIAG_SW_LOOP_BACK_5210 0x00000080 /* Loopback (i guess it goes with DIS_TX) [5210] */ 140576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DIAG_SW_LOOP_BACK_5211 0x00000040 140676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DIAG_SW_LOOP_BACK (ah->ah_version == AR5K_AR5210 ? \ 140776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman AR5K_DIAG_SW_LOOP_BACK_5210 : AR5K_DIAG_SW_LOOP_BACK_5211) 140876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DIAG_SW_CORR_FCS_5210 0x00000100 /* Corrupted FCS */ 140976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DIAG_SW_CORR_FCS_5211 0x00000080 141076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DIAG_SW_CORR_FCS (ah->ah_version == AR5K_AR5210 ? \ 141176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman AR5K_DIAG_SW_CORR_FCS_5210 : AR5K_DIAG_SW_CORR_FCS_5211) 141276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DIAG_SW_CHAN_INFO_5210 0x00000200 /* Dump channel info */ 141376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DIAG_SW_CHAN_INFO_5211 0x00000100 141476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DIAG_SW_CHAN_INFO (ah->ah_version == AR5K_AR5210 ? \ 141576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman AR5K_DIAG_SW_CHAN_INFO_5210 : AR5K_DIAG_SW_CHAN_INFO_5211) 141676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DIAG_SW_EN_SCRAM_SEED_5210 0x00000400 /* Enable fixed scrambler seed */ 141776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DIAG_SW_EN_SCRAM_SEED_5211 0x00000200 141876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DIAG_SW_EN_SCRAM_SEED (ah->ah_version == AR5K_AR5210 ? \ 141976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman AR5K_DIAG_SW_EN_SCRAM_SEED_5210 : AR5K_DIAG_SW_EN_SCRAM_SEED_5211) 142076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DIAG_SW_ECO_ENABLE 0x00000400 /* [5211+] */ 142176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DIAG_SW_SCVRAM_SEED 0x0003f800 /* [5210] */ 142276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DIAG_SW_SCRAM_SEED_M 0x0001fc00 /* Scrambler seed mask */ 142376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DIAG_SW_SCRAM_SEED_S 10 142476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DIAG_SW_DIS_SEQ_INC 0x00040000 /* Disable seqnum increment (?)[5210] */ 142576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DIAG_SW_FRAME_NV0_5210 0x00080000 142676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DIAG_SW_FRAME_NV0_5211 0x00020000 /* Accept frames of non-zero protocol number */ 142776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DIAG_SW_FRAME_NV0 (ah->ah_version == AR5K_AR5210 ? \ 142876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman AR5K_DIAG_SW_FRAME_NV0_5210 : AR5K_DIAG_SW_FRAME_NV0_5211) 142976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DIAG_SW_OBSPT_M 0x000c0000 /* Observation point select (?) */ 143076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DIAG_SW_OBSPT_S 18 143176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DIAG_SW_RX_CLEAR_HIGH 0x0010000 /* Force RX Clear high */ 143276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DIAG_SW_IGNORE_CARR_SENSE 0x0020000 /* Ignore virtual carrier sense */ 143376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DIAG_SW_CHANEL_IDLE_HIGH 0x0040000 /* Force channel idle high */ 143476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DIAG_SW_PHEAR_ME 0x0080000 /* ??? */ 143576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 143676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 143776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * TSF (clock) register (lower 32 bits) 143876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 143976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TSF_L32_5210 0x806c 144076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TSF_L32_5211 0x804c 144176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TSF_L32 (ah->ah_version == AR5K_AR5210 ? \ 144276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman AR5K_TSF_L32_5210 : AR5K_TSF_L32_5211) 144376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 144476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 144576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * TSF (clock) register (higher 32 bits) 144676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 144776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TSF_U32_5210 0x8070 144876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TSF_U32_5211 0x8050 144976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TSF_U32 (ah->ah_version == AR5K_AR5210 ? \ 145076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman AR5K_TSF_U32_5210 : AR5K_TSF_U32_5211) 145176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 145276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 145376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Last beacon timestamp register (Read Only) 145476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 145576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_LAST_TSTP 0x8080 145676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 145776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 145876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * ADDAC test register [5211+] 145976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 146076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_ADDAC_TEST 0x8054 /* Register Address */ 146176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_ADDAC_TEST_TXCONT 0x00000001 /* Test continuous tx */ 146276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_ADDAC_TEST_TST_MODE 0x00000002 /* Test mode */ 146376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_ADDAC_TEST_LOOP_EN 0x00000004 /* Enable loop */ 146476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_ADDAC_TEST_LOOP_LEN 0x00000008 /* Loop length (field) */ 146576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_ADDAC_TEST_USE_U8 0x00004000 /* Use upper 8 bits */ 146676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_ADDAC_TEST_MSB 0x00008000 /* State of MSB */ 146776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_ADDAC_TEST_TRIG_SEL 0x00010000 /* Trigger select */ 146876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_ADDAC_TEST_TRIG_PTY 0x00020000 /* Trigger polarity */ 146976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_ADDAC_TEST_RXCONT 0x00040000 /* Continuous capture */ 147076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_ADDAC_TEST_CAPTURE 0x00080000 /* Begin capture */ 147176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_ADDAC_TEST_TST_ARM 0x00100000 /* ARM rx buffer for capture */ 147276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 147376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 147476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Default antenna register [5211+] 147576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 147676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DEFAULT_ANTENNA 0x8058 147776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 147876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 147976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Frame control QoS mask register (?) [5211+] 148076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * (FC_QOS_MASK) 148176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 148276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_FRAME_CTL_QOSM 0x805c 148376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 148476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 148576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Seq mask register (?) [5211+] 148676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 148776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SEQ_MASK 0x8060 148876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 148976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 149076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Retry count register [5210] 149176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 149276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RETRY_CNT 0x8084 /* Register Address [5210] */ 149376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RETRY_CNT_SSH 0x0000003f /* Station short retry count (?) */ 149476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RETRY_CNT_SLG 0x00000fc0 /* Station long retry count (?) */ 149576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 149676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 149776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Back-off status register [5210] 149876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 149976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_BACKOFF 0x8088 /* Register Address [5210] */ 150076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_BACKOFF_CW 0x000003ff /* Backoff Contention Window (?) */ 150176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_BACKOFF_CNT 0x03ff0000 /* Backoff count (?) */ 150276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 150376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 150476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 150576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 150676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * NAV register (current) 150776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 150876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_NAV_5210 0x808c 150976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_NAV_5211 0x8084 151076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_NAV (ah->ah_version == AR5K_AR5210 ? \ 151176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman AR5K_NAV_5210 : AR5K_NAV_5211) 151276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 151376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 151476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * RTS success register 151576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 151676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RTS_OK_5210 0x8090 151776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RTS_OK_5211 0x8088 151876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RTS_OK (ah->ah_version == AR5K_AR5210 ? \ 151976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman AR5K_RTS_OK_5210 : AR5K_RTS_OK_5211) 152076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 152176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 152276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * RTS failure register 152376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 152476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RTS_FAIL_5210 0x8094 152576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RTS_FAIL_5211 0x808c 152676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RTS_FAIL (ah->ah_version == AR5K_AR5210 ? \ 152776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman AR5K_RTS_FAIL_5210 : AR5K_RTS_FAIL_5211) 152876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 152976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 153076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * ACK failure register 153176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 153276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_ACK_FAIL_5210 0x8098 153376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_ACK_FAIL_5211 0x8090 153476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_ACK_FAIL (ah->ah_version == AR5K_AR5210 ? \ 153576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman AR5K_ACK_FAIL_5210 : AR5K_ACK_FAIL_5211) 153676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 153776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 153876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * FCS failure register 153976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 154076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_FCS_FAIL_5210 0x809c 154176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_FCS_FAIL_5211 0x8094 154276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_FCS_FAIL (ah->ah_version == AR5K_AR5210 ? \ 154376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman AR5K_FCS_FAIL_5210 : AR5K_FCS_FAIL_5211) 154476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 154576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 154676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Beacon count register 154776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 154876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_BEACON_CNT_5210 0x80a0 154976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_BEACON_CNT_5211 0x8098 155076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_BEACON_CNT (ah->ah_version == AR5K_AR5210 ? \ 155176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman AR5K_BEACON_CNT_5210 : AR5K_BEACON_CNT_5211) 155276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 155376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 155476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/*===5212 Specific PCU registers===*/ 155576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 155676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 155776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Transmit power control register 155876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 155976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TPC 0x80e8 156076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TPC_ACK 0x0000003f /* ack frames */ 156176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TPC_ACK_S 0 156276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TPC_CTS 0x00003f00 /* cts frames */ 156376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TPC_CTS_S 8 156476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TPC_CHIRP 0x003f0000 /* chirp frames */ 156576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TPC_CHIRP_S 16 156676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TPC_DOPPLER 0x0f000000 /* doppler chirp span */ 156776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TPC_DOPPLER_S 24 156876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 156976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 157076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * XR (eXtended Range) mode register 157176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 157276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_XRMODE 0x80c0 /* Register Address */ 157376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_XRMODE_POLL_TYPE_M 0x0000003f /* Mask for Poll type (?) */ 157476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_XRMODE_POLL_TYPE_S 0 157576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_XRMODE_POLL_SUBTYPE_M 0x0000003c /* Mask for Poll subtype (?) */ 157676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_XRMODE_POLL_SUBTYPE_S 2 157776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_XRMODE_POLL_WAIT_ALL 0x00000080 /* Wait for poll */ 157876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_XRMODE_SIFS_DELAY 0x000fff00 /* Mask for SIFS delay */ 157976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_XRMODE_FRAME_HOLD_M 0xfff00000 /* Mask for frame hold (?) */ 158076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_XRMODE_FRAME_HOLD_S 20 158176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 158276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 158376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * XR delay register 158476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 158576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_XRDELAY 0x80c4 /* Register Address */ 158676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_XRDELAY_SLOT_DELAY_M 0x0000ffff /* Mask for slot delay */ 158776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_XRDELAY_SLOT_DELAY_S 0 158876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_XRDELAY_CHIRP_DELAY_M 0xffff0000 /* Mask for CHIRP data delay */ 158976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_XRDELAY_CHIRP_DELAY_S 16 159076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 159176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 159276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * XR timeout register 159376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 159476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_XRTIMEOUT 0x80c8 /* Register Address */ 159576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_XRTIMEOUT_CHIRP_M 0x0000ffff /* Mask for CHIRP timeout */ 159676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_XRTIMEOUT_CHIRP_S 0 159776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_XRTIMEOUT_POLL_M 0xffff0000 /* Mask for Poll timeout */ 159876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_XRTIMEOUT_POLL_S 16 159976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 160076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 160176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * XR chirp register 160276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 160376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_XRCHIRP 0x80cc /* Register Address */ 160476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_XRCHIRP_SEND 0x00000001 /* Send CHIRP */ 160576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_XRCHIRP_GAP 0xffff0000 /* Mask for CHIRP gap (?) */ 160676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 160776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 160876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * XR stomp register 160976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 161076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_XRSTOMP 0x80d0 /* Register Address */ 161176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_XRSTOMP_TX 0x00000001 /* Stomp Tx (?) */ 161276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_XRSTOMP_RX 0x00000002 /* Stomp Rx (?) */ 161376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_XRSTOMP_TX_RSSI 0x00000004 /* Stomp Tx RSSI (?) */ 161476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_XRSTOMP_TX_BSSID 0x00000008 /* Stomp Tx BSSID (?) */ 161576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_XRSTOMP_DATA 0x00000010 /* Stomp data (?)*/ 161676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_XRSTOMP_RSSI_THRES 0x0000ff00 /* Mask for XR RSSI threshold */ 161776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 161876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 161976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * First enhanced sleep register 162076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 162176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SLEEP0 0x80d4 /* Register Address */ 162276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SLEEP0_NEXT_DTIM 0x0007ffff /* Mask for next DTIM (?) */ 162376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SLEEP0_NEXT_DTIM_S 0 162476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SLEEP0_ASSUME_DTIM 0x00080000 /* Assume DTIM */ 162576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SLEEP0_ENH_SLEEP_EN 0x00100000 /* Enable enchanced sleep control */ 162676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SLEEP0_CABTO 0xff000000 /* Mask for CAB Time Out */ 162776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SLEEP0_CABTO_S 24 162876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 162976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 163076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Second enhanced sleep register 163176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 163276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SLEEP1 0x80d8 /* Register Address */ 163376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SLEEP1_NEXT_TIM 0x0007ffff /* Mask for next TIM (?) */ 163476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SLEEP1_NEXT_TIM_S 0 163576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SLEEP1_BEACON_TO 0xff000000 /* Mask for Beacon Time Out */ 163676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SLEEP1_BEACON_TO_S 24 163776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 163876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 163976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Third enhanced sleep register 164076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 164176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SLEEP2 0x80dc /* Register Address */ 164276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SLEEP2_TIM_PER 0x0000ffff /* Mask for TIM period (?) */ 164376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SLEEP2_TIM_PER_S 0 164476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SLEEP2_DTIM_PER 0xffff0000 /* Mask for DTIM period (?) */ 164576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_SLEEP2_DTIM_PER_S 16 164676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 164776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 164876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * BSSID mask registers 164976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 165076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_BSS_IDM0 0x80e0 /* Upper bits */ 165176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_BSS_IDM1 0x80e4 /* Lower bits */ 165276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 165376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 165476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * TX power control (TPC) register 165576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 165676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * XXX: PCDAC steps (0.5dbm) or DBM ? 165776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 165876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 165976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TXPC 0x80e8 /* Register Address */ 166076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TXPC_ACK_M 0x0000003f /* ACK tx power */ 166176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TXPC_ACK_S 0 166276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TXPC_CTS_M 0x00003f00 /* CTS tx power */ 166376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TXPC_CTS_S 8 166476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TXPC_CHIRP_M 0x003f0000 /* CHIRP tx power */ 166576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TXPC_CHIRP_S 16 166676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TXPC_DOPPLER 0x0f000000 /* Doppler chirp span (?) */ 166776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TXPC_DOPPLER_S 24 166876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 166976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 167076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Profile count registers 167176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 167276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PROFCNT_TX 0x80ec /* Tx count */ 167376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PROFCNT_RX 0x80f0 /* Rx count */ 167476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PROFCNT_RXCLR 0x80f4 /* Clear Rx count */ 167576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PROFCNT_CYCLE 0x80f8 /* Cycle count (?) */ 167676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 167776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 167876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Quiet period control registers 167976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 168076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QUIET_CTL1 0x80fc /* Register Address */ 168176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QUIET_CTL1_NEXT_QT_TSF 0x0000ffff /* Next quiet period TSF (TU) */ 168276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QUIET_CTL1_NEXT_QT_TSF_S 0 168376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QUIET_CTL1_QT_EN 0x00010000 /* Enable quiet period */ 168476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QUIET_CTL1_ACK_CTS_EN 0x00020000 /* Send ACK/CTS during quiet period */ 168576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 168676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QUIET_CTL2 0x8100 /* Register Address */ 168776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QUIET_CTL2_QT_PER 0x0000ffff /* Mask for quiet period periodicity */ 168876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QUIET_CTL2_QT_PER_S 0 168976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QUIET_CTL2_QT_DUR 0xffff0000 /* Mask for quiet period duration */ 169076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QUIET_CTL2_QT_DUR_S 16 169176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 169276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 169376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * TSF parameter register 169476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 169576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TSF_PARM 0x8104 /* Register Address */ 169676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TSF_PARM_INC 0x000000ff /* Mask for TSF increment */ 169776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TSF_PARM_INC_S 0 169876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 169976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 170076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * QoS NOACK policy 170176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 170276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QOS_NOACK 0x8108 /* Register Address */ 170376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QOS_NOACK_2BIT_VALUES 0x0000000f /* ??? */ 170476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QOS_NOACK_2BIT_VALUES_S 0 170576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QOS_NOACK_BIT_OFFSET 0x00000070 /* ??? */ 170676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QOS_NOACK_BIT_OFFSET_S 4 170776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QOS_NOACK_BYTE_OFFSET 0x00000180 /* ??? */ 170876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_QOS_NOACK_BYTE_OFFSET_S 7 170976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 171076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 171176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * PHY error filter register 171276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 171376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_ERR_FIL 0x810c 171476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_ERR_FIL_RADAR 0x00000020 /* Radar signal */ 171576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_ERR_FIL_OFDM 0x00020000 /* OFDM false detect (ANI) */ 171676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_ERR_FIL_CCK 0x02000000 /* CCK false detect (ANI) */ 171776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 171876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 171976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * XR latency register 172076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 172176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_XRLAT_TX 0x8110 172276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 172376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 172476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * ACK SIFS register 172576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 172676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_ACKSIFS 0x8114 /* Register Address */ 172776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_ACKSIFS_INC 0x00000000 /* ACK SIFS Increment (field) */ 172876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 172976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 173076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * MIC QoS control register (?) 173176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 173276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_MIC_QOS_CTL 0x8118 /* Register Address */ 173376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_MIC_QOS_CTL_OFF(_n) (1 << (_n * 2)) 173476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_MIC_QOS_CTL_MQ_EN 0x00010000 /* Enable MIC QoS */ 173576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 173676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 173776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * MIC QoS select register (?) 173876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 173976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_MIC_QOS_SEL 0x811c 174076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_MIC_QOS_SEL_OFF(_n) (1 << (_n * 4)) 174176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 174276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 174376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Misc mode control register (?) 174476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 174576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_MISC_MODE 0x8120 /* Register Address */ 174676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_MISC_MODE_FBSSID_MATCH 0x00000001 /* Force BSSID match */ 174776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_MISC_MODE_ACKSIFS_MEM 0x00000002 /* ACK SIFS memory (?) */ 174876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_MISC_MODE_COMBINED_MIC 0x00000004 /* use rx/tx MIC key */ 174976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* more bits */ 175076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 175176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 175276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * OFDM Filter counter 175376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 175476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_OFDM_FIL_CNT 0x8124 175576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 175676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 175776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * CCK Filter counter 175876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 175976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_CCK_FIL_CNT 0x8128 176076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 176176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 176276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * PHY Error Counters (?) 176376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 176476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHYERR_CNT1 0x812c 176576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHYERR_CNT1_MASK 0x8130 176676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 176776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHYERR_CNT2 0x8134 176876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHYERR_CNT2_MASK 0x8138 176976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 177076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 177176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * TSF Threshold register (?) 177276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 177376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_TSF_THRES 0x813c 177476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 177576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 177676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * TODO: Wake On Wireless registers 177776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Range: 0x8147 - 0x818c 177876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 177976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 178076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 178176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Rate -> ACK SIFS mapping table (32 entries) 178276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 178376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RATE_ACKSIFS_BASE 0x8680 /* Register Address */ 178476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RATE_ACKSIFS(_n) (AR5K_RATE_ACKSIFS_BSE + ((_n) << 2)) 178576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RATE_ACKSIFS_NORMAL 0x00000001 /* Normal SIFS (field) */ 178676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RATE_ACKSIFS_TURBO 0x00000400 /* Turbo SIFS (field) */ 178776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 178876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 178976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Rate -> duration mapping table (32 entries) 179076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 179176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RATE_DUR_BASE 0x8700 179276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RATE_DUR(_n) (AR5K_RATE_DUR_BASE + ((_n) << 2)) 179376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 179476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 179576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Rate -> db mapping table 179676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * (8 entries, each one has 4 8bit fields) 179776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 179876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RATE2DB_BASE 0x87c0 179976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RATE2DB(_n) (AR5K_RATE2DB_BASE + ((_n) << 2)) 180076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 180176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 180276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * db -> Rate mapping table 180376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * (8 entries, each one has 4 8bit fields) 180476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 180576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DB2RATE_BASE 0x87e0 180676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_DB2RATE(_n) (AR5K_DB2RATE_BASE + ((_n) << 2)) 180776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 180876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/*===5212 end===*/ 180976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 181076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 181176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Key table (WEP) register 181276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 181376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_KEYTABLE_0_5210 0x9000 181476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_KEYTABLE_0_5211 0x8800 181576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_KEYTABLE_5210(_n) (AR5K_KEYTABLE_0_5210 + ((_n) << 5)) 181676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_KEYTABLE_5211(_n) (AR5K_KEYTABLE_0_5211 + ((_n) << 5)) 181776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_KEYTABLE(_n) (ah->ah_version == AR5K_AR5210 ? \ 181876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman AR5K_KEYTABLE_5210(_n) : AR5K_KEYTABLE_5211(_n)) 181976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_KEYTABLE_OFF(_n, x) (AR5K_KEYTABLE(_n) + (x << 2)) 182076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_KEYTABLE_TYPE(_n) AR5K_KEYTABLE_OFF(_n, 5) 182176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_KEYTABLE_TYPE_40 0x00000000 182276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_KEYTABLE_TYPE_104 0x00000001 182376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_KEYTABLE_TYPE_128 0x00000003 182476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_KEYTABLE_TYPE_TKIP 0x00000004 /* [5212+] */ 182576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_KEYTABLE_TYPE_AES 0x00000005 /* [5211+] */ 182676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_KEYTABLE_TYPE_CCM 0x00000006 /* [5212+] */ 182776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_KEYTABLE_TYPE_NULL 0x00000007 /* [5211+] */ 182876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_KEYTABLE_ANTENNA 0x00000008 /* [5212+] */ 182976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_KEYTABLE_MAC0(_n) AR5K_KEYTABLE_OFF(_n, 6) 183076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_KEYTABLE_MAC1(_n) AR5K_KEYTABLE_OFF(_n, 7) 183176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_KEYTABLE_VALID 0x00008000 183276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 183376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* If key type is TKIP and MIC is enabled 183476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * MIC key goes in offset entry + 64 */ 183576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_KEYTABLE_MIC_OFFSET 64 183676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 183776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* WEP 40-bit = 40-bit entered key + 24 bit IV = 64-bit 183876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * WEP 104-bit = 104-bit entered key + 24-bit IV = 128-bit 183976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * WEP 128-bit = 128-bit entered key + 24 bit IV = 152-bit 184076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 184176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Some vendors have introduced bigger WEP keys to address 184276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * security vulnerabilities in WEP. This includes: 184376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 184476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * WEP 232-bit = 232-bit entered key + 24 bit IV = 256-bit 184576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 184676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * We can expand this if we find ar5k Atheros cards with a larger 184776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * key table size. 184876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 184976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_KEYTABLE_SIZE_5210 64 185076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_KEYTABLE_SIZE_5211 128 185176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_KEYTABLE_SIZE (ah->ah_version == AR5K_AR5210 ? \ 185276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman AR5K_KEYTABLE_SIZE_5210 : AR5K_KEYTABLE_SIZE_5211) 185376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 185476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 185576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/*===PHY REGISTERS===*/ 185676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 185776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 185876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * PHY registers start 185976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 186076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_BASE 0x9800 186176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY(_n) (AR5K_PHY_BASE + ((_n) << 2)) 186276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 186376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 186476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * TST_2 (Misc config parameters) 186576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 186676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TST2 0x9800 /* Register Address */ 186776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TST2_TRIG_SEL 0x00000007 /* Trigger select (?)*/ 186876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TST2_TRIG 0x00000010 /* Trigger (?) */ 186976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TST2_CBUS_MODE 0x00000060 /* Cardbus mode (?) */ 187076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TST2_CLK32 0x00000400 /* CLK_OUT is CLK32 (32Khz external) */ 187176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TST2_CHANCOR_DUMP_EN 0x00000800 /* Enable Chancor dump (?) */ 187276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TST2_EVEN_CHANCOR_DUMP 0x00001000 /* Even Chancor dump (?) */ 187376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TST2_RFSILENT_EN 0x00002000 /* Enable RFSILENT */ 187476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TST2_ALT_RFDATA 0x00004000 /* Alternate RFDATA (5-2GHz switch ?) */ 187576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TST2_MINI_OBS_EN 0x00008000 /* Enable mini OBS (?) */ 187676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TST2_RX2_IS_RX5_INV 0x00010000 /* 2GHz rx path is the 5GHz path inverted (?) */ 187776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TST2_SLOW_CLK160 0x00020000 /* Slow CLK160 (?) */ 187876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TST2_AGC_OBS_SEL_3 0x00040000 /* AGC OBS Select 3 (?) */ 187976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TST2_BBB_OBS_SEL 0x00080000 /* BB OBS Select (field ?) */ 188076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TST2_ADC_OBS_SEL 0x00800000 /* ADC OBS Select (field ?) */ 188176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TST2_RX_CLR_SEL 0x08000000 /* RX Clear Select (?) */ 188276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TST2_FORCE_AGC_CLR 0x10000000 /* Force AGC clear (?) */ 188376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_SHIFT_2GHZ 0x00004007 /* Used to access 2GHz radios */ 188476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_SHIFT_5GHZ 0x00000007 /* Used to access 5GHz radios (default) */ 188576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 188676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 188776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * PHY frame control register [5110] /turbo mode register [5111+] 188876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 188976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * There is another frame control register for [5111+] 189076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * at address 0x9944 (see below) but the 2 first flags 189176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * are common here between 5110 frame control register 189276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * and [5111+] turbo mode register, so this also works as 189376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * a "turbo mode register" for 5110. We treat this one as 189476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * a frame control register for 5110 below. 189576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 189676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TURBO 0x9804 /* Register Address */ 189776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TURBO_MODE 0x00000001 /* Enable turbo mode */ 189876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TURBO_SHORT 0x00000002 /* Set short symbols to turbo mode */ 189976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TURBO_MIMO 0x00000004 /* Set turbo for mimo mimo */ 190076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 190176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 190276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * PHY agility command register 190376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * (aka TST_1) 190476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 190576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_AGC 0x9808 /* Register Address */ 190676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TST1 0x9808 190776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_AGC_DISABLE 0x08000000 /* Disable AGC to A2 (?)*/ 190876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TST1_TXHOLD 0x00003800 /* Set tx hold (?) */ 190976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TST1_TXSRC_SRC 0x00000002 /* Used with bit 7 (?) */ 191076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TST1_TXSRC_SRC_S 1 191176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TST1_TXSRC_ALT 0x00000080 /* Set input to tsdac (?) */ 191276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TST1_TXSRC_ALT_S 7 191376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 191476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 191576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 191676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * PHY timing register 3 [5112+] 191776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 191876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TIMING_3 0x9814 191976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TIMING_3_DSC_MAN 0xfffe0000 192076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TIMING_3_DSC_MAN_S 17 192176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TIMING_3_DSC_EXP 0x0001e000 192276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TIMING_3_DSC_EXP_S 13 192376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 192476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 192576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * PHY chip revision register 192676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 192776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_CHIP_ID 0x9818 192876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 192976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 193076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * PHY activation register 193176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 193276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_ACT 0x981c /* Register Address */ 193376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_ACT_ENABLE 0x00000001 /* Activate PHY */ 193476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_ACT_DISABLE 0x00000002 /* Deactivate PHY */ 193576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 193676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 193776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * PHY RF control registers 193876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 193976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_RF_CTL2 0x9824 /* Register Address */ 194076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_RF_CTL2_TXF2TXD_START 0x0000000f /* TX frame to TX data start */ 194176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_RF_CTL2_TXF2TXD_START_S 0 194276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 194376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_RF_CTL3 0x9828 /* Register Address */ 194476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_RF_CTL3_TXE2XLNA_ON 0x0000ff00 /* TX end to XLNA on */ 194576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_RF_CTL3_TXE2XLNA_ON_S 8 194676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 194776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_ADC_CTL 0x982c 194876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_ADC_CTL_INBUFGAIN_OFF 0x00000003 194976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_ADC_CTL_INBUFGAIN_OFF_S 0 195076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_ADC_CTL_PWD_DAC_OFF 0x00002000 195176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_ADC_CTL_PWD_BAND_GAP_OFF 0x00004000 195276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_ADC_CTL_PWD_ADC_OFF 0x00008000 195376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_ADC_CTL_INBUFGAIN_ON 0x00030000 195476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_ADC_CTL_INBUFGAIN_ON_S 16 195576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 195676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_RF_CTL4 0x9834 /* Register Address */ 195776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_RF_CTL4_TXF2XPA_A_ON 0x00000001 /* TX frame to XPA A on (field) */ 195876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_RF_CTL4_TXF2XPA_B_ON 0x00000100 /* TX frame to XPA B on (field) */ 195976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_RF_CTL4_TXE2XPA_A_OFF 0x00010000 /* TX end to XPA A off (field) */ 196076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_RF_CTL4_TXE2XPA_B_OFF 0x01000000 /* TX end to XPA B off (field) */ 196176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 196276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 196376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Pre-Amplifier control register 196476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * (XPA -> external pre-amplifier) 196576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 196676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_PA_CTL 0x9838 /* Register Address */ 196776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_PA_CTL_XPA_A_HI 0x00000001 /* XPA A high (?) */ 196876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_PA_CTL_XPA_B_HI 0x00000002 /* XPA B high (?) */ 196976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_PA_CTL_XPA_A_EN 0x00000004 /* Enable XPA A */ 197076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_PA_CTL_XPA_B_EN 0x00000008 /* Enable XPA B */ 197176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 197276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 197376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * PHY settling register 197476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 197576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_SETTLING 0x9844 /* Register Address */ 197676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_SETTLING_AGC 0x0000007f /* AGC settling time */ 197776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_SETTLING_AGC_S 0 197876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_SETTLING_SWITCH 0x00003f80 /* Switch settlig time */ 197976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_SETTLING_SWITCH_S 7 198076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 198176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 198276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * PHY Gain registers 198376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 198476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_GAIN 0x9848 /* Register Address */ 198576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_GAIN_TXRX_ATTEN 0x0003f000 /* TX-RX Attenuation */ 198676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_GAIN_TXRX_ATTEN_S 12 198776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_GAIN_TXRX_RF_MAX 0x007c0000 198876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_GAIN_TXRX_RF_MAX_S 18 198976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 199076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_GAIN_OFFSET 0x984c /* Register Address */ 199176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_GAIN_OFFSET_RXTX_FLAG 0x00020000 /* RX-TX flag (?) */ 199276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 199376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 199476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Desired ADC/PGA size register 199576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * (for more infos read ANI patent) 199676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 199776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_DESIRED_SIZE 0x9850 /* Register Address */ 199876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_DESIRED_SIZE_ADC 0x000000ff /* ADC desired size */ 199976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_DESIRED_SIZE_ADC_S 0 200076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_DESIRED_SIZE_PGA 0x0000ff00 /* PGA desired size */ 200176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_DESIRED_SIZE_PGA_S 8 200276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_DESIRED_SIZE_TOT 0x0ff00000 /* Total desired size */ 200376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_DESIRED_SIZE_TOT_S 20 200476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 200576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 200676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * PHY signal register 200776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * (for more infos read ANI patent) 200876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 200976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_SIG 0x9858 /* Register Address */ 201076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_SIG_FIRSTEP 0x0003f000 /* FIRSTEP */ 201176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_SIG_FIRSTEP_S 12 201276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_SIG_FIRPWR 0x03fc0000 /* FIPWR */ 201376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_SIG_FIRPWR_S 18 201476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 201576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 201676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * PHY coarse agility control register 201776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * (for more infos read ANI patent) 201876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 201976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_AGCCOARSE 0x985c /* Register Address */ 202076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_AGCCOARSE_LO 0x00007f80 /* AGC Coarse low */ 202176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_AGCCOARSE_LO_S 7 202276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_AGCCOARSE_HI 0x003f8000 /* AGC Coarse high */ 202376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_AGCCOARSE_HI_S 15 202476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 202576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 202676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * PHY agility control register 202776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 202876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_AGCCTL 0x9860 /* Register address */ 202976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_AGCCTL_CAL 0x00000001 /* Enable PHY calibration */ 203076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_AGCCTL_NF 0x00000002 /* Enable Noise Floor calibration */ 203176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_AGCCTL_NF_EN 0x00008000 /* Enable nf calibration to happen (?) */ 203276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_AGCCTL_NF_NOUPDATE 0x00020000 /* Don't update nf automaticaly */ 203376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 203476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 203576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * PHY noise floor status register 203676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 203776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_NF 0x9864 /* Register address */ 203876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_NF_M 0x000001ff /* Noise floor mask */ 203976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_NF_ACTIVE 0x00000100 /* Noise floor calibration still active */ 204076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_NF_RVAL(_n) (((_n) >> 19) & AR5K_PHY_NF_M) 204176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_NF_AVAL(_n) (-((_n) ^ AR5K_PHY_NF_M) + 1) 204276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_NF_SVAL(_n) (((_n) & AR5K_PHY_NF_M) | (1 << 9)) 204376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_NF_THRESH62 0x0007f000 /* Thresh62 -check ANI patent- (field) */ 204476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_NF_THRESH62_S 12 204576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_NF_MINCCA_PWR 0x0ff80000 /* ??? */ 204676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_NF_MINCCA_PWR_S 19 204776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 204876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 204976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * PHY ADC saturation register [5110] 205076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 205176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_ADCSAT 0x9868 205276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_ADCSAT_ICNT 0x0001f800 205376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_ADCSAT_ICNT_S 11 205476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_ADCSAT_THR 0x000007e0 205576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_ADCSAT_THR_S 5 205676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 205776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 205876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * PHY Weak ofdm signal detection threshold registers (ANI) [5212+] 205976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 206076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 206176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* High thresholds */ 206276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_WEAK_OFDM_HIGH_THR 0x9868 206376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_COUNT 0x0000001f 206476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_COUNT_S 0 206576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_WEAK_OFDM_HIGH_THR_M1 0x00fe0000 206676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_WEAK_OFDM_HIGH_THR_M1_S 17 206776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2 0x7f000000 206876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_S 24 206976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 207076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Low thresholds */ 207176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_WEAK_OFDM_LOW_THR 0x986c 207276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_WEAK_OFDM_LOW_THR_SELFCOR_EN 0x00000001 207376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_WEAK_OFDM_LOW_THR_M2_COUNT 0x00003f00 207476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_WEAK_OFDM_LOW_THR_M2_COUNT_S 8 207576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_WEAK_OFDM_LOW_THR_M1 0x001fc000 207676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_WEAK_OFDM_LOW_THR_M1_S 14 207776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_WEAK_OFDM_LOW_THR_M2 0x0fe00000 207876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_WEAK_OFDM_LOW_THR_M2_S 21 207976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 208076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 208176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 208276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * PHY sleep registers [5112+] 208376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 208476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_SCR 0x9870 208576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 208676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_SLMT 0x9874 208776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_SLMT_32MHZ 0x0000007f 208876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 208976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_SCAL 0x9878 209076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_SCAL_32MHZ 0x0000000e 209176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_SCAL_32MHZ_2417 0x0000000a 209276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_SCAL_32MHZ_HB63 0x00000032 209376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 209476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 209576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * PHY PLL (Phase Locked Loop) control register 209676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 209776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_PLL 0x987c 209876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_PLL_20MHZ 0x00000013 /* For half rate (?) */ 209976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 40MHz -> 5GHz band */ 210076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_PLL_40MHZ_5211 0x00000018 210176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_PLL_40MHZ_5212 0x000000aa 210276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_PLL_40MHZ_5413 0x00000004 210376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_PLL_40MHZ (ah->ah_version == AR5K_AR5211 ? \ 210476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman AR5K_PHY_PLL_40MHZ_5211 : AR5K_PHY_PLL_40MHZ_5212) 210576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 44MHz -> 2.4GHz band */ 210676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_PLL_44MHZ_5211 0x00000019 210776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_PLL_44MHZ_5212 0x000000ab 210876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_PLL_44MHZ (ah->ah_version == AR5K_AR5211 ? \ 210976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman AR5K_PHY_PLL_44MHZ_5211 : AR5K_PHY_PLL_44MHZ_5212) 211076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 211176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_PLL_RF5111 0x00000000 211276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_PLL_RF5112 0x00000040 211376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_PLL_HALF_RATE 0x00000100 211476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_PLL_QUARTER_RATE 0x00000200 211576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 211676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 211776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * RF Buffer register 211876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 211976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * It's obvious from the code that 0x989c is the buffer register but 212076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * for the other special registers that we write to after sending each 212176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * packet, i have no idea. So i'll name them BUFFER_CONTROL_X registers 212276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * for now. It's interesting that they are also used for some other operations. 212376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 212476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 212576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RF_BUFFER 0x989c 212676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RF_BUFFER_CONTROL_0 0x98c0 /* Channel on 5110 */ 212776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RF_BUFFER_CONTROL_1 0x98c4 /* Bank 7 on 5112 */ 212876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RF_BUFFER_CONTROL_2 0x98cc /* Bank 7 on 5111 */ 212976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 213076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RF_BUFFER_CONTROL_3 0x98d0 /* Bank 2 on 5112 */ 213176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman /* Channel set on 5111 */ 213276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman /* Used to read radio revision*/ 213376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 213476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RF_BUFFER_CONTROL_4 0x98d4 /* RF Stage register on 5110 */ 213576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman /* Bank 0,1,2,6 on 5111 */ 213676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman /* Bank 1 on 5112 */ 213776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman /* Used during activation on 5111 */ 213876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 213976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RF_BUFFER_CONTROL_5 0x98d8 /* Bank 3 on 5111 */ 214076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman /* Used during activation on 5111 */ 214176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman /* Channel on 5112 */ 214276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman /* Bank 6 on 5112 */ 214376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 214476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RF_BUFFER_CONTROL_6 0x98dc /* Bank 3 on 5112 */ 214576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 214676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 214776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * PHY RF stage register [5210] 214876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 214976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_RFSTG 0x98d4 215076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_RFSTG_DISABLE 0x00000021 215176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 215276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 215376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * BIN masks (?) 215476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 215576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_BIN_MASK_1 0x9900 215676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_BIN_MASK_2 0x9904 215776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_BIN_MASK_3 0x9908 215876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 215976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_BIN_MASK_CTL 0x990c 216076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_BIN_MASK_CTL_MASK_4 0x00003fff 216176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_BIN_MASK_CTL_MASK_4_S 0 216276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_BIN_MASK_CTL_RATE 0xff000000 216376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_BIN_MASK_CTL_RATE_S 24 216476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 216576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 216676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * PHY Antenna control register 216776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 216876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_ANT_CTL 0x9910 /* Register Address */ 216976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_ANT_CTL_TXRX_EN 0x00000001 /* Enable TX/RX (?) */ 217076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_ANT_CTL_SECTORED_ANT 0x00000004 /* Sectored Antenna */ 217176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_ANT_CTL_HITUNE5 0x00000008 /* Hitune5 (?) */ 217276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_ANT_CTL_SWTABLE_IDLE 0x000003f0 /* Switch table idle (?) */ 217376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_ANT_CTL_SWTABLE_IDLE_S 4 217476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 217576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 217676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * PHY receiver delay register [5111+] 217776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 217876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_RX_DELAY 0x9914 /* Register Address */ 217976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_RX_DELAY_M 0x00003fff /* Mask for RX activate to receive delay (/100ns) */ 218076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 218176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 218276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * PHY max rx length register (?) [5111] 218376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 218476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_MAX_RX_LEN 0x991c 218576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 218676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 218776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * PHY timing register 4 218876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * I(nphase)/Q(adrature) calibration register [5111+] 218976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 219076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_IQ 0x9920 /* Register Address */ 219176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_IQ_CORR_Q_Q_COFF 0x0000001f /* Mask for q correction info */ 219276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_IQ_CORR_Q_I_COFF 0x000007e0 /* Mask for i correction info */ 219376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_IQ_CORR_Q_I_COFF_S 5 219476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_IQ_CORR_ENABLE 0x00000800 /* Enable i/q correction */ 219576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_IQ_CAL_NUM_LOG_MAX 0x0000f000 /* Mask for max number of samples in log scale */ 219676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_IQ_CAL_NUM_LOG_MAX_S 12 219776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_IQ_RUN 0x00010000 /* Run i/q calibration */ 219876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_IQ_USE_PT_DF 0x00020000 /* Use pilot track df (?) */ 219976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_IQ_EARLY_TRIG_THR 0x00200000 /* Early trigger threshold (?) (field) */ 220076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_IQ_PILOT_MASK_EN 0x10000000 /* Enable pilot mask (?) */ 220176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_IQ_CHAN_MASK_EN 0x20000000 /* Enable channel mask (?) */ 220276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_IQ_SPUR_FILT_EN 0x40000000 /* Enable spur filter */ 220376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_IQ_SPUR_RSSI_EN 0x80000000 /* Enable spur rssi */ 220476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 220576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 220676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * PHY timing register 5 220776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * OFDM Self-correlator Cyclic RSSI threshold params 220876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * (Check out bb_cycpwr_thr1 on ANI patent) 220976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 221076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_OFDM_SELFCORR 0x9924 /* Register Address */ 221176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1_EN 0x00000001 /* Enable cyclic RSSI thr 1 */ 221276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1 0x000000fe /* Mask for Cyclic RSSI threshold 1 */ 221376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1_S 1 221476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR3 0x00000100 /* Cyclic RSSI threshold 3 (field) (?) */ 221576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_OFDM_SELFCORR_RSSI_1ATHR_EN 0x00008000 /* Enable 1A RSSI threshold (?) */ 221676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_OFDM_SELFCORR_RSSI_1ATHR 0x00010000 /* 1A RSSI threshold (field) (?) */ 221776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_OFDM_SELFCORR_LSCTHR_HIRSSI 0x00800000 /* Long sc threshold hi rssi (?) */ 221876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 221976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 222076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * PHY-only warm reset register 222176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 222276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_WARM_RESET 0x9928 222376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 222476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 222576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * PHY-only control register 222676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 222776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_CTL 0x992c /* Register Address */ 222876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_CTL_RX_DRAIN_RATE 0x00000001 /* RX drain rate (?) */ 222976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_CTL_LATE_TX_SIG_SYM 0x00000002 /* Late tx signal symbol (?) */ 223076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_CTL_GEN_SCRAMBLER 0x00000004 /* Generate scrambler */ 223176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_CTL_TX_ANT_SEL 0x00000008 /* TX antenna select */ 223276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_CTL_TX_ANT_STATIC 0x00000010 /* Static TX antenna */ 223376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_CTL_RX_ANT_SEL 0x00000020 /* RX antenna select */ 223476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_CTL_RX_ANT_STATIC 0x00000040 /* Static RX antenna */ 223576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_CTL_LOW_FREQ_SLE_EN 0x00000080 /* Enable low freq sleep */ 223676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 223776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 223876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * PHY PAPD probe register [5111+] 223976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 224076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_PAPD_PROBE 0x9930 224176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_PAPD_PROBE_SH_HI_PAR 0x00000001 224276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_PAPD_PROBE_PCDAC_BIAS 0x00000002 224376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_PAPD_PROBE_COMP_GAIN 0x00000040 224476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_PAPD_PROBE_TXPOWER 0x00007e00 224576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_PAPD_PROBE_TXPOWER_S 9 224676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_PAPD_PROBE_TX_NEXT 0x00008000 224776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_PAPD_PROBE_PREDIST_EN 0x00010000 224876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_PAPD_PROBE_TYPE 0x01800000 /* [5112+] */ 224976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_PAPD_PROBE_TYPE_S 23 225076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_PAPD_PROBE_TYPE_OFDM 0 225176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_PAPD_PROBE_TYPE_XR 1 225276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_PAPD_PROBE_TYPE_CCK 2 225376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_PAPD_PROBE_GAINF 0xfe000000 225476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_PAPD_PROBE_GAINF_S 25 225576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_PAPD_PROBE_INI_5111 0x00004883 /* [5212+] */ 225676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_PAPD_PROBE_INI_5112 0x00004882 /* [5212+] */ 225776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 225876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 225976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * PHY TX rate power registers [5112+] 226076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 226176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TXPOWER_RATE1 0x9934 226276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TXPOWER_RATE2 0x9938 226376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TXPOWER_RATE_MAX 0x993c 226476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE 0x00000040 226576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TXPOWER_RATE3 0xa234 226676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TXPOWER_RATE4 0xa238 226776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 226876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 226976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * PHY frame control register [5111+] 227076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 227176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_FRAME_CTL_5210 0x9804 227276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_FRAME_CTL_5211 0x9944 227376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_FRAME_CTL (ah->ah_version == AR5K_AR5210 ? \ 227476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman AR5K_PHY_FRAME_CTL_5210 : AR5K_PHY_FRAME_CTL_5211) 227576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/*---[5111+]---*/ 227676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_FRAME_CTL_TX_CLIP 0x00000038 /* Mask for tx clip (?) */ 227776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_FRAME_CTL_TX_CLIP_S 3 227876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_FRAME_CTL_PREP_CHINFO 0x00010000 /* Prepend chan info */ 227976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_FRAME_CTL_EMU 0x80000000 228076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_FRAME_CTL_EMU_S 31 228176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/*---[5110/5111]---*/ 228276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_FRAME_CTL_TIMING_ERR 0x01000000 /* PHY timing error */ 228376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_FRAME_CTL_PARITY_ERR 0x02000000 /* Parity error */ 228476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_FRAME_CTL_ILLRATE_ERR 0x04000000 /* Illegal rate */ 228576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_FRAME_CTL_ILLLEN_ERR 0x08000000 /* Illegal length */ 228676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_FRAME_CTL_SERVICE_ERR 0x20000000 228776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_FRAME_CTL_TXURN_ERR 0x40000000 /* TX underrun */ 228876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_FRAME_CTL_INI AR5K_PHY_FRAME_CTL_SERVICE_ERR | \ 228976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman AR5K_PHY_FRAME_CTL_TXURN_ERR | \ 229076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman AR5K_PHY_FRAME_CTL_ILLLEN_ERR | \ 229176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman AR5K_PHY_FRAME_CTL_ILLRATE_ERR | \ 229276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman AR5K_PHY_FRAME_CTL_PARITY_ERR | \ 229376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman AR5K_PHY_FRAME_CTL_TIMING_ERR 229476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 229576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 229676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * PHY Tx Power adjustment register [5212A+] 229776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 229876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TX_PWR_ADJ 0x994c 229976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DELTA 0x00000fc0 230076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DELTA_S 6 230176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_INDEX 0x00fc0000 230276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_INDEX_S 18 230376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 230476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 230576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * PHY radar detection register [5111+] 230676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 230776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_RADAR 0x9954 230876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_RADAR_ENABLE 0x00000001 230976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_RADAR_DISABLE 0x00000000 231076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_RADAR_INBANDTHR 0x0000003e /* Inband threshold 231176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 5-bits, units unknown {0..31} 231276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman (? MHz ?) */ 231376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_RADAR_INBANDTHR_S 1 231476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 231576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_RADAR_PRSSI_THR 0x00000fc0 /* Pulse RSSI/SNR threshold 231676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 6-bits, dBm range {0..63} 231776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman in dBm units. */ 231876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_RADAR_PRSSI_THR_S 6 231976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 232076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_RADAR_PHEIGHT_THR 0x0003f000 /* Pulse height threshold 232176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 6-bits, dBm range {0..63} 232276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman in dBm units. */ 232376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_RADAR_PHEIGHT_THR_S 12 232476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 232576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_RADAR_RSSI_THR 0x00fc0000 /* Radar RSSI/SNR threshold. 232676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 6-bits, dBm range {0..63} 232776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman in dBm units. */ 232876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_RADAR_RSSI_THR_S 18 232976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 233076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_RADAR_FIRPWR_THR 0x7f000000 /* Finite Impulse Response 233176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman filter power out threshold. 233276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 7-bits, standard power range 233376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman {0..127} in 1/2 dBm units. */ 233476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_RADAR_FIRPWR_THRS 24 233576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 233676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 233776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * PHY antenna switch table registers 233876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 233976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_ANT_SWITCH_TABLE_0 0x9960 234076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_ANT_SWITCH_TABLE_1 0x9964 234176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 234276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 234376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * PHY Noise floor threshold 234476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 234576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_NFTHRES 0x9968 234676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 234776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 234876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Sigma Delta register (?) [5213] 234976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 235076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_SIGMA_DELTA 0x996C 235176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_SIGMA_DELTA_ADC_SEL 0x00000003 235276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_SIGMA_DELTA_ADC_SEL_S 0 235376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_SIGMA_DELTA_FILT2 0x000000f8 235476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_SIGMA_DELTA_FILT2_S 3 235576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_SIGMA_DELTA_FILT1 0x00001f00 235676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_SIGMA_DELTA_FILT1_S 8 235776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_SIGMA_DELTA_ADC_CLIP 0x01ffe000 235876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_SIGMA_DELTA_ADC_CLIP_S 13 235976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 236076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 236176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * RF restart register [5112+] (?) 236276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 236376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_RESTART 0x9970 /* restart */ 236476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_RESTART_DIV_GC 0x001c0000 /* Fast diversity gc_limit (?) */ 236576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_RESTART_DIV_GC_S 18 236676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 236776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 236876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * RF Bus access request register (for synth-oly channel switching) 236976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 237076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_RFBUS_REQ 0x997C 237176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_RFBUS_REQ_REQUEST 0x00000001 237276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 237376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 237476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Spur mitigation masks (?) 237576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 237676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TIMING_7 0x9980 237776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TIMING_8 0x9984 237876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TIMING_8_PILOT_MASK_2 0x000fffff 237976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TIMING_8_PILOT_MASK_2_S 0 238076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 238176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_BIN_MASK2_1 0x9988 238276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_BIN_MASK2_2 0x998c 238376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_BIN_MASK2_3 0x9990 238476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 238576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_BIN_MASK2_4 0x9994 238676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_BIN_MASK2_4_MASK_4 0x00003fff 238776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_BIN_MASK2_4_MASK_4_S 0 238876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 238976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TIMING_9 0x9998 239076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TIMING_10 0x999c 239176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TIMING_10_PILOT_MASK_2 0x000fffff 239276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TIMING_10_PILOT_MASK_2_S 0 239376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 239476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 239576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Spur mitigation control 239676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 239776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TIMING_11 0x99a0 /* Register address */ 239876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE 0x000fffff /* Spur delta phase */ 239976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE_S 0 240076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TIMING_11_SPUR_FREQ_SD 0x3ff00000 /* Freq sigma delta */ 240176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TIMING_11_SPUR_FREQ_SD_S 20 240276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TIMING_11_USE_SPUR_IN_AGC 0x40000000 /* Spur filter in AGC detector */ 240376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TIMING_11_USE_SPUR_IN_SELFCOR 0x80000000 /* Spur filter in OFDM self correlator */ 240476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 240576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 240676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Gain tables 240776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 240876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_BB_GAIN_BASE 0x9b00 /* BaseBand Amplifier Gain table base address */ 240976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_BB_GAIN(_n) (AR5K_BB_GAIN_BASE + ((_n) << 2)) 241076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RF_GAIN_BASE 0x9a00 /* RF Amplrifier Gain table base address */ 241176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_RF_GAIN(_n) (AR5K_RF_GAIN_BASE + ((_n) << 2)) 241276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 241376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 241476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * PHY timing IQ calibration result register [5111+] 241576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 241676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_IQRES_CAL_PWR_I 0x9c10 /* I (Inphase) power value */ 241776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_IQRES_CAL_PWR_Q 0x9c14 /* Q (Quadrature) power value */ 241876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_IQRES_CAL_CORR 0x9c18 /* I/Q Correlation */ 241976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 242076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 242176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * PHY current RSSI register [5111+] 242276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 242376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_CURRENT_RSSI 0x9c1c 242476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 242576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 242676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * PHY RF Bus grant register 242776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 242876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_RFBUS_GRANT 0x9c20 242976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_RFBUS_GRANT_OK 0x00000001 243076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 243176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 243276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * PHY ADC test register 243376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 243476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_ADC_TEST 0x9c24 243576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_ADC_TEST_I 0x00000001 243676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_ADC_TEST_Q 0x00000200 243776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 243876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 243976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * PHY DAC test register 244076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 244176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_DAC_TEST 0x9c28 244276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_DAC_TEST_I 0x00000001 244376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_DAC_TEST_Q 0x00000200 244476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 244576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 244676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * PHY PTAT register (?) 244776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 244876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_PTAT 0x9c2c 244976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 245076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 245176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * PHY Illegal TX rate register [5112+] 245276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 245376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_BAD_TX_RATE 0x9c30 245476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 245576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 245676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * PHY SPUR Power register [5112+] 245776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 245876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_SPUR_PWR 0x9c34 /* Register Address */ 245976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_SPUR_PWR_I 0x00000001 /* SPUR Power estimate for I (field) */ 246076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_SPUR_PWR_Q 0x00000100 /* SPUR Power estimate for Q (field) */ 246176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_SPUR_PWR_FILT 0x00010000 /* Power with SPUR removed (field) */ 246276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 246376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 246476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * PHY Channel status register [5112+] (?) 246576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 246676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_CHAN_STATUS 0x9c38 246776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_CHAN_STATUS_BT_ACT 0x00000001 246876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_CHAN_STATUS_RX_CLR_RAW 0x00000002 246976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_CHAN_STATUS_RX_CLR_MAC 0x00000004 247076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_CHAN_STATUS_RX_CLR_PAP 0x00000008 247176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 247276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 247376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Heavy clip enable register 247476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 247576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_HEAVY_CLIP_ENABLE 0x99e0 247676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 247776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 247876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * PHY clock sleep registers [5112+] 247976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 248076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_SCLOCK 0x99f0 248176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_SCLOCK_32MHZ 0x0000000c 248276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_SDELAY 0x99f4 248376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_SDELAY_32MHZ 0x000000ff 248476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_SPENDING 0x99f8 248576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 248676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 248776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 248876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * PHY PAPD I (power?) table (?) 248976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * (92! entries) 249076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 249176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_PAPD_I_BASE 0xa000 249276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_PAPD_I(_n) (AR5K_PHY_PAPD_I_BASE + ((_n) << 2)) 249376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 249476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 249576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * PHY PCDAC TX power table 249676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 249776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_PCDAC_TXPOWER_BASE 0xa180 249876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_PCDAC_TXPOWER(_n) (AR5K_PHY_PCDAC_TXPOWER_BASE + ((_n) << 2)) 249976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 250076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 250176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * PHY mode register [5111+] 250276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 250376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_MODE 0x0a200 /* Register Address */ 250476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_MODE_MOD 0x00000001 /* PHY Modulation bit */ 250576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_MODE_MOD_OFDM 0 250676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_MODE_MOD_CCK 1 250776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_MODE_FREQ 0x00000002 /* Freq mode bit */ 250876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_MODE_FREQ_5GHZ 0 250976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_MODE_FREQ_2GHZ 2 251076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_MODE_MOD_DYN 0x00000004 /* Enable Dynamic OFDM/CCK mode [5112+] */ 251176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_MODE_RAD 0x00000008 /* [5212+] */ 251276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_MODE_RAD_RF5111 0 251376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_MODE_RAD_RF5112 8 251476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_MODE_XR 0x00000010 /* Enable XR mode [5112+] */ 251576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_MODE_HALF_RATE 0x00000020 /* Enable Half rate (test) */ 251676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_MODE_QUARTER_RATE 0x00000040 /* Enable Quarter rat (test) */ 251776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 251876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 251976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * PHY CCK transmit control register [5111+ (?)] 252076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 252176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_CCKTXCTL 0xa204 252276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_CCKTXCTL_WORLD 0x00000000 252376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_CCKTXCTL_JAPAN 0x00000010 252476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_CCKTXCTL_SCRAMBLER_DIS 0x00000001 252576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_CCKTXCTK_DAC_SCALE 0x00000004 252676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 252776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 252876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * PHY CCK Cross-correlator Barker RSSI threshold register [5212+] 252976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 253076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_CCK_CROSSCORR 0xa208 253176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_CCK_CROSSCORR_WEAK_SIG_THR 0x0000000f 253276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_CCK_CROSSCORR_WEAK_SIG_THR_S 0 253376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 253476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Same address is used for antenna diversity activation */ 253576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_FAST_ANT_DIV 0xa208 253676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_FAST_ANT_DIV_EN 0x00002000 253776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 253876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 253976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * PHY 2GHz gain register [5111+] 254076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 254176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_GAIN_2GHZ 0xa20c 254276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX 0x00fc0000 254376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX_S 18 254476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_GAIN_2GHZ_INI_5111 0x6480416c 254576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 254676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_CCK_RX_CTL_4 0xa21c 254776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_CCK_RX_CTL_4_FREQ_EST_SHORT 0x01f80000 254876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_CCK_RX_CTL_4_FREQ_EST_SHORT_S 19 254976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 255076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_DAG_CCK_CTL 0xa228 255176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_DAG_CCK_CTL_EN_RSSI_THR 0x00000200 255276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_DAG_CCK_CTL_RSSI_THR 0x0001fc00 255376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_DAG_CCK_CTL_RSSI_THR_S 10 255476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 255576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_FAST_ADC 0xa24c 255676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 255776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_BLUETOOTH 0xa254 255876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 255976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 256076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Transmit Power Control register 256176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * [2413+] 256276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 256376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TPC_RG1 0xa258 256476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TPC_RG1_NUM_PD_GAIN 0x0000c000 256576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TPC_RG1_NUM_PD_GAIN_S 14 256676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TPC_RG1_PDGAIN_1 0x00030000 256776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TPC_RG1_PDGAIN_1_S 16 256876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TPC_RG1_PDGAIN_2 0x000c0000 256976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TPC_RG1_PDGAIN_2_S 18 257076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TPC_RG1_PDGAIN_3 0x00300000 257176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TPC_RG1_PDGAIN_3_S 20 257276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 257376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TPC_RG5 0xa26C 257476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP 0x0000000F 257576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP_S 0 257676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1 0x000003F0 257776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1_S 4 257876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2 0x0000FC00 257976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2_S 10 258076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3 0x003F0000 258176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3_S 16 258276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4 0x0FC00000 258376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4_S 22 258476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 258576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 258676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * PHY PDADC Tx power table 258776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 258876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_PDADC_TXPOWER_BASE 0xa280 258976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AR5K_PHY_PDADC_TXPOWER(_n) (AR5K_PHY_PDADC_TXPOWER_BASE + ((_n) << 2)) 2590