176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#ifdef ALLMULTI 276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#error multicast support is not yet implemented 376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#endif 476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/************************************************************************** 576d05dc695b06c4e987bb8078f78032441e1430cGreg HartmanEtherboot - BOOTP/TFTP Bootstrap Program 676d05dc695b06c4e987bb8078f78032441e1430cGreg HartmanIntel EEPRO/10 NIC driver for Etherboot 776d05dc695b06c4e987bb8078f78032441e1430cGreg HartmanAdapted from Linux eepro.c from kernel 2.2.17 876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 976d05dc695b06c4e987bb8078f78032441e1430cGreg HartmanThis board accepts a 32 pin EEPROM (29C256), however a test with a 1076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman27C010 shows that this EPROM also works in the socket, but it's not clear 1176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanhow repeatably. The two top address pins appear to be held low, thus 1276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanthe bottom 32kB of the 27C010 is visible in the CPU's address space. 1376d05dc695b06c4e987bb8078f78032441e1430cGreg HartmanTo be sure you could put 4 copies of the code in the 27C010, then 1476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanit doesn't matter whether the extra lines are held low or high, just 1576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanhopefully not floating as CMOS chips don't like floating inputs. 1676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 1776d05dc695b06c4e987bb8078f78032441e1430cGreg HartmanBe careful with seating the EPROM as the socket on my board actually 1876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanhas 34 pins, the top row of 2 are not used. 1976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman***************************************************************************/ 2076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 2176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 2276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 2376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman timlegge 2005-05-18 remove the relocation changes cards that 2476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman write directly to the hardware don't need it 2576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman*/ 2676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 2776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 2876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * This program is free software; you can redistribute it and/or 2976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * modify it under the terms of the GNU General Public License as 3076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * published by the Free Software Foundation; either version 2, or (at 3176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * your option) any later version. 3276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 3376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 3476d05dc695b06c4e987bb8078f78032441e1430cGreg HartmanFILE_LICENCE ( GPL2_OR_LATER ); 3576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 3676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#include "etherboot.h" 3776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#include <errno.h> 3876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#include "nic.h" 3976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#include <gpxe/isa.h> 4076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#include <gpxe/ethernet.h> 4176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 4276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Different 82595 chips */ 4376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define LAN595 0 4476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define LAN595TX 1 4576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define LAN595FX 2 4676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define LAN595FX_10ISA 3 4776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 4876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define SLOW_DOWN inb(0x80); 4976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 5076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* The station (ethernet) address prefix, used for IDing the board. */ 5176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define SA_ADDR0 0x00 /* Etherexpress Pro/10 */ 5276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define SA_ADDR1 0xaa 5376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define SA_ADDR2 0x00 5476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 5576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define GetBit(x,y) ((x & (1<<y))>>y) 5676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 5776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* EEPROM Word 0: */ 5876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ee_PnP 0 /* Plug 'n Play enable bit */ 5976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ee_Word1 1 /* Word 1? */ 6076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ee_BusWidth 2 /* 8/16 bit */ 6176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ee_FlashAddr 3 /* Flash Address */ 6276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ee_FlashMask 0x7 /* Mask */ 6376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ee_AutoIO 6 /* */ 6476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ee_reserved0 7 /* =0! */ 6576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ee_Flash 8 /* Flash there? */ 6676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ee_AutoNeg 9 /* Auto Negotiation enabled? */ 6776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ee_IO0 10 /* IO Address LSB */ 6876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ee_IO0Mask 0x /*...*/ 6976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ee_IO1 15 /* IO MSB */ 7076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 7176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* EEPROM Word 1: */ 7276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ee_IntSel 0 /* Interrupt */ 7376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ee_IntMask 0x7 7476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ee_LI 3 /* Link Integrity 0= enabled */ 7576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ee_PC 4 /* Polarity Correction 0= enabled */ 7676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ee_TPE_AUI 5 /* PortSelection 1=TPE */ 7776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ee_Jabber 6 /* Jabber prevention 0= enabled */ 7876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ee_AutoPort 7 /* Auto Port Selection 1= Disabled */ 7976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ee_SMOUT 8 /* SMout Pin Control 0= Input */ 8076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ee_PROM 9 /* Flash EPROM / PROM 0=Flash */ 8176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ee_reserved1 10 /* .. 12 =0! */ 8276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ee_AltReady 13 /* Alternate Ready, 0=normal */ 8376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ee_reserved2 14 /* =0! */ 8476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ee_Duplex 15 8576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 8676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Word2,3,4: */ 8776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ee_IA5 0 /*bit start for individual Addr Byte 5 */ 8876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ee_IA4 8 /*bit start for individual Addr Byte 5 */ 8976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ee_IA3 0 /*bit start for individual Addr Byte 5 */ 9076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ee_IA2 8 /*bit start for individual Addr Byte 5 */ 9176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ee_IA1 0 /*bit start for individual Addr Byte 5 */ 9276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ee_IA0 8 /*bit start for individual Addr Byte 5 */ 9376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 9476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Word 5: */ 9576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ee_BNC_TPE 0 /* 0=TPE */ 9676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ee_BootType 1 /* 00=None, 01=IPX, 10=ODI, 11=NDIS */ 9776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ee_BootTypeMask 0x3 9876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ee_NumConn 3 /* Number of Connections 0= One or Two */ 9976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ee_FlashSock 4 /* Presence of Flash Socket 0= Present */ 10076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ee_PortTPE 5 10176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ee_PortBNC 6 10276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ee_PortAUI 7 10376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ee_PowerMgt 10 /* 0= disabled */ 10476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ee_CP 13 /* Concurrent Processing */ 10576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ee_CPMask 0x7 10676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 10776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Word 6: */ 10876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ee_Stepping 0 /* Stepping info */ 10976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ee_StepMask 0x0F 11076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ee_BoardID 4 /* Manucaturer Board ID, reserved */ 11176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ee_BoardMask 0x0FFF 11276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 11376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Word 7: */ 11476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ee_INT_TO_IRQ 0 /* int to IRQ Mapping = 0x1EB8 for Pro/10+ */ 11576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ee_FX_INT2IRQ 0x1EB8 /* the _only_ mapping allowed for FX chips */ 11676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 11776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/*..*/ 11876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ee_SIZE 0x40 /* total EEprom Size */ 11976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ee_Checksum 0xBABA /* initial and final value for adding checksum */ 12076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 12176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 12276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Card identification via EEprom: */ 12376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ee_addr_vendor 0x10 /* Word offset for EISA Vendor ID */ 12476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ee_addr_id 0x11 /* Word offset for Card ID */ 12576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ee_addr_SN 0x12 /* Serial Number */ 12676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ee_addr_CRC_8 0x14 /* CRC over last thee Bytes */ 12776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 12876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 12976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ee_vendor_intel0 0x25 /* Vendor ID Intel */ 13076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ee_vendor_intel1 0xD4 13176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ee_id_eepro10p0 0x10 /* ID for eepro/10+ */ 13276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ee_id_eepro10p1 0x31 13376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 13476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* now this section could be used by both boards: the oldies and the ee10: 13576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * ee10 uses tx buffer before of rx buffer and the oldies the inverse. 13676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * (aris) 13776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 13876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RAM_SIZE 0x8000 13976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 14076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RCV_HEADER 8 14176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RCV_DEFAULT_RAM 0x6000 14276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RCV_RAM rcv_ram 14376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 14476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstatic unsigned rcv_ram = RCV_DEFAULT_RAM; 14576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 14676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define XMT_HEADER 8 14776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define XMT_RAM (RAM_SIZE - RCV_RAM) 14876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 14976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define XMT_START ((rcv_start + RCV_RAM) % RAM_SIZE) 15076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 15176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RCV_LOWER_LIMIT (rcv_start >> 8) 15276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RCV_UPPER_LIMIT (((rcv_start + RCV_RAM) - 2) >> 8) 15376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define XMT_LOWER_LIMIT (XMT_START >> 8) 15476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define XMT_UPPER_LIMIT (((XMT_START + XMT_RAM) - 2) >> 8) 15576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 15676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RCV_START_PRO 0x00 15776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RCV_START_10 XMT_RAM 15876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman /* by default the old driver */ 15976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstatic unsigned rcv_start = RCV_START_PRO; 16076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 16176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RCV_DONE 0x0008 16276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RX_OK 0x2000 16376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RX_ERROR 0x0d81 16476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 16576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define TX_DONE_BIT 0x0080 16676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define CHAIN_BIT 0x8000 16776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define XMT_STATUS 0x02 16876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define XMT_CHAIN 0x04 16976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define XMT_COUNT 0x06 17076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 17176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define BANK0_SELECT 0x00 17276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define BANK1_SELECT 0x40 17376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define BANK2_SELECT 0x80 17476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 17576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Bank 0 registers */ 17676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define COMMAND_REG 0x00 /* Register 0 */ 17776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define MC_SETUP 0x03 17876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define XMT_CMD 0x04 17976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define DIAGNOSE_CMD 0x07 18076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RCV_ENABLE_CMD 0x08 18176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RCV_DISABLE_CMD 0x0a 18276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define STOP_RCV_CMD 0x0b 18376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RESET_CMD 0x0e 18476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define POWER_DOWN_CMD 0x18 18576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RESUME_XMT_CMD 0x1c 18676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define SEL_RESET_CMD 0x1e 18776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define STATUS_REG 0x01 /* Register 1 */ 18876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RX_INT 0x02 18976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define TX_INT 0x04 19076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define EXEC_STATUS 0x30 19176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ID_REG 0x02 /* Register 2 */ 19276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define R_ROBIN_BITS 0xc0 /* round robin counter */ 19376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ID_REG_MASK 0x2c 19476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ID_REG_SIG 0x24 19576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define AUTO_ENABLE 0x10 19676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define INT_MASK_REG 0x03 /* Register 3 */ 19776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RX_STOP_MASK 0x01 19876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RX_MASK 0x02 19976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define TX_MASK 0x04 20076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define EXEC_MASK 0x08 20176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ALL_MASK 0x0f 20276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define IO_32_BIT 0x10 20376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RCV_BAR 0x04 /* The following are word (16-bit) registers */ 20476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RCV_STOP 0x06 20576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 20676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define XMT_BAR_PRO 0x0a 20776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define XMT_BAR_10 0x0b 20876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstatic unsigned xmt_bar = XMT_BAR_PRO; 20976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 21076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define HOST_ADDRESS_REG 0x0c 21176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define IO_PORT 0x0e 21276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define IO_PORT_32_BIT 0x0c 21376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 21476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Bank 1 registers */ 21576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define REG1 0x01 21676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define WORD_WIDTH 0x02 21776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define INT_ENABLE 0x80 21876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define INT_NO_REG 0x02 21976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RCV_LOWER_LIMIT_REG 0x08 22076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RCV_UPPER_LIMIT_REG 0x09 22176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 22276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define XMT_LOWER_LIMIT_REG_PRO 0x0a 22376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define XMT_UPPER_LIMIT_REG_PRO 0x0b 22476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define XMT_LOWER_LIMIT_REG_10 0x0b 22576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define XMT_UPPER_LIMIT_REG_10 0x0a 22676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstatic unsigned xmt_lower_limit_reg = XMT_LOWER_LIMIT_REG_PRO; 22776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstatic unsigned xmt_upper_limit_reg = XMT_UPPER_LIMIT_REG_PRO; 22876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 22976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Bank 2 registers */ 23076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define XMT_Chain_Int 0x20 /* Interrupt at the end of the transmit chain */ 23176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define XMT_Chain_ErrStop 0x40 /* Interrupt at the end of the chain even if there are errors */ 23276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RCV_Discard_BadFrame 0x80 /* Throw bad frames away, and continue to receive others */ 23376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define REG2 0x02 23476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PRMSC_Mode 0x01 23576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define Multi_IA 0x20 23676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define REG3 0x03 23776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define TPE_BIT 0x04 23876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define BNC_BIT 0x20 23976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define REG13 0x0d 24076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define FDX 0x00 24176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define A_N_ENABLE 0x02 24276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 24376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define I_ADD_REG0 0x04 24476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define I_ADD_REG1 0x05 24576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define I_ADD_REG2 0x06 24676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define I_ADD_REG3 0x07 24776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define I_ADD_REG4 0x08 24876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define I_ADD_REG5 0x09 24976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 25076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define EEPROM_REG_PRO 0x0a 25176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define EEPROM_REG_10 0x0b 25276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstatic unsigned eeprom_reg = EEPROM_REG_PRO; 25376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 25476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define EESK 0x01 25576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define EECS 0x02 25676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define EEDI 0x04 25776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define EEDO 0x08 25876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 25976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* The horrible routine to read a word from the serial EEPROM. */ 26076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* IMPORTANT - the 82595 will be set to Bank 0 after the eeprom is read */ 26176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 26276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* The delay between EEPROM clock transitions. */ 26376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define eeprom_delay() { udelay(40); } 26476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define EE_READ_CMD (6 << 6) 26576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 26676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* do a full reset; data sheet asks for 250us delay */ 26776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define eepro_full_reset(ioaddr) outb(RESET_CMD, ioaddr); udelay(255); 26876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 26976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* do a nice reset */ 27076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define eepro_sel_reset(ioaddr) \ 27176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman do { \ 27276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman outb ( SEL_RESET_CMD, ioaddr ); \ 27376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman (void) SLOW_DOWN; \ 27476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman (void) SLOW_DOWN; \ 27576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman } while (0) 27676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 27776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* clear all interrupts */ 27876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define eepro_clear_int(ioaddr) outb(ALL_MASK, ioaddr + STATUS_REG) 27976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 28076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* enable rx */ 28176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define eepro_en_rx(ioaddr) outb(RCV_ENABLE_CMD, ioaddr) 28276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 28376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* disable rx */ 28476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define eepro_dis_rx(ioaddr) outb(RCV_DISABLE_CMD, ioaddr) 28576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 28676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* switch bank */ 28776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define eepro_sw2bank0(ioaddr) outb(BANK0_SELECT, ioaddr) 28876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define eepro_sw2bank1(ioaddr) outb(BANK1_SELECT, ioaddr) 28976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define eepro_sw2bank2(ioaddr) outb(BANK2_SELECT, ioaddr) 29076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 29176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstatic unsigned int rx_start, tx_start; 29276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstatic int tx_last; 29376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstatic unsigned int tx_end; 29476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstatic int eepro = 0; 29576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstatic unsigned int mem_start, mem_end = RCV_DEFAULT_RAM / 1024; 29676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 29776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/************************************************************************** 29876d05dc695b06c4e987bb8078f78032441e1430cGreg HartmanRESET - Reset adapter 29976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman***************************************************************************/ 30076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstatic void eepro_reset(struct nic *nic) 30176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman{ 30276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman int temp_reg, i; 30376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 30476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman /* put the card in its initial state */ 30576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman eepro_sw2bank2(nic->ioaddr); /* be careful, bank2 now */ 30676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman temp_reg = inb(nic->ioaddr + eeprom_reg); 30776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman DBG("Stepping %d\n", temp_reg >> 5); 30876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman if (temp_reg & 0x10) /* check the TurnOff Enable bit */ 30976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman outb(temp_reg & 0xEF, nic->ioaddr + eeprom_reg); 31076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman for (i = 0; i < ETH_ALEN; i++) /* fill the MAC address */ 31176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman outb(nic->node_addr[i], nic->ioaddr + I_ADD_REG0 + i); 31276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman temp_reg = inb(nic->ioaddr + REG1); 31376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman /* setup Transmit Chaining and discard bad RCV frames */ 31476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman outb(temp_reg | XMT_Chain_Int | XMT_Chain_ErrStop 31576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman | RCV_Discard_BadFrame, nic->ioaddr + REG1); 31676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman temp_reg = inb(nic->ioaddr + REG2); /* match broadcast */ 31776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman outb(temp_reg | 0x14, nic->ioaddr + REG2); 31876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman temp_reg = inb(nic->ioaddr + REG3); 31976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman outb(temp_reg & 0x3F, nic->ioaddr + REG3); /* clear test mode */ 32076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman /* set the receiving mode */ 32176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman eepro_sw2bank1(nic->ioaddr); /* be careful, bank1 now */ 32276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman /* initialise the RCV and XMT upper and lower limits */ 32376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman outb(RCV_LOWER_LIMIT, nic->ioaddr + RCV_LOWER_LIMIT_REG); 32476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman outb(RCV_UPPER_LIMIT, nic->ioaddr + RCV_UPPER_LIMIT_REG); 32576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman outb(XMT_LOWER_LIMIT, nic->ioaddr + xmt_lower_limit_reg); 32676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman outb(XMT_UPPER_LIMIT, nic->ioaddr + xmt_upper_limit_reg); 32776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman eepro_sw2bank0(nic->ioaddr); /* Switch back to bank 0 */ 32876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman eepro_clear_int(nic->ioaddr); 32976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman /* Initialise RCV */ 33076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman outw(rx_start = (RCV_LOWER_LIMIT << 8), nic->ioaddr + RCV_BAR); 33176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman outw(((RCV_UPPER_LIMIT << 8) | 0xFE), nic->ioaddr + RCV_STOP); 33276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman /* Make sure 1st poll won't find a valid packet header */ 33376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman outw((RCV_LOWER_LIMIT << 8), nic->ioaddr + HOST_ADDRESS_REG); 33476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman outw(0, nic->ioaddr + IO_PORT); 33576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman /* Intialise XMT */ 33676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman outw((XMT_LOWER_LIMIT << 8), nic->ioaddr + xmt_bar); 33776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman eepro_sel_reset(nic->ioaddr); 33876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman tx_start = tx_end = (unsigned int) (XMT_LOWER_LIMIT << 8); 33976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman tx_last = 0; 34076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman eepro_en_rx(nic->ioaddr); 34176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman} 34276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 34376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/************************************************************************** 34476d05dc695b06c4e987bb8078f78032441e1430cGreg HartmanPOLL - Wait for a frame 34576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman***************************************************************************/ 34676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstatic int eepro_poll(struct nic *nic, int retrieve) 34776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman{ 34876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman unsigned int rcv_car = rx_start; 34976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman unsigned int rcv_event, rcv_status, rcv_next_frame, rcv_size; 35076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 35176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman /* return true if there's an ethernet packet ready to read */ 35276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman /* nic->packet should contain data on return */ 35376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman /* nic->packetlen should contain length of data */ 35476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#if 0 35576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman if ((inb(nic->ioaddr + STATUS_REG) & 0x40) == 0) 35676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman return (0); 35776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman outb(0x40, nic->ioaddr + STATUS_REG); 35876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#endif 35976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman outw(rcv_car, nic->ioaddr + HOST_ADDRESS_REG); 36076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman rcv_event = inw(nic->ioaddr + IO_PORT); 36176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman if (rcv_event != RCV_DONE) 36276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman return (0); 36376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 36476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman /* FIXME: I'm guessing this might not work with this card, since 36576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman it looks like once a rcv_event is started it must be completed. 36676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman maybe there's another way. */ 36776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman if ( ! retrieve ) return 1; 36876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 36976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman rcv_status = inw(nic->ioaddr + IO_PORT); 37076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman rcv_next_frame = inw(nic->ioaddr + IO_PORT); 37176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman rcv_size = inw(nic->ioaddr + IO_PORT); 37276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#if 0 37376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman printf("%hX %hX %d %hhX\n", rcv_status, rcv_next_frame, rcv_size, 37476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman inb(nic->ioaddr + STATUS_REG)); 37576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#endif 37676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman if ((rcv_status & (RX_OK|RX_ERROR)) != RX_OK) { 37776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman printf("Receive error %hX\n", rcv_status); 37876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman return (0); 37976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman } 38076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman rcv_size &= 0x3FFF; 38176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman insw(nic->ioaddr + IO_PORT, nic->packet, ((rcv_size + 3) >> 1)); 38276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#if 0 38376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman{ 38476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman int i; 38576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman for (i = 0; i < 48; i++) { 38676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman printf("%hhX", nic->packet[i]); 38776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman putchar(i % 16 == 15 ? '\n' : ' '); 38876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman } 38976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman} 39076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#endif 39176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman nic->packetlen = rcv_size; 39276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman rcv_car = (rx_start + RCV_HEADER + rcv_size); 39376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman rx_start = rcv_next_frame; 39476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 39576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman hex_dump(rcv_car, nic->packetlen); 39676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman*/ 39776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 39876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman if (rcv_car == 0) 39976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman rcv_car = ((RCV_UPPER_LIMIT << 8) | 0xff); 40076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman outw(rcv_car - 1, nic->ioaddr + RCV_STOP); 40176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman return (1); 40276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman} 40376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 40476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/************************************************************************** 40576d05dc695b06c4e987bb8078f78032441e1430cGreg HartmanTRANSMIT - Transmit a frame 40676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman***************************************************************************/ 40776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstatic void eepro_transmit( 40876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct nic *nic, 40976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman const char *d, /* Destination */ 41076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman unsigned int t, /* Type */ 41176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman unsigned int s, /* size */ 41276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman const char *p) /* Packet */ 41376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman{ 41476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman unsigned int status, tx_available, last, end, length; 41576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman unsigned short type; 41676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman int boguscount = 20; 41776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 41876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman length = s + ETH_HLEN; 41976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman if (tx_end > tx_start) 42076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman tx_available = XMT_RAM - (tx_end - tx_start); 42176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman else if (tx_end < tx_start) 42276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman tx_available = tx_start - tx_end; 42376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman else 42476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman tx_available = XMT_RAM; 42576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman last = tx_end; 42676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman end = last + (((length + 3) >> 1) << 1) + XMT_HEADER; 42776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman if (end >= (XMT_UPPER_LIMIT << 8)) { 42876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman last = (XMT_LOWER_LIMIT << 8); 42976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman end = last + (((length + 3) >> 1) << 1) + XMT_HEADER; 43076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman } 43176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman outw(last, nic->ioaddr + HOST_ADDRESS_REG); 43276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman outw(XMT_CMD, nic->ioaddr + IO_PORT); 43376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman outw(0, nic->ioaddr + IO_PORT); 43476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman outw(end, nic->ioaddr + IO_PORT); 43576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman outw(length, nic->ioaddr + IO_PORT); 43676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman outsw(nic->ioaddr + IO_PORT, d, ETH_ALEN / 2); 43776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman outsw(nic->ioaddr + IO_PORT, nic->node_addr, ETH_ALEN / 2); 43876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman type = htons(t); 43976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman outsw(nic->ioaddr + IO_PORT, &type, sizeof(type) / 2); 44076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman outsw(nic->ioaddr + IO_PORT, p, (s + 3) >> 1); 44176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman /* A dummy read to flush the DRAM write pipeline */ 44276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman status = inw(nic->ioaddr + IO_PORT); 44376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman outw(last, nic->ioaddr + xmt_bar); 44476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman outb(XMT_CMD, nic->ioaddr); 44576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman tx_start = last; 44676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman tx_last = last; 44776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman tx_end = end; 44876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#if 0 44976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman printf("%d %d\n", tx_start, tx_end); 45076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#endif 45176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman while (boguscount > 0) { 45276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman if (((status = inw(nic->ioaddr + IO_PORT)) & TX_DONE_BIT) == 0) { 45376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman udelay(40); 45476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman boguscount--; 45576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman continue; 45676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman } 45776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman if ((status & 0x2000) == 0) { 45876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman DBG("Transmit status %hX\n", status); 45976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman } 46076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman } 46176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman} 46276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 46376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/************************************************************************** 46476d05dc695b06c4e987bb8078f78032441e1430cGreg HartmanDISABLE - Turn off ethernet interface 46576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman***************************************************************************/ 46676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstatic void eepro_disable ( struct nic *nic, struct isa_device *isa __unused ) { 46776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman eepro_sw2bank0(nic->ioaddr); /* Switch to bank 0 */ 46876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman /* Flush the Tx and disable Rx */ 46976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman outb(STOP_RCV_CMD, nic->ioaddr); 47076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman tx_start = tx_end = (XMT_LOWER_LIMIT << 8); 47176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman tx_last = 0; 47276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman /* Reset the 82595 */ 47376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman eepro_full_reset(nic->ioaddr); 47476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman} 47576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 47676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/************************************************************************** 47776d05dc695b06c4e987bb8078f78032441e1430cGreg HartmanDISABLE - Enable, Disable, or Force interrupts 47876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman***************************************************************************/ 47976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstatic void eepro_irq(struct nic *nic __unused, irq_action_t action __unused) 48076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman{ 48176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman switch ( action ) { 48276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman case DISABLE : 48376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman break; 48476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman case ENABLE : 48576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman break; 48676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman case FORCE : 48776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman break; 48876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman } 48976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman} 49076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 49176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstatic int read_eeprom(uint16_t ioaddr, int location) 49276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman{ 49376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman int i; 49476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman unsigned short retval = 0; 49576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman int ee_addr = ioaddr + eeprom_reg; 49676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman int read_cmd = location | EE_READ_CMD; 49776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman int ctrl_val = EECS; 49876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 49976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman if (eepro == LAN595FX_10ISA) { 50076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman eepro_sw2bank1(ioaddr); 50176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman outb(0x00, ioaddr + STATUS_REG); 50276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman } 50376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman eepro_sw2bank2(ioaddr); 50476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman outb(ctrl_val, ee_addr); 50576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman /* shift the read command bits out */ 50676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman for (i = 8; i >= 0; i--) { 50776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman short outval = (read_cmd & (1 << i)) ? ctrl_val | EEDI : ctrl_val; 50876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman outb(outval, ee_addr); 50976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman outb(outval | EESK, ee_addr); /* EEPROM clock tick */ 51076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman eeprom_delay(); 51176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman outb(outval, ee_addr); /* finish EEPROM clock tick */ 51276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman eeprom_delay(); 51376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman } 51476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman outb(ctrl_val, ee_addr); 51576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman for (i = 16; i > 0; i--) { 51676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman outb(ctrl_val | EESK, ee_addr); 51776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman eeprom_delay(); 51876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman retval = (retval << 1) | ((inb(ee_addr) & EEDO) ? 1 : 0); 51976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman outb(ctrl_val, ee_addr); 52076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman eeprom_delay(); 52176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman } 52276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman /* terminate the EEPROM access */ 52376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman ctrl_val &= ~EECS; 52476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman outb(ctrl_val | EESK, ee_addr); 52576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman eeprom_delay(); 52676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman outb(ctrl_val, ee_addr); 52776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman eeprom_delay(); 52876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman eepro_sw2bank0(ioaddr); 52976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman return (retval); 53076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman} 53176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 53276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstatic int eepro_probe1 ( isa_probe_addr_t ioaddr ) { 53376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman int id, counter; 53476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 53576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman id = inb(ioaddr + ID_REG); 53676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman if ((id & ID_REG_MASK) != ID_REG_SIG) 53776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman return (0); 53876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman counter = id & R_ROBIN_BITS; 53976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman if (((id = inb(ioaddr + ID_REG)) & R_ROBIN_BITS) != (counter + 0x40)) 54076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman return (0); 54176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman /* yes the 82595 has been found */ 54276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman return (1); 54376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman} 54476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 54576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstatic struct nic_operations eepro_operations = { 54676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman .connect = dummy_connect, 54776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman .poll = eepro_poll, 54876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman .transmit = eepro_transmit, 54976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman .irq = eepro_irq, 55076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 55176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 55276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 55376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/************************************************************************** 55476d05dc695b06c4e987bb8078f78032441e1430cGreg HartmanPROBE - Look for an adapter, this routine's visible to the outside 55576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman***************************************************************************/ 55676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstatic int eepro_probe ( struct nic *nic, struct isa_device *isa ) { 55776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 55876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman int i, l_eepro = 0; 55976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman union { 56076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman unsigned char caddr[ETH_ALEN]; 56176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman unsigned short saddr[ETH_ALEN/2]; 56276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman } station_addr; 56376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman const char *name; 56476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 56576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman nic->irqno = 0; 56676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman nic->ioaddr = isa->ioaddr; 56776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 56876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman station_addr.saddr[2] = read_eeprom(nic->ioaddr,2); 56976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman if ( ( station_addr.saddr[2] == 0x0000 ) || 57076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman ( station_addr.saddr[2] == 0xFFFF ) ) { 57176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman l_eepro = 3; 57276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman eepro = LAN595FX_10ISA; 57376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman eeprom_reg= EEPROM_REG_10; 57476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman rcv_start = RCV_START_10; 57576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman xmt_lower_limit_reg = XMT_LOWER_LIMIT_REG_10; 57676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman xmt_upper_limit_reg = XMT_UPPER_LIMIT_REG_10; 57776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman station_addr.saddr[2] = read_eeprom(nic->ioaddr,2); 57876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman } 57976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman station_addr.saddr[1] = read_eeprom(nic->ioaddr,3); 58076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman station_addr.saddr[0] = read_eeprom(nic->ioaddr,4); 58176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman if (l_eepro) 58276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman name = "Intel EtherExpress 10 ISA"; 58376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman else if (read_eeprom(nic->ioaddr,7) == ee_FX_INT2IRQ) { 58476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman name = "Intel EtherExpress Pro/10+ ISA"; 58576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman l_eepro = 2; 58676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman } else if (station_addr.saddr[0] == SA_ADDR1) { 58776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman name = "Intel EtherExpress Pro/10 ISA"; 58876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman l_eepro = 1; 58976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman } else { 59076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman l_eepro = 0; 59176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman name = "Intel 82595-based LAN card"; 59276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman } 59376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman station_addr.saddr[0] = swap16(station_addr.saddr[0]); 59476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman station_addr.saddr[1] = swap16(station_addr.saddr[1]); 59576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman station_addr.saddr[2] = swap16(station_addr.saddr[2]); 59676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman for (i = 0; i < ETH_ALEN; i++) { 59776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman nic->node_addr[i] = station_addr.caddr[i]; 59876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman } 59976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 60076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman DBG ( "%s ioaddr %#hX, addr %s", name, nic->ioaddr, eth_ntoa ( nic->node_addr ) ); 60176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 60276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman mem_start = RCV_LOWER_LIMIT << 8; 60376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman if ((mem_end & 0x3F) < 3 || (mem_end & 0x3F) > 29) 60476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman mem_end = RCV_UPPER_LIMIT << 8; 60576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman else { 60676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman mem_end = mem_end * 1024 + (RCV_LOWER_LIMIT << 8); 60776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman rcv_ram = mem_end - (RCV_LOWER_LIMIT << 8); 60876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman } 60976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman printf(", Rx mem %dK, if %s\n", (mem_end - mem_start) >> 10, 61076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman GetBit(read_eeprom(nic->ioaddr,5), ee_BNC_TPE) ? "BNC" : "TP"); 61176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 61276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman eepro_reset(nic); 61376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 61476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman /* point to NIC specific routines */ 61576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman nic->nic_op = &eepro_operations; 61676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman return 1; 61776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman} 61876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 61976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstatic isa_probe_addr_t eepro_probe_addrs[] = { 62076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x300, 0x210, 0x240, 0x280, 0x2C0, 0x200, 0x320, 0x340, 0x360, 62176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 62276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 62376d05dc695b06c4e987bb8078f78032441e1430cGreg HartmanISA_DRIVER ( eepro_driver, eepro_probe_addrs, eepro_probe1, 62476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman GENERIC_ISAPNP_VENDOR, 0x828a ); 62576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 62676d05dc695b06c4e987bb8078f78032441e1430cGreg HartmanDRIVER ( "eepro", nic_driver, isa_driver, eepro_driver, 62776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman eepro_probe, eepro_disable ); 62876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 62976d05dc695b06c4e987bb8078f78032441e1430cGreg HartmanISA_ROM ( "eepro", "Intel Etherexpress Pro/10" ); 63076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 63176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 63276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Local variables: 63376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * c-basic-offset: 8 63476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * c-indent-level: 8 63576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * tab-width: 8 63676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * End: 63776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 638