176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#ifndef _GPXE_PCI_H 276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define _GPXE_PCI_H 376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Support for NE2000 PCI clones added David Monro June 1997 676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Generalised for other PCI NICs by Ken Yap July 1997 776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * PCI support rewritten by Michael Brown 2006 876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Most of this is taken from /usr/src/linux/include/linux/pci.h. 1076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 1176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 1276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 1376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * This program is free software; you can redistribute it and/or 1476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * modify it under the terms of the GNU General Public License as 1576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * published by the Free Software Foundation; either version 2, or (at 1676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * your option) any later version. 1776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 1876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 1976d05dc695b06c4e987bb8078f78032441e1430cGreg HartmanFILE_LICENCE ( GPL2_ONLY ); 2076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 2176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#include <stdint.h> 2276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#include <gpxe/device.h> 2376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#include <gpxe/tables.h> 2476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#include <gpxe/pci_io.h> 2576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#include "pci_ids.h" 2676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 2776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 2876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * PCI constants 2976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 3076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 3176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 3276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ 3376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_COMMAND_MEM 0x2 /* Enable response in mem space */ 3476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */ 3576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 3676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ 3776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_LATENCY_TIMER 0x0d /* 8 bits */ 3876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 3976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */ 4076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */ 4176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */ 4276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */ 4376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */ 4476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_COMMAND_SERR 0x100 /* Enable SERR */ 4576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */ 4676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */ 4776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 4876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 4976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_VENDOR_ID 0x00 /* 16 bits */ 5076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_DEVICE_ID 0x02 /* 16 bits */ 5176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_COMMAND 0x04 /* 16 bits */ 5276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 5376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_STATUS 0x06 /* 16 bits */ 5476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */ 5576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */ 5676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */ 5776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */ 5876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_STATUS_PARITY 0x100 /* Detected parity error */ 5976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */ 6076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_STATUS_DEVSEL_FAST 0x000 6176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_STATUS_DEVSEL_MEDIUM 0x200 6276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_STATUS_DEVSEL_SLOW 0x400 6376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */ 6476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */ 6576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */ 6676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */ 6776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */ 6876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 6976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_REVISION 0x08 /* 8 bits */ 7076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_REVISION_ID 0x08 /* 8 bits */ 7176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_CLASS_REVISION 0x08 /* 32 bits */ 7276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_CLASS_CODE 0x0b /* 8 bits */ 7376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_SUBCLASS_CODE 0x0a /* 8 bits */ 7476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_HEADER_TYPE 0x0e /* 8 bits */ 7576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_HEADER_TYPE_NORMAL 0 7676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_HEADER_TYPE_BRIDGE 1 7776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_HEADER_TYPE_CARDBUS 2 7876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 7976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 8076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Header type 0 (normal devices) */ 8176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_CARDBUS_CIS 0x28 8276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_SUBSYSTEM_VENDOR_ID 0x2c 8376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_SUBSYSTEM_ID 0x2e 8476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 8576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */ 8676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_BASE_ADDRESS_1 0x14 /* 32 bits */ 8776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_BASE_ADDRESS_2 0x18 /* 32 bits */ 8876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */ 8976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */ 9076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */ 9176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 9276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */ 9376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_BASE_ADDRESS_SPACE_IO 0x01 9476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00 9576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 9676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06 9776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */ 9876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */ 9976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */ 10076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_BASE_ADDRESS_MEM_MASK (~0x0f) 10176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_BASE_ADDRESS_IO_MASK (~0x03) 10276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_ROM_ADDRESS 0x30 /* 32 bits */ 10376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_ROM_ADDRESS_ENABLE 0x01 /* Write 1 to enable ROM, 10476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman bits 31..11 are address, 10576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 10..2 are reserved */ 10676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 10776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */ 10876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 10976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_INTERRUPT_LINE 0x3c /* IRQ number (0-15) */ 11076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_INTERRUPT_PIN 0x3d /* IRQ pin on PCI bus (A-D) */ 11176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 11276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Header type 1 (PCI-to-PCI bridges) */ 11376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_PRIMARY_BUS 0x18 /* Primary bus number */ 11476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */ 11576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */ 11676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */ 11776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_IO_BASE 0x1c /* I/O range behind the bridge */ 11876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_IO_LIMIT 0x1d 11976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */ 12076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_IO_RANGE_TYPE_16 0x00 12176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_IO_RANGE_TYPE_32 0x01 12276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_IO_RANGE_MASK ~0x0f 12376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */ 12476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_MEMORY_BASE 0x20 /* Memory range behind */ 12576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_MEMORY_LIMIT 0x22 12676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_MEMORY_RANGE_TYPE_MASK 0x0f 12776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_MEMORY_RANGE_MASK ~0x0f 12876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */ 12976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_PREF_MEMORY_LIMIT 0x26 13076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_PREF_RANGE_TYPE_MASK 0x0f 13176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_PREF_RANGE_TYPE_32 0x00 13276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_PREF_RANGE_TYPE_64 0x01 13376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_PREF_RANGE_MASK ~0x0f 13476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */ 13576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_PREF_LIMIT_UPPER32 0x2c 13676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */ 13776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_IO_LIMIT_UPPER16 0x32 13876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 0x34 same as for htype 0 */ 13976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 0x35-0x3b is reserved */ 14076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */ 14176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 0x3c-0x3d are same as for htype 0 */ 14276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_BRIDGE_CONTROL 0x3e 14376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */ 14476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */ 14576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */ 14676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */ 14776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */ 14876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */ 14976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */ 15076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 15176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_CB_CAPABILITY_LIST 0x14 15276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 15376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Capability lists */ 15476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 15576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_CAP_LIST_ID 0 /* Capability ID */ 15676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_CAP_ID_PM 0x01 /* Power Management */ 15776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */ 15876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */ 15976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */ 16076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */ 16176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */ 16276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_CAP_ID_EXP 0x10 /* PCI Express */ 16376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ 16476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */ 16576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_CAP_SIZEOF 4 16676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 16776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Power Management Registers */ 16876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 16976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_PM_PMC 2 /* PM Capabilities Register */ 17076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_PM_CAP_VER_MASK 0x0007 /* Version */ 17176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */ 17276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_PM_CAP_RESERVED 0x0010 /* Reserved field */ 17376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */ 17476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_PM_CAP_AUX_POWER 0x01C0 /* Auxilliary power support mask */ 17576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_PM_CAP_D1 0x0200 /* D1 power state support */ 17676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_PM_CAP_D2 0x0400 /* D2 power state support */ 17776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_PM_CAP_PME 0x0800 /* PME pin supported */ 17876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_PM_CAP_PME_MASK 0xF800 /* PME Mask of all supported states */ 17976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_PM_CAP_PME_D0 0x0800 /* PME# from D0 */ 18076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_PM_CAP_PME_D1 0x1000 /* PME# from D1 */ 18176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_PM_CAP_PME_D2 0x2000 /* PME# from D2 */ 18276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_PM_CAP_PME_D3 0x4000 /* PME# from D3 (hot) */ 18376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_PM_CAP_PME_D3cold 0x8000 /* PME# from D3 (cold) */ 18476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_PM_CTRL 4 /* PM control and status register */ 18576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */ 18676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */ 18776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */ 18876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */ 18976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */ 19076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */ 19176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */ 19276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */ 19376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_PM_DATA_REGISTER 7 /* (??) */ 19476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_PM_SIZEOF 8 19576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 19676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* AGP registers */ 19776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 19876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_AGP_VERSION 2 /* BCD version number */ 19976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_AGP_RFU 3 /* Rest of capability flags */ 20076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_AGP_STATUS 4 /* Status register */ 20176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */ 20276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */ 20376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */ 20476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */ 20576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */ 20676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */ 20776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */ 20876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_AGP_COMMAND 8 /* Control register */ 20976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */ 21076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */ 21176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */ 21276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */ 21376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */ 21476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */ 21576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 2x rate */ 21676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 1x rate */ 21776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_AGP_SIZEOF 12 21876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 21976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Slot Identification */ 22076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 22176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_SID_ESR 2 /* Expansion Slot Register */ 22276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */ 22376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */ 22476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_SID_CHASSIS_NR 3 /* Chassis Number */ 22576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 22676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Message Signalled Interrupts registers */ 22776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 22876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_MSI_FLAGS 2 /* Various flags */ 22976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */ 23076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */ 23176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */ 23276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */ 23376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_MSI_RFU 3 /* Rest of capability flags */ 23476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */ 23576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */ 23676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */ 23776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */ 23876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 23976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Advanced Error Reporting */ 24076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 24176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */ 24276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_ERR_UNC_TRAIN 0x00000001 /* Training */ 24376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_ERR_UNC_DLP 0x00000010 /* Data Link Protocol */ 24476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_ERR_UNC_POISON_TLP 0x00001000 /* Poisoned TLP */ 24576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_ERR_UNC_FCP 0x00002000 /* Flow Control Protocol */ 24676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_ERR_UNC_COMP_TIME 0x00004000 /* Completion Timeout */ 24776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_ERR_UNC_COMP_ABORT 0x00008000 /* Completer Abort */ 24876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_ERR_UNC_UNX_COMP 0x00010000 /* Unexpected Completion */ 24976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_ERR_UNC_RX_OVER 0x00020000 /* Receiver Overflow */ 25076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_ERR_UNC_MALF_TLP 0x00040000 /* Malformed TLP */ 25176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_ERR_UNC_ECRC 0x00080000 /* ECRC Error Status */ 25276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_ERR_UNC_UNSUP 0x00100000 /* Unsupported Request */ 25376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_ERR_UNCOR_MASK 8 /* Uncorrectable Error Mask */ 25476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman /* Same bits as above */ 25576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_ERR_UNCOR_SEVER 12 /* Uncorrectable Error Severity */ 25676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman /* Same bits as above */ 25776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_ERR_COR_STATUS 16 /* Correctable Error Status */ 25876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_ERR_COR_RCVR 0x00000001 /* Receiver Error Status */ 25976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_ERR_COR_BAD_TLP 0x00000040 /* Bad TLP Status */ 26076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_ERR_COR_BAD_DLLP 0x00000080 /* Bad DLLP Status */ 26176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_ERR_COR_REP_ROLL 0x00000100 /* REPLAY_NUM Rollover */ 26276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_ERR_COR_REP_TIMER 0x00001000 /* Replay Timer Timeout */ 26376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_ERR_COR_MASK 20 /* Correctable Error Mask */ 26476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman /* Same bits as above */ 26576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 26676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/** A PCI device ID list entry */ 26776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct pci_device_id { 26876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman /** Name */ 26976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman const char *name; 27076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman /** PCI vendor ID */ 27176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman uint16_t vendor; 27276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman /** PCI device ID */ 27376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman uint16_t device; 27476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman /** Arbitrary driver data */ 27576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman unsigned long driver_data; 27676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 27776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 27876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/** Match-anything ID */ 27976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_ANY_ID 0xffff 28076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 28176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/** A PCI device */ 28276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct pci_device { 28376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman /** Generic device */ 28476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct device dev; 28576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman /** Memory base 28676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 28776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * This is the physical address of the first valid memory BAR. 28876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 28976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman unsigned long membase; 29076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman /** 29176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * I/O address 29276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 29376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * This is the physical address of the first valid I/O BAR. 29476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 29576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman unsigned long ioaddr; 29676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman /** Vendor ID */ 29776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman uint16_t vendor; 29876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman /** Device ID */ 29976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman uint16_t device; 30076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman /** Device class */ 30176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman uint32_t class; 30276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman /** Interrupt number */ 30376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman uint8_t irq; 30476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman /** Bus number */ 30576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman uint8_t bus; 30676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman /** Device and function number */ 30776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman uint8_t devfn; 30876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman /** Driver for this device */ 30976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct pci_driver *driver; 31076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman /** Driver-private data 31176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 31276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Use pci_set_drvdata() and pci_get_drvdata() to access this 31376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * field. 31476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 31576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman void *priv; 31676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman /** Driver name */ 31776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman const char *driver_name; 31876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 31976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 32076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/** A PCI driver */ 32176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct pci_driver { 32276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman /** PCI ID table */ 32376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct pci_device_id *ids; 32476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman /** Number of entries in PCI ID table */ 32576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman unsigned int id_count; 32676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman /** 32776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Probe device 32876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 32976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * @v pci PCI device 33076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * @v id Matching entry in ID table 33176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * @ret rc Return status code 33276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 33376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman int ( * probe ) ( struct pci_device *pci, 33476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman const struct pci_device_id *id ); 33576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman /** 33676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Remove device 33776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 33876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * @v pci PCI device 33976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 34076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman void ( * remove ) ( struct pci_device *pci ); 34176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 34276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 34376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/** PCI driver table */ 34476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_DRIVERS __table ( struct pci_driver, "pci_drivers" ) 34576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 34676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/** Declare a PCI driver */ 34776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define __pci_driver __table_entry ( PCI_DRIVERS, 01 ) 34876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 34976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_DEVFN( slot, func ) ( ( (slot) << 3 ) | (func) ) 35076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_SLOT( devfn ) ( ( (devfn) >> 3 ) & 0x1f ) 35176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_FUNC( devfn ) ( (devfn) & 0x07 ) 35276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_BUS( busdevfn ) ( (busdevfn) >> 8 ) 35376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_BUSDEVFN( bus, devfn ) ( ( (bus) << 8 ) | (devfn) ) 35476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 35576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_BASE_CLASS( class ) ( (class) >> 16 ) 35676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_SUB_CLASS( class ) ( ( (class) >> 8 ) & 0xff ) 35776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_PROG_INTF( class ) ( (class) & 0xff ) 35876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 35976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 36076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * PCI_ROM is used to build up entries in a struct pci_id array. It 36176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * is also parsed by parserom.pl to generate Makefile rules and files 36276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * for rom-o-matic. 36376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 36476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * PCI_ID can be used to generate entries without creating a 36576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * corresponding ROM in the build process. 36676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 36776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_ID( _vendor, _device, _name, _description, _data ) { \ 36876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman .vendor = _vendor, \ 36976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman .device = _device, \ 37076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman .name = _name, \ 37176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman .driver_data = _data \ 37276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman} 37376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PCI_ROM( _vendor, _device, _name, _description, _data ) \ 37476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PCI_ID( _vendor, _device, _name, _description, _data ) 37576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 37676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanextern void adjust_pci_device ( struct pci_device *pci ); 37776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanextern unsigned long pci_bar_start ( struct pci_device *pci, 37876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman unsigned int reg ); 37976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanextern int pci_find_capability ( struct pci_device *pci, int capability ); 38076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanextern unsigned long pci_bar_size ( struct pci_device *pci, unsigned int reg ); 38176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 38276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/** 38376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Set PCI driver-private data 38476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 38576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * @v pci PCI device 38676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * @v priv Private data 38776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 38876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstatic inline void pci_set_drvdata ( struct pci_device *pci, void *priv ) { 38976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pci->priv = priv; 39076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman} 39176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 39276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/** 39376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Get PCI driver-private data 39476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 39576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * @v pci PCI device 39676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * @ret priv Private data 39776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 39876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstatic inline void * pci_get_drvdata ( struct pci_device *pci ) { 39976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman return pci->priv; 40076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman} 40176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 40276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#endif /* _GPXE_PCI_H */ 403