cpu-mips.cc revision b8a8cc1952d61a2f3a2568848933943a543b5d3e 
1// Copyright 2012 the V8 project authors. All rights reserved.
2// Use of this source code is governed by a BSD-style license that can be
3// found in the LICENSE file.
4
5// CPU specific code for arm independent of OS goes here.
6
7#include <sys/syscall.h>
8#include <unistd.h>
9
10#ifdef __mips
11#include <asm/cachectl.h>
12#endif  // #ifdef __mips
13
14#include "src/v8.h"
15
16#if V8_TARGET_ARCH_MIPS
17
18#include "src/assembler.h"
19#include "src/macro-assembler.h"
20
21#include "src/simulator.h"  // For cache flushing.
22
23namespace v8 {
24namespace internal {
25
26
27void CpuFeatures::FlushICache(void* start, size_t size) {
28  // Nothing to do, flushing no instructions.
29  if (size == 0) {
30    return;
31  }
32
33#if !defined (USE_SIMULATOR)
34#if defined(ANDROID)
35  // Bionic cacheflush can typically run in userland, avoiding kernel call.
36  char *end = reinterpret_cast<char *>(start) + size;
37  cacheflush(
38    reinterpret_cast<intptr_t>(start), reinterpret_cast<intptr_t>(end), 0);
39#else  // ANDROID
40  int res;
41  // See http://www.linux-mips.org/wiki/Cacheflush_Syscall.
42  res = syscall(__NR_cacheflush, start, size, ICACHE);
43  if (res) {
44    V8_Fatal(__FILE__, __LINE__, "Failed to flush the instruction cache");
45  }
46#endif  // ANDROID
47#else  // USE_SIMULATOR.
48  // Not generating mips instructions for C-code. This means that we are
49  // building a mips emulator based target.  We should notify the simulator
50  // that the Icache was flushed.
51  // None of this code ends up in the snapshot so there are no issues
52  // around whether or not to generate the code when building snapshots.
53  Simulator::FlushICache(Isolate::Current()->simulator_i_cache(), start, size);
54#endif  // USE_SIMULATOR.
55}
56
57} }  // namespace v8::internal
58
59#endif  // V8_TARGET_ARCH_MIPS
60