13b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Copyright (c) 1994-2006 Sun Microsystems Inc. 23b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// All Rights Reserved. 33b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// 43b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Redistribution and use in source and binary forms, with or without 53b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// modification, are permitted provided that the following conditions 63b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// are met: 73b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// 83b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// - Redistributions of source code must retain the above copyright notice, 93b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// this list of conditions and the following disclaimer. 103b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// 113b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// - Redistribution in binary form must reproduce the above copyright 123b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// notice, this list of conditions and the following disclaimer in the 133b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// documentation and/or other materials provided with the 143b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// distribution. 153b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// 163b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// - Neither the name of Sun Microsystems or the names of contributors may 173b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// be used to endorse or promote products derived from this software without 183b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// specific prior written permission. 193b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// 203b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 213b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 223b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 233b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 243b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 253b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 263b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 273b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 283b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 293b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 303b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 313b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// OF THE POSSIBILITY OF SUCH DAMAGE. 323b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 333b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// The original source code covered by the above license above has been 343b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// modified significantly by Google Inc. 353b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Copyright 2014 the V8 project authors. All rights reserved. 363b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 373b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch#include "src/s390/assembler-s390.h" 383b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 393b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch#if V8_TARGET_ARCH_S390 403b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 413b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch#if V8_HOST_ARCH_S390 423b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch#include <elf.h> // Required for auxv checks for STFLE support 433b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch#endif 443b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 453b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch#include "src/base/bits.h" 463b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch#include "src/base/cpu.h" 473b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch#include "src/s390/assembler-s390-inl.h" 483b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 493b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch#include "src/macro-assembler.h" 503b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 513b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochnamespace v8 { 523b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochnamespace internal { 533b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 543b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Get the CPU features enabled by the build. 553b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochstatic unsigned CpuFeaturesImpliedByCompiler() { 563b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch unsigned answer = 0; 573b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch return answer; 583b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 593b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 603b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Check whether Store Facility STFLE instruction is available on the platform. 613b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Instruction returns a bit vector of the enabled hardware facilities. 623b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochstatic bool supportsSTFLE() { 633b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch#if V8_HOST_ARCH_S390 643b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch static bool read_tried = false; 653b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch static uint32_t auxv_hwcap = 0; 663b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 673b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch if (!read_tried) { 683b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch // Open the AUXV (auxilliary vector) psuedo-file 693b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch int fd = open("/proc/self/auxv", O_RDONLY); 703b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 713b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch read_tried = true; 723b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch if (fd != -1) { 733b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch#if V8_TARGET_ARCH_S390X 743b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch static Elf64_auxv_t buffer[16]; 753b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch Elf64_auxv_t* auxv_element; 763b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch#else 773b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch static Elf32_auxv_t buffer[16]; 783b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch Elf32_auxv_t* auxv_element; 793b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch#endif 803b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch int bytes_read = 0; 813b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch while (bytes_read >= 0) { 823b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch // Read a chunk of the AUXV 833b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch bytes_read = read(fd, buffer, sizeof(buffer)); 843b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch // Locate and read the platform field of AUXV if it is in the chunk 853b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch for (auxv_element = buffer; 863b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch auxv_element + sizeof(auxv_element) <= buffer + bytes_read && 873b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch auxv_element->a_type != AT_NULL; 883b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch auxv_element++) { 893b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch // We are looking for HWCAP entry in AUXV to search for STFLE support 903b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch if (auxv_element->a_type == AT_HWCAP) { 913b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch /* Note: Both auxv_hwcap and buffer are static */ 923b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch auxv_hwcap = auxv_element->a_un.a_val; 933b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch goto done_reading; 943b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } 953b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } 963b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } 973b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch done_reading: 983b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch close(fd); 993b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } 1003b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } 1013b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 1023b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch // Did not find result 1033b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch if (0 == auxv_hwcap) { 1043b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch return false; 1053b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } 1063b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 1073b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch // HWCAP_S390_STFLE is defined to be 4 in include/asm/elf.h. Currently 1083b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch // hardcoded in case that include file does not exist. 1093b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch const uint32_t HWCAP_S390_STFLE = 4; 1103b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch return (auxv_hwcap & HWCAP_S390_STFLE); 1113b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch#else 1123b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch // STFLE is not available on non-s390 hosts 1133b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch return false; 1143b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch#endif 1153b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 1163b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 1173b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid CpuFeatures::ProbeImpl(bool cross_compile) { 1183b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch supported_ |= CpuFeaturesImpliedByCompiler(); 1193b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch icache_line_size_ = 256; 1203b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 1213b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch // Only use statically determined features for cross compile (snapshot). 1223b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch if (cross_compile) return; 1233b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 1243b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch#ifdef DEBUG 1253b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch initialized_ = true; 1263b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch#endif 1273b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 1283b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch static bool performSTFLE = supportsSTFLE(); 1293b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 1303b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Need to define host, as we are generating inlined S390 assembly to test 1313b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// for facilities. 1323b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch#if V8_HOST_ARCH_S390 1333b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch if (performSTFLE) { 1343b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch // STFLE D(B) requires: 1353b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch // GPR0 to specify # of double words to update minus 1. 1363b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch // i.e. GPR0 = 0 for 1 doubleword 1373b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch // D(B) to specify to memory location to store the facilities bits 1383b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch // The facilities we are checking for are: 1393b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch // Bit 45 - Distinct Operands for instructions like ARK, SRK, etc. 1403b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch // As such, we require only 1 double word 14162ed631aa0ff23db68a47fd423efa9c019ff2c9eBen Murdoch int64_t facilities[3] = {0L}; 1423b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch // LHI sets up GPR0 1433b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch // STFLE is specified as .insn, as opcode is not recognized. 1443b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch // We register the instructions kill r0 (LHI) and the CC (STFLE). 1453b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch asm volatile( 14662ed631aa0ff23db68a47fd423efa9c019ff2c9eBen Murdoch "lhi 0,2\n" 1473b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch ".insn s,0xb2b00000,%0\n" 1483b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch : "=Q"(facilities) 1493b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch : 1503b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch : "cc", "r0"); 1513b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 15262ed631aa0ff23db68a47fd423efa9c019ff2c9eBen Murdoch uint64_t one = static_cast<uint64_t>(1); 1533b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch // Test for Distinct Operands Facility - Bit 45 15462ed631aa0ff23db68a47fd423efa9c019ff2c9eBen Murdoch if (facilities[0] & (one << (63 - 45))) { 1553b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch supported_ |= (1u << DISTINCT_OPS); 1563b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } 1573b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch // Test for General Instruction Extension Facility - Bit 34 15862ed631aa0ff23db68a47fd423efa9c019ff2c9eBen Murdoch if (facilities[0] & (one << (63 - 34))) { 1593b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch supported_ |= (1u << GENERAL_INSTR_EXT); 1603b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } 1613b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch // Test for Floating Point Extension Facility - Bit 37 16262ed631aa0ff23db68a47fd423efa9c019ff2c9eBen Murdoch if (facilities[0] & (one << (63 - 37))) { 1633b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch supported_ |= (1u << FLOATING_POINT_EXT); 1643b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } 16562ed631aa0ff23db68a47fd423efa9c019ff2c9eBen Murdoch // Test for Vector Facility - Bit 129 16662ed631aa0ff23db68a47fd423efa9c019ff2c9eBen Murdoch if (facilities[2] & (one << (63 - (129 - 128)))) { 16762ed631aa0ff23db68a47fd423efa9c019ff2c9eBen Murdoch supported_ |= (1u << VECTOR_FACILITY); 16862ed631aa0ff23db68a47fd423efa9c019ff2c9eBen Murdoch } 16962ed631aa0ff23db68a47fd423efa9c019ff2c9eBen Murdoch // Test for Miscellaneous Instruction Extension Facility - Bit 58 17062ed631aa0ff23db68a47fd423efa9c019ff2c9eBen Murdoch if (facilities[0] & (1lu << (63 - 58))) { 17162ed631aa0ff23db68a47fd423efa9c019ff2c9eBen Murdoch supported_ |= (1u << MISC_INSTR_EXT2); 17262ed631aa0ff23db68a47fd423efa9c019ff2c9eBen Murdoch } 1733b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } 1743b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch#else 1753b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch // All distinct ops instructions can be simulated 1763b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch supported_ |= (1u << DISTINCT_OPS); 1773b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch // RISBG can be simulated 1783b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch supported_ |= (1u << GENERAL_INSTR_EXT); 1793b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch supported_ |= (1u << FLOATING_POINT_EXT); 18062ed631aa0ff23db68a47fd423efa9c019ff2c9eBen Murdoch supported_ |= (1u << MISC_INSTR_EXT2); 1813b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch USE(performSTFLE); // To avoid assert 18262ed631aa0ff23db68a47fd423efa9c019ff2c9eBen Murdoch supported_ |= (1u << VECTOR_FACILITY); 1833b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch#endif 1843b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch supported_ |= (1u << FPU); 1853b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 1863b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 1873b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid CpuFeatures::PrintTarget() { 1883b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch const char* s390_arch = NULL; 1893b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 1903b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch#if V8_TARGET_ARCH_S390X 1913b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch s390_arch = "s390x"; 1923b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch#else 1933b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch s390_arch = "s390"; 1943b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch#endif 1953b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 1963b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch printf("target %s\n", s390_arch); 1973b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 1983b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 1993b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid CpuFeatures::PrintFeatures() { 2003b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch printf("FPU=%d\n", CpuFeatures::IsSupported(FPU)); 2013b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch printf("FPU_EXT=%d\n", CpuFeatures::IsSupported(FLOATING_POINT_EXT)); 2023b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch printf("GENERAL_INSTR=%d\n", CpuFeatures::IsSupported(GENERAL_INSTR_EXT)); 2033b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch printf("DISTINCT_OPS=%d\n", CpuFeatures::IsSupported(DISTINCT_OPS)); 20462ed631aa0ff23db68a47fd423efa9c019ff2c9eBen Murdoch printf("VECTOR_FACILITY=%d\n", CpuFeatures::IsSupported(VECTOR_FACILITY)); 20562ed631aa0ff23db68a47fd423efa9c019ff2c9eBen Murdoch printf("MISC_INSTR_EXT2=%d\n", CpuFeatures::IsSupported(MISC_INSTR_EXT2)); 2063b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 2073b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 2083b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben MurdochRegister ToRegister(int num) { 2093b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(num >= 0 && num < kNumRegisters); 2103b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch const Register kRegisters[] = {r0, r1, r2, r3, r4, r5, r6, r7, 2113b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch r8, r9, r10, fp, ip, r13, r14, sp}; 2123b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch return kRegisters[num]; 2133b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 2143b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 2153b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// ----------------------------------------------------------------------------- 2163b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Implementation of RelocInfo 2173b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 2183b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochconst int RelocInfo::kApplyMask = 2193b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch RelocInfo::kCodeTargetMask | 1 << RelocInfo::INTERNAL_REFERENCE; 2203b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 2213b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochbool RelocInfo::IsCodedSpecially() { 2223b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch // The deserializer needs to know whether a pointer is specially 2233b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch // coded. Being specially coded on S390 means that it is an iihf/iilf 2243b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch // instruction sequence, and that is always the case inside code 2253b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch // objects. 2263b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch return true; 2273b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 2283b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 2293b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochbool RelocInfo::IsInConstantPool() { return false; } 2303b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 231bcf72ee8e3b26f1d0726869c7ddb3921c68b09a8Ben MurdochAddress RelocInfo::wasm_memory_reference() { 232bcf72ee8e3b26f1d0726869c7ddb3921c68b09a8Ben Murdoch DCHECK(IsWasmMemoryReference(rmode_)); 233bcf72ee8e3b26f1d0726869c7ddb3921c68b09a8Ben Murdoch return Assembler::target_address_at(pc_, host_); 234bcf72ee8e3b26f1d0726869c7ddb3921c68b09a8Ben Murdoch} 235bcf72ee8e3b26f1d0726869c7ddb3921c68b09a8Ben Murdoch 236bcf72ee8e3b26f1d0726869c7ddb3921c68b09a8Ben Murdochuint32_t RelocInfo::wasm_memory_size_reference() { 237bcf72ee8e3b26f1d0726869c7ddb3921c68b09a8Ben Murdoch DCHECK(IsWasmMemorySizeReference(rmode_)); 238bcf72ee8e3b26f1d0726869c7ddb3921c68b09a8Ben Murdoch return static_cast<uint32_t>( 239bcf72ee8e3b26f1d0726869c7ddb3921c68b09a8Ben Murdoch reinterpret_cast<intptr_t>(Assembler::target_address_at(pc_, host_))); 240bcf72ee8e3b26f1d0726869c7ddb3921c68b09a8Ben Murdoch} 241bcf72ee8e3b26f1d0726869c7ddb3921c68b09a8Ben Murdoch 24213e2dadd00298019ed862f2b2fc5068bba730bcfBen MurdochAddress RelocInfo::wasm_global_reference() { 24313e2dadd00298019ed862f2b2fc5068bba730bcfBen Murdoch DCHECK(IsWasmGlobalReference(rmode_)); 24413e2dadd00298019ed862f2b2fc5068bba730bcfBen Murdoch return Assembler::target_address_at(pc_, host_); 24513e2dadd00298019ed862f2b2fc5068bba730bcfBen Murdoch} 24613e2dadd00298019ed862f2b2fc5068bba730bcfBen Murdoch 24762ed631aa0ff23db68a47fd423efa9c019ff2c9eBen Murdochuint32_t RelocInfo::wasm_function_table_size_reference() { 24862ed631aa0ff23db68a47fd423efa9c019ff2c9eBen Murdoch DCHECK(IsWasmFunctionTableSizeReference(rmode_)); 24962ed631aa0ff23db68a47fd423efa9c019ff2c9eBen Murdoch return static_cast<uint32_t>( 25062ed631aa0ff23db68a47fd423efa9c019ff2c9eBen Murdoch reinterpret_cast<intptr_t>(Assembler::target_address_at(pc_, host_))); 25162ed631aa0ff23db68a47fd423efa9c019ff2c9eBen Murdoch} 25262ed631aa0ff23db68a47fd423efa9c019ff2c9eBen Murdoch 25313e2dadd00298019ed862f2b2fc5068bba730bcfBen Murdochvoid RelocInfo::unchecked_update_wasm_memory_reference( 25413e2dadd00298019ed862f2b2fc5068bba730bcfBen Murdoch Address address, ICacheFlushMode flush_mode) { 25513e2dadd00298019ed862f2b2fc5068bba730bcfBen Murdoch Assembler::set_target_address_at(isolate_, pc_, host_, address, flush_mode); 25613e2dadd00298019ed862f2b2fc5068bba730bcfBen Murdoch} 25713e2dadd00298019ed862f2b2fc5068bba730bcfBen Murdoch 25862ed631aa0ff23db68a47fd423efa9c019ff2c9eBen Murdochvoid RelocInfo::unchecked_update_wasm_size(uint32_t size, 25962ed631aa0ff23db68a47fd423efa9c019ff2c9eBen Murdoch ICacheFlushMode flush_mode) { 26013e2dadd00298019ed862f2b2fc5068bba730bcfBen Murdoch Assembler::set_target_address_at(isolate_, pc_, host_, 26113e2dadd00298019ed862f2b2fc5068bba730bcfBen Murdoch reinterpret_cast<Address>(size), flush_mode); 262bcf72ee8e3b26f1d0726869c7ddb3921c68b09a8Ben Murdoch} 263bcf72ee8e3b26f1d0726869c7ddb3921c68b09a8Ben Murdoch 2643b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// ----------------------------------------------------------------------------- 2653b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Implementation of Operand and MemOperand 2663b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// See assembler-s390-inl.h for inlined constructors 2673b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 2683b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben MurdochOperand::Operand(Handle<Object> handle) { 2693b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch AllowDeferredHandleDereference using_raw_address; 2703b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rm_ = no_reg; 2713b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch // Verify all Objects referred by code are NOT in new space. 2723b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch Object* obj = *handle; 2733b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch if (obj->IsHeapObject()) { 2743b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch imm_ = reinterpret_cast<intptr_t>(handle.location()); 2753b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rmode_ = RelocInfo::EMBEDDED_OBJECT; 2763b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } else { 2773b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch // no relocation needed 2783b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch imm_ = reinterpret_cast<intptr_t>(obj); 2793b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rmode_ = kRelocInfo_NONEPTR; 2803b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } 2813b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 2823b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 2833b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben MurdochMemOperand::MemOperand(Register rn, int32_t offset) { 2843b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch baseRegister = rn; 2853b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch indexRegister = r0; 2863b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch offset_ = offset; 2873b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 2883b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 2893b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben MurdochMemOperand::MemOperand(Register rx, Register rb, int32_t offset) { 2903b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch baseRegister = rb; 2913b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch indexRegister = rx; 2923b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch offset_ = offset; 2933b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 2943b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 2953b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// ----------------------------------------------------------------------------- 2963b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Specific instructions, constants, and masks. 2973b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 2983b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben MurdochAssembler::Assembler(Isolate* isolate, void* buffer, int buffer_size) 2993b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch : AssemblerBase(isolate, buffer, buffer_size), 3003b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch recorded_ast_id_(TypeFeedbackId::None()), 301f91f0611dbaf29ca0f1d4aecb357ce243a19d2faBen Murdoch code_targets_(100) { 3023b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch reloc_info_writer.Reposition(buffer_ + buffer_size_, pc_); 3033b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 3043b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch last_bound_pos_ = 0; 3053b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch ClearRecordedAstId(); 3063b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch relocations_.reserve(128); 3073b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 3083b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 3093b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::GetCode(CodeDesc* desc) { 3103b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch EmitRelocations(); 3113b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 3123b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch // Set up code descriptor. 3133b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch desc->buffer = buffer_; 3143b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch desc->buffer_size = buffer_size_; 3153b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch desc->instr_size = pc_offset(); 3163b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch desc->reloc_size = (buffer_ + buffer_size_) - reloc_info_writer.pos(); 3173b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch desc->origin = this; 31813e2dadd00298019ed862f2b2fc5068bba730bcfBen Murdoch desc->unwinding_info_size = 0; 31913e2dadd00298019ed862f2b2fc5068bba730bcfBen Murdoch desc->unwinding_info = nullptr; 3203b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 3213b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 3223b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::Align(int m) { 3233b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(m >= 4 && base::bits::IsPowerOfTwo32(m)); 3243b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch while ((pc_offset() & (m - 1)) != 0) { 3253b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch nop(0); 3263b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } 3273b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 3283b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 3293b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::CodeTargetAlign() { Align(8); } 3303b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 3313b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben MurdochCondition Assembler::GetCondition(Instr instr) { 3323b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch switch (instr & kCondMask) { 3333b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch case BT: 3343b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch return eq; 3353b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch case BF: 3363b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch return ne; 3373b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch default: 3383b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch UNIMPLEMENTED(); 3393b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } 3403b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch return al; 3413b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 3423b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 3433b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch#if V8_TARGET_ARCH_S390X 3443b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// This code assumes a FIXED_SEQUENCE for 64bit loads (iihf/iilf) 3453b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochbool Assembler::Is64BitLoadIntoIP(SixByteInstr instr1, SixByteInstr instr2) { 3463b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch // Check the instructions are the iihf/iilf load into ip 3473b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch return (((instr1 >> 32) == 0xC0C8) && ((instr2 >> 32) == 0xC0C9)); 3483b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 3493b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch#else 3503b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// This code assumes a FIXED_SEQUENCE for 32bit loads (iilf) 3513b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochbool Assembler::Is32BitLoadIntoIP(SixByteInstr instr) { 3523b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch // Check the instruction is an iilf load into ip/r12. 3533b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch return ((instr >> 32) == 0xC0C9); 3543b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 3553b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch#endif 3563b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 3573b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Labels refer to positions in the (to be) generated code. 3583b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// There are bound, linked, and unused labels. 3593b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// 3603b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Bound labels refer to known positions in the already 3613b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// generated code. pos() is the position the label refers to. 3623b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// 3633b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Linked labels refer to unknown positions in the code 3643b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// to be generated; pos() is the position of the last 3653b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// instruction using the label. 3663b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 3673b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// The link chain is terminated by a negative code position (must be aligned) 3683b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochconst int kEndOfChain = -4; 3693b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 3703b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Returns the target address of the relative instructions, typically 3713b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// of the form: pos + imm (where immediate is in # of halfwords for 3723b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// BR* and LARL). 3733b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochint Assembler::target_at(int pos) { 3743b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch SixByteInstr instr = instr_at(pos); 3753b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch // check which type of branch this is 16 or 26 bit offset 3763b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch Opcode opcode = Instruction::S390OpcodeValue(buffer_ + pos); 3773b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 3783b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch if (BRC == opcode || BRCT == opcode || BRCTG == opcode) { 3793b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch int16_t imm16 = SIGN_EXT_IMM16((instr & kImm16Mask)); 3803b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch imm16 <<= 1; // BRC immediate is in # of halfwords 3813b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch if (imm16 == 0) return kEndOfChain; 3823b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch return pos + imm16; 3833b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } else if (LLILF == opcode || BRCL == opcode || LARL == opcode || 3843b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch BRASL == opcode) { 3853b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch int32_t imm32 = 3863b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch static_cast<int32_t>(instr & (static_cast<uint64_t>(0xffffffff))); 3873b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch if (LLILF != opcode) 3883b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch imm32 <<= 1; // BR* + LARL treat immediate in # of halfwords 3893b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch if (imm32 == 0) return kEndOfChain; 3903b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch return pos + imm32; 3913b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } 3923b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 3933b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch // Unknown condition 3943b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(false); 3953b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch return -1; 3963b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 3973b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 3983b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Update the target address of the current relative instruction. 3993b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::target_at_put(int pos, int target_pos, bool* is_branch) { 4003b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch SixByteInstr instr = instr_at(pos); 4013b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch Opcode opcode = Instruction::S390OpcodeValue(buffer_ + pos); 4023b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 4033b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch if (is_branch != nullptr) { 4043b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch *is_branch = (opcode == BRC || opcode == BRCT || opcode == BRCTG || 4053b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch opcode == BRCL || opcode == BRASL); 4063b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } 4073b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 4083b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch if (BRC == opcode || BRCT == opcode || BRCTG == opcode) { 4093b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch int16_t imm16 = target_pos - pos; 4103b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch instr &= (~0xffff); 4113b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(is_int16(imm16)); 4123b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch instr_at_put<FourByteInstr>(pos, instr | (imm16 >> 1)); 4133b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch return; 4143b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } else if (BRCL == opcode || LARL == opcode || BRASL == opcode) { 4153b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch // Immediate is in # of halfwords 4163b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch int32_t imm32 = target_pos - pos; 4173b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch instr &= (~static_cast<uint64_t>(0xffffffff)); 4183b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch instr_at_put<SixByteInstr>(pos, instr | (imm32 >> 1)); 4193b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch return; 4203b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } else if (LLILF == opcode) { 4213b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(target_pos == kEndOfChain || target_pos >= 0); 4223b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch // Emitted label constant, not part of a branch. 4233b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch // Make label relative to Code* of generated Code object. 4243b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch int32_t imm32 = target_pos + (Code::kHeaderSize - kHeapObjectTag); 4253b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch instr &= (~static_cast<uint64_t>(0xffffffff)); 4263b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch instr_at_put<SixByteInstr>(pos, instr | imm32); 4273b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch return; 4283b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } 4293b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(false); 4303b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 4313b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 4323b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Returns the maximum number of bits given instruction can address. 4333b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochint Assembler::max_reach_from(int pos) { 4343b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch Opcode opcode = Instruction::S390OpcodeValue(buffer_ + pos); 4353b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 4363b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch // Check which type of instr. In theory, we can return 4373b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch // the values below + 1, given offset is # of halfwords 4383b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch if (BRC == opcode || BRCT == opcode || BRCTG == opcode) { 4393b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch return 16; 4403b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } else if (LLILF == opcode || BRCL == opcode || LARL == opcode || 4413b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch BRASL == opcode) { 4423b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch return 31; // Using 31 as workaround instead of 32 as 4433b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch // is_intn(x,32) doesn't work on 32-bit platforms. 4443b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch // llilf: Emitted label constant, not part of 4453b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch // a branch (regexp PushBacktrack). 4463b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } 4473b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(false); 4483b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch return 16; 4493b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 4503b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 4513b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::bind_to(Label* L, int pos) { 4523b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(0 <= pos && pos <= pc_offset()); // must have a valid binding position 4533b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch bool is_branch = false; 4543b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch while (L->is_linked()) { 4553b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch int fixup_pos = L->pos(); 4563b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch#ifdef DEBUG 4573b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch int32_t offset = pos - fixup_pos; 4583b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch int maxReach = max_reach_from(fixup_pos); 4593b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch#endif 4603b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch next(L); // call next before overwriting link with target at fixup_pos 4613b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(is_intn(offset, maxReach)); 4623b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch target_at_put(fixup_pos, pos, &is_branch); 4633b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } 4643b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch L->bind_to(pos); 4653b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 4663b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch // Keep track of the last bound label so we don't eliminate any instructions 4673b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch // before a bound label. 4683b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch if (pos > last_bound_pos_) last_bound_pos_ = pos; 4693b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 4703b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 4713b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::bind(Label* L) { 4723b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(!L->is_bound()); // label can only be bound once 4733b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch bind_to(L, pc_offset()); 4743b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 4753b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 4763b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::next(Label* L) { 4773b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(L->is_linked()); 4783b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch int link = target_at(L->pos()); 4793b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch if (link == kEndOfChain) { 4803b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch L->Unuse(); 4813b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } else { 4823b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(link >= 0); 4833b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch L->link_to(link); 4843b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } 4853b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 4863b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 4873b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochbool Assembler::is_near(Label* L, Condition cond) { 4883b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(L->is_bound()); 4893b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch if (L->is_bound() == false) return false; 4903b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 4913b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch int maxReach = ((cond == al) ? 26 : 16); 4923b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch int offset = L->pos() - pc_offset(); 4933b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 4943b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch return is_intn(offset, maxReach); 4953b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 4963b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 4973b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochint Assembler::link(Label* L) { 4983b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch int position; 4993b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch if (L->is_bound()) { 5003b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch position = L->pos(); 5013b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } else { 5023b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch if (L->is_linked()) { 5033b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch position = L->pos(); // L's link 5043b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } else { 5053b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch // was: target_pos = kEndOfChain; 5063b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch // However, using self to mark the first reference 5073b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch // should avoid most instances of branch offset overflow. See 5083b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch // target_at() for where this is converted back to kEndOfChain. 5093b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch position = pc_offset(); 5103b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } 5113b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch L->link_to(pc_offset()); 5123b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } 5133b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 5143b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch return position; 5153b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 5163b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 5173b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::load_label_offset(Register r1, Label* L) { 5183b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch int target_pos; 5193b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch int constant; 5203b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch if (L->is_bound()) { 5213b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch target_pos = L->pos(); 5223b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch constant = target_pos + (Code::kHeaderSize - kHeapObjectTag); 5233b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } else { 5243b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch if (L->is_linked()) { 5253b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch target_pos = L->pos(); // L's link 5263b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } else { 5273b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch // was: target_pos = kEndOfChain; 5283b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch // However, using branch to self to mark the first reference 5293b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch // should avoid most instances of branch offset overflow. See 5303b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch // target_at() for where this is converted back to kEndOfChain. 5313b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch target_pos = pc_offset(); 5323b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } 5333b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch L->link_to(pc_offset()); 5343b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 5353b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch constant = target_pos - pc_offset(); 5363b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } 5373b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch llilf(r1, Operand(constant)); 5383b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 5393b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 5403b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Pseudo op - branch on condition 5413b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::branchOnCond(Condition c, int branch_offset, bool is_bound) { 54262ed631aa0ff23db68a47fd423efa9c019ff2c9eBen Murdoch int offset_in_halfwords = branch_offset / 2; 54362ed631aa0ff23db68a47fd423efa9c019ff2c9eBen Murdoch if (is_bound && is_int16(offset_in_halfwords)) { 54462ed631aa0ff23db68a47fd423efa9c019ff2c9eBen Murdoch brc(c, Operand(offset_in_halfwords)); // short jump 5453b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } else { 54662ed631aa0ff23db68a47fd423efa9c019ff2c9eBen Murdoch brcl(c, Operand(offset_in_halfwords)); // long jump 5473b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } 5483b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 5493b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 5503b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// 32-bit Store Multiple - short displacement (12-bits unsigned) 5513b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::stm(Register r1, Register r2, const MemOperand& src) { 5523b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rs_form(STM, r1, r2, src.rb(), src.offset()); 5533b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 5543b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 5553b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// 32-bit Store Multiple - long displacement (20-bits signed) 5563b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::stmy(Register r1, Register r2, const MemOperand& src) { 5573b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rsy_form(STMY, r1, r2, src.rb(), src.offset()); 5583b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 5593b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 5603b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// 64-bit Store Multiple - long displacement (20-bits signed) 5613b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::stmg(Register r1, Register r2, const MemOperand& src) { 5623b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rsy_form(STMG, r1, r2, src.rb(), src.offset()); 5633b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 5643b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 5653b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Exception-generating instructions and debugging support. 5663b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Stops with a non-negative code less than kNumOfWatchedStops support 5673b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// enabling/disabling and a counter feature. See simulator-s390.h . 5683b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::stop(const char* msg, Condition cond, int32_t code, 5693b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch CRegister cr) { 5703b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch if (cond != al) { 5713b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch Label skip; 5723b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch b(NegateCondition(cond), &skip, Label::kNear); 5733b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch bkpt(0); 5743b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch bind(&skip); 5753b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } else { 5763b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch bkpt(0); 5773b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } 5783b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 5793b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 5803b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::bkpt(uint32_t imm16) { 5813b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch // GDB software breakpoint instruction 5823b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch emit2bytes(0x0001); 5833b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 5843b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 5853b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Pseudo instructions. 5863b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::nop(int type) { 5873b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch switch (type) { 5883b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch case 0: 5893b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch lr(r0, r0); 5903b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch break; 5913b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch case DEBUG_BREAK_NOP: 5923b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch // TODO(john.yan): Use a better NOP break 5933b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch oill(r3, Operand::Zero()); 5943b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch break; 5953b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch default: 5963b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch UNIMPLEMENTED(); 5973b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } 5983b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 5993b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 6003b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 6013b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 6023b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// RI1 format: <insn> R1,I2 6033b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// +--------+----+----+------------------+ 6043b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// | OpCode | R1 |OpCd| I2 | 6053b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// +--------+----+----+------------------+ 6063b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// 0 8 12 16 31 6073b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch#define RI1_FORM_EMIT(name, op) \ 6083b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch void Assembler::name(Register r, const Operand& i2) { ri_form(op, r, i2); } 6093b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 6103b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::ri_form(Opcode op, Register r1, const Operand& i2) { 6113b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(is_uint12(op)); 6123b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(is_uint16(i2.imm_) || is_int16(i2.imm_)); 6133b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch emit4bytes((op & 0xFF0) * B20 | r1.code() * B20 | (op & 0xF) * B16 | 6143b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (i2.imm_ & 0xFFFF)); 6153b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 6163b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 6173b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// RI2 format: <insn> M1,I2 6183b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// +--------+----+----+------------------+ 6193b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// | OpCode | M1 |OpCd| I2 | 6203b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// +--------+----+----+------------------+ 6213b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// 0 8 12 16 31 6223b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch#define RI2_FORM_EMIT(name, op) \ 6233b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch void Assembler::name(Condition m, const Operand& i2) { ri_form(op, m, i2); } 6243b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 6253b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::ri_form(Opcode op, Condition m1, const Operand& i2) { 6263b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(is_uint12(op)); 6273b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(is_uint4(m1)); 62862ed631aa0ff23db68a47fd423efa9c019ff2c9eBen Murdoch DCHECK(op == BRC ? is_int16(i2.imm_) : is_uint16(i2.imm_)); 6293b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch emit4bytes((op & 0xFF0) * B20 | m1 * B20 | (op & 0xF) * B16 | 6303b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (i2.imm_ & 0xFFFF)); 6313b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 6323b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 6333b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// RIE-f format: <insn> R1,R2,I3,I4,I5 6343b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// +--------+----+----+------------------+--------+--------+ 6353b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// | OpCode | R1 | R2 | I3 | I4 | I5 | OpCode | 6363b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// +--------+----+----+------------------+--------+--------+ 6373b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// 0 8 12 16 24 32 40 47 6383b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::rie_f_form(Opcode op, Register r1, Register r2, 6393b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch const Operand& i3, const Operand& i4, 6403b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch const Operand& i5) { 6413b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(is_uint16(op)); 6423b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(is_uint8(i3.imm_)); 6433b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(is_uint8(i4.imm_)); 6443b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(is_uint8(i5.imm_)); 6453b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch uint64_t code = (static_cast<uint64_t>(op & 0xFF00)) * B32 | 6463b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(r1.code())) * B36 | 6473b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(r2.code())) * B32 | 6483b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(i3.imm_)) * B24 | 6493b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(i4.imm_)) * B16 | 6503b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(i5.imm_)) * B8 | 6513b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(op & 0x00FF)); 6523b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch emit6bytes(code); 6533b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 6543b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 6553b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// RIE format: <insn> R1,R3,I2 6563b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// +--------+----+----+------------------+--------+--------+ 6573b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// | OpCode | R1 | R3 | I2 |////////| OpCode | 6583b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// +--------+----+----+------------------+--------+--------+ 6593b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// 0 8 12 16 32 40 47 6603b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch#define RIE_FORM_EMIT(name, op) \ 6613b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch void Assembler::name(Register r1, Register r3, const Operand& i2) { \ 6623b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rie_form(op, r1, r3, i2); \ 6633b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } 6643b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 6653b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::rie_form(Opcode op, Register r1, Register r3, 6663b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch const Operand& i2) { 6673b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(is_uint16(op)); 6683b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(is_int16(i2.imm_)); 6693b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch uint64_t code = (static_cast<uint64_t>(op & 0xFF00)) * B32 | 6703b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(r1.code())) * B36 | 6713b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(r3.code())) * B32 | 6723b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(i2.imm_ & 0xFFFF)) * B16 | 6733b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(op & 0x00FF)); 6743b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch emit6bytes(code); 6753b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 6763b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 6773b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// RS1 format: <insn> R1,R3,D2(B2) 6783b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// +--------+----+----+----+-------------+ 6793b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// | OpCode | R1 | R3 | B2 | D2 | 6803b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// +--------+----+----+----+-------------+ 6813b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// 0 8 12 16 20 31 6823b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch#define RS1_FORM_EMIT(name, op) \ 6833b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch void Assembler::name(Register r1, Register r3, Register b2, Disp d2) { \ 6843b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rs_form(op, r1, r3, b2, d2); \ 6853b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } \ 6863b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch void Assembler::name(Register r1, Register r3, const MemOperand& opnd) { \ 6873b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch name(r1, r3, opnd.getBaseRegister(), opnd.getDisplacement()); \ 6883b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } 6893b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 6903b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::rs_form(Opcode op, Register r1, Register r3, Register b2, 6913b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch const Disp d2) { 6923b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(is_uint12(d2)); 6933b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch emit4bytes(op * B24 | r1.code() * B20 | r3.code() * B16 | b2.code() * B12 | 6943b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch d2); 6953b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 6963b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 6973b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// RS2 format: <insn> R1,M3,D2(B2) 6983b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// +--------+----+----+----+-------------+ 6993b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// | OpCode | R1 | M3 | B2 | D2 | 7003b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// +--------+----+----+----+-------------+ 7013b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// 0 8 12 16 20 31 7023b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch#define RS2_FORM_EMIT(name, op) \ 7033b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch void Assembler::name(Register r1, Condition m3, Register b2, Disp d2) { \ 7043b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rs_form(op, r1, m3, b2, d2); \ 7053b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } \ 7063b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch void Assembler::name(Register r1, Condition m3, const MemOperand& opnd) { \ 7073b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch name(r1, m3, opnd.getBaseRegister(), opnd.getDisplacement()); \ 7083b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } 7093b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 7103b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::rs_form(Opcode op, Register r1, Condition m3, Register b2, 7113b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch const Disp d2) { 7123b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(is_uint12(d2)); 7133b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch emit4bytes(op * B24 | r1.code() * B20 | m3 * B16 | b2.code() * B12 | d2); 7143b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 7153b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 7163b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// RSI format: <insn> R1,R3,I2 7173b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// +--------+----+----+------------------+ 7183b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// | OpCode | R1 | R3 | RI2 | 7193b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// +--------+----+----+------------------+ 7203b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// 0 8 12 16 31 7213b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch#define RSI_FORM_EMIT(name, op) \ 7223b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch void Assembler::name(Register r1, Register r3, const Operand& i2) { \ 7233b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rsi_form(op, r1, r3, i2); \ 7243b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } 7253b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 7263b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::rsi_form(Opcode op, Register r1, Register r3, 7273b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch const Operand& i2) { 7283b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(is_uint8(op)); 7293b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(is_uint16(i2.imm_)); 7303b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch emit4bytes(op * B24 | r1.code() * B20 | r3.code() * B16 | (i2.imm_ & 0xFFFF)); 7313b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 7323b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 7333b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// RSL format: <insn> R1,R3,D2(B2) 7343b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// +--------+----+----+----+-------------+--------+--------+ 7353b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// | OpCode | L1 | | B2 | D2 | | OpCode | 7363b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// +--------+----+----+----+-------------+--------+--------+ 7373b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// 0 8 12 16 20 32 40 47 7383b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch#define RSL_FORM_EMIT(name, op) \ 7393b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch void Assembler::name(Length l1, Register b2, Disp d2) { \ 7403b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rsl_form(op, l1, b2, d2); \ 7413b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } 7423b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 7433b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::rsl_form(Opcode op, Length l1, Register b2, Disp d2) { 7443b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(is_uint16(op)); 7453b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch uint64_t code = (static_cast<uint64_t>(op & 0xFF00)) * B32 | 7463b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(l1)) * B36 | 7473b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(b2.code())) * B28 | 7483b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(d2)) * B16 | 7493b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(op & 0x00FF)); 7503b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch emit6bytes(code); 7513b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 7523b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 7533b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// RSY1 format: <insn> R1,R3,D2(B2) 7543b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// +--------+----+----+----+-------------+--------+--------+ 7553b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// | OpCode | R1 | R3 | B2 | DL2 | DH2 | OpCode | 7563b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// +--------+----+----+----+-------------+--------+--------+ 7573b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// 0 8 12 16 20 32 40 47 7583b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch#define RSY1_FORM_EMIT(name, op) \ 7593b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch void Assembler::name(Register r1, Register r3, Register b2, Disp d2) { \ 7603b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rsy_form(op, r1, r3, b2, d2); \ 7613b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } \ 7623b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch void Assembler::name(Register r1, Register r3, const MemOperand& opnd) { \ 7633b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch name(r1, r3, opnd.getBaseRegister(), opnd.getDisplacement()); \ 7643b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } 7653b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 7663b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::rsy_form(Opcode op, Register r1, Register r3, Register b2, 7673b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch const Disp d2) { 7683b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(is_int20(d2)); 7693b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(is_uint16(op)); 7703b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch uint64_t code = (static_cast<uint64_t>(op & 0xFF00)) * B32 | 7713b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(r1.code())) * B36 | 7723b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(r3.code())) * B32 | 7733b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(b2.code())) * B28 | 7743b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(d2 & 0x0FFF)) * B16 | 7753b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(d2 & 0x0FF000)) >> 4 | 7763b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(op & 0x00FF)); 7773b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch emit6bytes(code); 7783b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 7793b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 7803b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// RSY2 format: <insn> R1,M3,D2(B2) 7813b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// +--------+----+----+----+-------------+--------+--------+ 7823b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// | OpCode | R1 | M3 | B2 | DL2 | DH2 | OpCode | 7833b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// +--------+----+----+----+-------------+--------+--------+ 7843b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// 0 8 12 16 20 32 40 47 7853b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch#define RSY2_FORM_EMIT(name, op) \ 7863b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch void Assembler::name(Register r1, Condition m3, Register b2, Disp d2) { \ 7873b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rsy_form(op, r1, m3, b2, d2); \ 7883b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } \ 7893b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch void Assembler::name(Register r1, Condition m3, const MemOperand& opnd) { \ 7903b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch name(r1, m3, opnd.getBaseRegister(), opnd.getDisplacement()); \ 7913b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } 7923b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 7933b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::rsy_form(Opcode op, Register r1, Condition m3, Register b2, 7943b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch const Disp d2) { 7953b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(is_int20(d2)); 7963b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(is_uint16(op)); 7973b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch uint64_t code = (static_cast<uint64_t>(op & 0xFF00)) * B32 | 7983b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(r1.code())) * B36 | 7993b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(m3)) * B32 | 8003b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(b2.code())) * B28 | 8013b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(d2 & 0x0FFF)) * B16 | 8023b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(d2 & 0x0FF000)) >> 4 | 8033b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(op & 0x00FF)); 8043b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch emit6bytes(code); 8053b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 8063b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 8073b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// RXE format: <insn> R1,D2(X2,B2) 8083b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// +--------+----+----+----+-------------+--------+--------+ 8093b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// | OpCode | R1 | X2 | B2 | D2 |////////| OpCode | 8103b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// +--------+----+----+----+-------------+--------+--------+ 8113b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// 0 8 12 16 20 32 40 47 8123b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch#define RXE_FORM_EMIT(name, op) \ 8133b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch void Assembler::name(Register r1, Register x2, Register b2, Disp d2) { \ 8143b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rxe_form(op, r1, x2, b2, d2); \ 8153b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } \ 8163b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch void Assembler::name(Register r1, const MemOperand& opnd) { \ 8173b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch name(r1, opnd.getIndexRegister(), opnd.getBaseRegister(), \ 8183b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch opnd.getDisplacement()); \ 8193b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } 8203b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 8213b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::rxe_form(Opcode op, Register r1, Register x2, Register b2, 8223b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch Disp d2) { 8233b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(is_uint12(d2)); 8243b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(is_uint16(op)); 8253b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch uint64_t code = (static_cast<uint64_t>(op & 0xFF00)) * B32 | 8263b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(r1.code())) * B36 | 8273b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(x2.code())) * B32 | 8283b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(b2.code())) * B28 | 8293b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(d2 & 0x0FFF)) * B16 | 8303b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(op & 0x00FF)); 8313b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch emit6bytes(code); 8323b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 8333b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 8343b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// RRS format: <insn> R1,R2,M3,D4(B4) 8353b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// +--------+----+----+----+-------------+----+---+--------+ 8363b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// | OpCode | R1 | R2 | B4 | D4 | M3 |///| OpCode | 8373b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// +--------+----+----+----+-------------+----+---+--------+ 8383b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// 0 8 12 16 20 32 36 40 47 8393b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch#define RRS_FORM_EMIT(name, op) \ 8403b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch void Assembler::name(Register r1, Register r2, Register b4, Disp d4, \ 8413b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch Condition m3) { \ 8423b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rrs_form(op, r1, r2, b4, d4, m3); \ 8433b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } \ 8443b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch void Assembler::name(Register r1, Register r2, Condition m3, \ 8453b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch const MemOperand& opnd) { \ 8463b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch name(r1, r2, opnd.getBaseRegister(), opnd.getDisplacement(), m3); \ 8473b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } 8483b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 8493b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::rrs_form(Opcode op, Register r1, Register r2, Register b4, 8503b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch Disp d4, Condition m3) { 8513b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(is_uint12(d4)); 8523b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(is_uint16(op)); 8533b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch uint64_t code = (static_cast<uint64_t>(op & 0xFF00)) * B32 | 8543b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(r1.code())) * B36 | 8553b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(r2.code())) * B32 | 8563b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(b4.code())) * B28 | 8573b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(d4)) * B16 | 8583b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(m3)) << 12 | 8593b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(op & 0x00FF)); 8603b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch emit6bytes(code); 8613b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 8623b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 8633b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// RIS format: <insn> R1,I2,M3,D4(B4) 8643b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// +--------+----+----+----+-------------+--------+--------+ 8653b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// | OpCode | R1 | M3 | B4 | D4 | I2 | OpCode | 8663b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// +--------+----+----+----+-------------+--------+--------+ 8673b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// 0 8 12 16 20 32 40 47 8683b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch#define RIS_FORM_EMIT(name, op) \ 8693b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch void Assembler::name(Register r1, Condition m3, Register b4, Disp d4, \ 8703b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch const Operand& i2) { \ 8713b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch ris_form(op, r1, m3, b4, d4, i2); \ 8723b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } \ 8733b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch void Assembler::name(Register r1, const Operand& i2, Condition m3, \ 8743b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch const MemOperand& opnd) { \ 8753b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch name(r1, m3, opnd.getBaseRegister(), opnd.getDisplacement(), i2); \ 8763b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } 8773b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 8783b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::ris_form(Opcode op, Register r1, Condition m3, Register b4, 8793b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch Disp d4, const Operand& i2) { 8803b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(is_uint12(d4)); 8813b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(is_uint16(op)); 8823b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(is_uint8(i2.imm_)); 8833b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch uint64_t code = (static_cast<uint64_t>(op & 0xFF00)) * B32 | 8843b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(r1.code())) * B36 | 8853b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(m3)) * B32 | 8863b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(b4.code())) * B28 | 8873b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(d4)) * B16 | 8883b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(i2.imm_)) << 8 | 8893b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(op & 0x00FF)); 8903b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch emit6bytes(code); 8913b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 8923b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 8933b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// S format: <insn> D2(B2) 8943b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// +------------------+----+-------------+ 8953b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// | OpCode | B2 | D2 | 8963b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// +------------------+----+-------------+ 8973b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// 0 16 20 31 8983b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch#define S_FORM_EMIT(name, op) \ 8993b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch void Assembler::name(Register b1, Disp d2) { s_form(op, b1, d2); } \ 9003b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch void Assembler::name(const MemOperand& opnd) { \ 9013b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch name(opnd.getBaseRegister(), opnd.getDisplacement()); \ 9023b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } 9033b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 9043b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::s_form(Opcode op, Register b1, Disp d2) { 9053b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(is_uint12(d2)); 9063b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch emit4bytes(op << 16 | b1.code() * B12 | d2); 9073b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 9083b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 9093b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// SI format: <insn> D1(B1),I2 9103b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// +--------+---------+----+-------------+ 9113b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// | OpCode | I2 | B1 | D1 | 9123b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// +--------+---------+----+-------------+ 9133b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// 0 8 16 20 31 9143b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch#define SI_FORM_EMIT(name, op) \ 9153b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch void Assembler::name(const Operand& i2, Register b1, Disp d1) { \ 9163b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch si_form(op, i2, b1, d1); \ 9173b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } \ 9183b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch void Assembler::name(const MemOperand& opnd, const Operand& i2) { \ 9193b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch name(i2, opnd.getBaseRegister(), opnd.getDisplacement()); \ 9203b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } 9213b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 9223b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::si_form(Opcode op, const Operand& i2, Register b1, Disp d1) { 9233b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch emit4bytes((op & 0x00FF) << 24 | i2.imm_ * B16 | b1.code() * B12 | d1); 9243b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 9253b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 9263b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// SIY format: <insn> D1(B1),I2 9273b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// +--------+---------+----+-------------+--------+--------+ 9283b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// | OpCode | I2 | B1 | DL1 | DH1 | OpCode | 9293b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// +--------+---------+----+-------------+--------+--------+ 9303b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// 0 8 16 20 32 36 40 47 9313b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch#define SIY_FORM_EMIT(name, op) \ 9323b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch void Assembler::name(const Operand& i2, Register b1, Disp d1) { \ 9333b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch siy_form(op, i2, b1, d1); \ 9343b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } \ 9353b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch void Assembler::name(const MemOperand& opnd, const Operand& i2) { \ 9363b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch name(i2, opnd.getBaseRegister(), opnd.getDisplacement()); \ 9373b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } 9383b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 9393b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::siy_form(Opcode op, const Operand& i2, Register b1, Disp d1) { 94062ed631aa0ff23db68a47fd423efa9c019ff2c9eBen Murdoch DCHECK(is_uint20(d1) || is_int20(d1)); 9413b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(is_uint16(op)); 9423b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(is_uint8(i2.imm_)); 9433b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch uint64_t code = (static_cast<uint64_t>(op & 0xFF00)) * B32 | 9443b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(i2.imm_)) * B32 | 9453b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(b1.code())) * B28 | 9463b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(d1 & 0x0FFF)) * B16 | 9473b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(d1 & 0x0FF000)) >> 4 | 9483b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(op & 0x00FF)); 9493b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch emit6bytes(code); 9503b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 9513b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 9523b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// SIL format: <insn> D1(B1),I2 9533b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// +------------------+----+-------------+-----------------+ 9543b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// | OpCode | B1 | D1 | I2 | 9553b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// +------------------+----+-------------+-----------------+ 9563b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// 0 16 20 32 47 9573b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch#define SIL_FORM_EMIT(name, op) \ 9583b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch void Assembler::name(Register b1, Disp d1, const Operand& i2) { \ 9593b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch sil_form(op, b1, d1, i2); \ 9603b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } \ 9613b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch void Assembler::name(const MemOperand& opnd, const Operand& i2) { \ 9623b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch name(opnd.getBaseRegister(), opnd.getDisplacement(), i2); \ 9633b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } 9643b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 9653b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::sil_form(Opcode op, Register b1, Disp d1, const Operand& i2) { 9663b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(is_uint12(d1)); 9673b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(is_uint16(op)); 9683b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(is_uint16(i2.imm_)); 9693b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch uint64_t code = (static_cast<uint64_t>(op)) * B32 | 9703b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(b1.code())) * B28 | 9713b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(d1)) * B16 | 9723b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(i2.imm_)); 9733b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch emit6bytes(code); 9743b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 9753b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 9763b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// RXF format: <insn> R1,R3,D2(X2,B2) 9773b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// +--------+----+----+----+-------------+----+---+--------+ 9783b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// | OpCode | R3 | X2 | B2 | D2 | R1 |///| OpCode | 9793b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// +--------+----+----+----+-------------+----+---+--------+ 9803b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// 0 8 12 16 20 32 36 40 47 9813b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch#define RXF_FORM_EMIT(name, op) \ 9823b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch void Assembler::name(Register r1, Register r3, Register b2, Register x2, \ 9833b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch Disp d2) { \ 9843b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rxf_form(op, r1, r3, b2, x2, d2); \ 9853b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } \ 9863b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch void Assembler::name(Register r1, Register r3, const MemOperand& opnd) { \ 9873b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch name(r1, r3, opnd.getBaseRegister(), opnd.getIndexRegister(), \ 9883b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch opnd.getDisplacement()); \ 9893b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } 9903b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 9913b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::rxf_form(Opcode op, Register r1, Register r3, Register b2, 9923b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch Register x2, Disp d2) { 9933b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(is_uint12(d2)); 9943b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(is_uint16(op)); 9953b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch uint64_t code = (static_cast<uint64_t>(op & 0xFF00)) * B32 | 9963b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(r3.code())) * B36 | 9973b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(x2.code())) * B32 | 9983b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(b2.code())) * B28 | 9993b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(d2)) * B16 | 10003b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(r1.code())) * B12 | 10013b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(op & 0x00FF)); 10023b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch emit6bytes(code); 10033b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 10043b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 10053b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// SS1 format: <insn> D1(L,B1),D2(B3) 10063b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// +--------+----+----+----+-------------+----+------------+ 10073b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// | OpCode | L | B1 | D1 | B2 | D2 | 10083b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// +--------+----+----+----+-------------+----+------------+ 10093b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// 0 8 12 16 20 32 36 47 10103b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch#define SS1_FORM_EMIT(name, op) \ 10113b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch void Assembler::name(Register b1, Disp d1, Register b2, Disp d2, Length l) { \ 10123b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch ss_form(op, l, b1, d1, b2, d2); \ 10133b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } \ 10143b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch void Assembler::name(const MemOperand& opnd1, const MemOperand& opnd2, \ 10153b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch Length length) { \ 10163b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch name(opnd1.getBaseRegister(), opnd1.getDisplacement(), \ 10173b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch opnd2.getBaseRegister(), opnd2.getDisplacement(), length); \ 10183b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } 10193b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 10203b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::ss_form(Opcode op, Length l, Register b1, Disp d1, Register b2, 10213b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch Disp d2) { 10223b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(is_uint12(d2)); 10233b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(is_uint12(d1)); 10243b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(is_uint8(op)); 10253b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(is_uint8(l)); 10263b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch uint64_t code = 10273b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(op)) * B40 | (static_cast<uint64_t>(l)) * B32 | 10283b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(b1.code())) * B28 | 10293b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(d1)) * B16 | 10303b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(b2.code())) * B12 | (static_cast<uint64_t>(d2)); 10313b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch emit6bytes(code); 10323b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 10333b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 10343b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// SS2 format: <insn> D1(L1,B1), D2(L3,B3) 10353b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// +--------+----+----+----+-------------+----+------------+ 10363b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// | OpCode | L1 | L2 | B1 | D1 | B2 | D2 | 10373b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// +--------+----+----+----+-------------+----+------------+ 10383b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// 0 8 12 16 20 32 36 47 10393b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch#define SS2_FORM_EMIT(name, op) \ 10403b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch void Assembler::name(Register b1, Disp d1, Register b2, Disp d2, Length l1, \ 10413b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch Length l2) { \ 10423b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch ss_form(op, l1, l2, b1, d1, b2, d2); \ 10433b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } \ 10443b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch void Assembler::name(const MemOperand& opnd1, const MemOperand& opnd2, \ 10453b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch Length length1, Length length2) { \ 10463b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch name(opnd1.getBaseRegister(), opnd1.getDisplacement(), \ 10473b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch opnd2.getBaseRegister(), opnd2.getDisplacement(), length1, length2); \ 10483b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } 10493b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 10503b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::ss_form(Opcode op, Length l1, Length l2, Register b1, Disp d1, 10513b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch Register b2, Disp d2) { 10523b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(is_uint12(d2)); 10533b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(is_uint12(d1)); 10543b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(is_uint8(op)); 10553b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(is_uint4(l2)); 10563b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(is_uint4(l1)); 10573b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch uint64_t code = 10583b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(op)) * B40 | (static_cast<uint64_t>(l1)) * B36 | 10593b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(l2)) * B32 | 10603b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(b1.code())) * B28 | 10613b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(d1)) * B16 | 10623b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(b2.code())) * B12 | (static_cast<uint64_t>(d2)); 10633b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch emit6bytes(code); 10643b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 10653b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 10663b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// SS3 format: <insn> D1(L1,B1), D2(I3,B2) 10673b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// +--------+----+----+----+-------------+----+------------+ 10683b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// | OpCode | L1 | I3 | B1 | D1 | B2 | D2 | 10693b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// +--------+----+----+----+-------------+----+------------+ 10703b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// 0 8 12 16 20 32 36 47 10713b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch#define SS3_FORM_EMIT(name, op) \ 10723b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch void Assembler::name(const Operand& i3, Register b1, Disp d1, Register b2, \ 10733b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch Disp d2, Length l1) { \ 10743b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch ss_form(op, l1, i3, b1, d1, b2, d2); \ 10753b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } \ 10763b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch void Assembler::name(const MemOperand& opnd1, const MemOperand& opnd2, \ 10773b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch Length length) { \ 10783b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(false); \ 10793b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } 10803b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::ss_form(Opcode op, Length l1, const Operand& i3, Register b1, 10813b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch Disp d1, Register b2, Disp d2) { 10823b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(is_uint12(d2)); 10833b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(is_uint12(d1)); 10843b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(is_uint8(op)); 10853b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(is_uint4(l1)); 10863b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(is_uint4(i3.imm_)); 10873b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch uint64_t code = 10883b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(op)) * B40 | (static_cast<uint64_t>(l1)) * B36 | 10893b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(i3.imm_)) * B32 | 10903b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(b1.code())) * B28 | 10913b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(d1)) * B16 | 10923b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(b2.code())) * B12 | (static_cast<uint64_t>(d2)); 10933b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch emit6bytes(code); 10943b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 10953b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 10963b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// SS4 format: <insn> D1(R1,B1), D2(R3,B2) 10973b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// +--------+----+----+----+-------------+----+------------+ 10983b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// | OpCode | R1 | R3 | B1 | D1 | B2 | D2 | 10993b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// +--------+----+----+----+-------------+----+------------+ 11003b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// 0 8 12 16 20 32 36 47 11013b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch#define SS4_FORM_EMIT(name, op) \ 11023b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch void Assembler::name(Register r1, Register r3, Register b1, Disp d1, \ 11033b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch Register b2, Disp d2) { \ 11043b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch ss_form(op, r1, r3, b1, d1, b2, d2); \ 11053b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } \ 11063b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch void Assembler::name(const MemOperand& opnd1, const MemOperand& opnd2) { \ 11073b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(false); \ 11083b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } 11093b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::ss_form(Opcode op, Register r1, Register r3, Register b1, 11103b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch Disp d1, Register b2, Disp d2) { 11113b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(is_uint12(d2)); 11123b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(is_uint12(d1)); 11133b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(is_uint8(op)); 11143b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch uint64_t code = (static_cast<uint64_t>(op)) * B40 | 11153b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(r1.code())) * B36 | 11163b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(r3.code())) * B32 | 11173b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(b1.code())) * B28 | 11183b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(d1)) * B16 | 11193b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(b2.code())) * B12 | 11203b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(d2)); 11213b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch emit6bytes(code); 11223b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 11233b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 11243b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// SS5 format: <insn> D1(R1,B1), D2(R3,B2) 11253b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// +--------+----+----+----+-------------+----+------------+ 11263b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// | OpCode | R1 | R3 | B2 | D2 | B4 | D4 | 11273b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// +--------+----+----+----+-------------+----+------------+ 11283b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// 0 8 12 16 20 32 36 47 11293b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch#define SS5_FORM_EMIT(name, op) \ 11303b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch void Assembler::name(Register r1, Register r3, Register b2, Disp d2, \ 11313b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch Register b4, Disp d4) { \ 11323b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch ss_form(op, r1, r3, b2, d2, b4, d4); /*SS5 use the same form as SS4*/ \ 11333b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } \ 11343b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch void Assembler::name(const MemOperand& opnd1, const MemOperand& opnd2) { \ 11353b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(false); \ 11363b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } 11373b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 11383b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch#define SS6_FORM_EMIT(name, op) SS1_FORM_EMIT(name, op) 11393b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 11403b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// SSE format: <insn> D1(B1),D2(B2) 11413b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// +------------------+----+-------------+----+------------+ 11423b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// | OpCode | B1 | D1 | B2 | D2 | 11433b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// +------------------+----+-------------+----+------------+ 11443b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// 0 8 12 16 20 32 36 47 11453b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch#define SSE_FORM_EMIT(name, op) \ 11463b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch void Assembler::name(Register b1, Disp d1, Register b2, Disp d2) { \ 11473b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch sse_form(op, b1, d1, b2, d2); \ 11483b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } \ 11493b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch void Assembler::name(const MemOperand& opnd1, const MemOperand& opnd2) { \ 11503b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch name(opnd1.getBaseRegister(), opnd1.getDisplacement(), \ 11513b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch opnd2.getBaseRegister(), opnd2.getDisplacement()); \ 11523b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } 11533b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::sse_form(Opcode op, Register b1, Disp d1, Register b2, 11543b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch Disp d2) { 11553b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(is_uint12(d2)); 11563b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(is_uint12(d1)); 11573b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(is_uint16(op)); 11583b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch uint64_t code = (static_cast<uint64_t>(op)) * B32 | 11593b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(b1.code())) * B28 | 11603b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(d1)) * B16 | 11613b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(b2.code())) * B12 | 11623b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(d2)); 11633b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch emit6bytes(code); 11643b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 11653b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 11663b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// SSF format: <insn> R3, D1(B1),D2(B2),R3 11673b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// +--------+----+----+----+-------------+----+------------+ 11683b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// | OpCode | R3 |OpCd| B1 | D1 | B2 | D2 | 11693b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// +--------+----+----+----+-------------+----+------------+ 11703b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// 0 8 12 16 20 32 36 47 11713b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch#define SSF_FORM_EMIT(name, op) \ 11723b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch void Assembler::name(Register r3, Register b1, Disp d1, Register b2, \ 11733b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch Disp d2) { \ 11743b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch ssf_form(op, r3, b1, d1, b2, d2); \ 11753b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } \ 11763b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch void Assembler::name(Register r3, const MemOperand& opnd1, \ 11773b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch const MemOperand& opnd2) { \ 11783b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch name(r3, opnd1.getBaseRegister(), opnd1.getDisplacement(), \ 11793b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch opnd2.getBaseRegister(), opnd2.getDisplacement()); \ 11803b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } 11813b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 11823b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::ssf_form(Opcode op, Register r3, Register b1, Disp d1, 11833b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch Register b2, Disp d2) { 11843b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(is_uint12(d2)); 11853b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(is_uint12(d1)); 11863b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(is_uint12(op)); 11873b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch uint64_t code = (static_cast<uint64_t>(op & 0xFF0)) * B36 | 11883b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(r3.code())) * B36 | 11893b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(op & 0x00F)) * B32 | 11903b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(b1.code())) * B28 | 11913b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(d1)) * B16 | 11923b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(b2.code())) * B12 | 11933b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (static_cast<uint64_t>(d2)); 11943b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch emit6bytes(code); 11953b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 11963b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 11973b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// RRF1 format: <insn> R1,R2,R3 11983b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// +------------------+----+----+----+----+ 11993b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// | OpCode | R3 | | R1 | R2 | 12003b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// +------------------+----+----+----+----+ 12013b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// 0 16 20 24 28 31 12023b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch#define RRF1_FORM_EMIT(name, op) \ 12033b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch void Assembler::name(Register r1, Register r2, Register r3) { \ 12043b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rrf1_form(op << 16 | r3.code() * B12 | r1.code() * B4 | r2.code()); \ 12053b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } 12063b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 12073b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::rrf1_form(Opcode op, Register r1, Register r2, Register r3) { 12083b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch uint32_t code = op << 16 | r3.code() * B12 | r1.code() * B4 | r2.code(); 12093b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch emit4bytes(code); 12103b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 12113b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 12123b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::rrf1_form(uint32_t code) { emit4bytes(code); } 12133b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 12143b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// RRF2 format: <insn> R1,R2,M3 12153b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// +------------------+----+----+----+----+ 12163b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// | OpCode | M3 | | R1 | R2 | 12173b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// +------------------+----+----+----+----+ 12183b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// 0 16 20 24 28 31 12193b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch#define RRF2_FORM_EMIT(name, op) \ 12203b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch void Assembler::name(Condition m3, Register r1, Register r2) { \ 12213b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rrf2_form(op << 16 | m3 * B12 | r1.code() * B4 | r2.code()); \ 12223b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } 12233b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 12243b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::rrf2_form(uint32_t code) { emit4bytes(code); } 12253b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 12263b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// RRF3 format: <insn> R1,R2,R3,M4 12273b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// +------------------+----+----+----+----+ 12283b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// | OpCode | R3 | M4 | R1 | R2 | 12293b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// +------------------+----+----+----+----+ 12303b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// 0 16 20 24 28 31 12313b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch#define RRF3_FORM_EMIT(name, op) \ 12323b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch void Assembler::name(Register r3, Conition m4, Register r1, Register r2) { \ 12333b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rrf3_form(op << 16 | r3.code() * B12 | m4 * B8 | r1.code() * B4 | \ 12343b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch r2.code()); \ 12353b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } 12363b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 12373b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::rrf3_form(uint32_t code) { emit4bytes(code); } 12383b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 12393b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// RRF-e format: <insn> R1,M3,R2,M4 12403b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// +------------------+----+----+----+----+ 12413b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// | OpCode | M3 | M4 | R1 | R2 | 12423b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// +------------------+----+----+----+----+ 12433b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// 0 16 20 24 28 31 12443b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::rrfe_form(Opcode op, Condition m3, Condition m4, Register r1, 12453b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch Register r2) { 12463b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch uint32_t code = op << 16 | m3 * B12 | m4 * B8 | r1.code() * B4 | r2.code(); 12473b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch emit4bytes(code); 12483b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 12493b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 12503b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// end of S390 Instruction generation 12513b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 12523b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// start of S390 instruction 12533b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben MurdochSS1_FORM_EMIT(ed, ED) 12543b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben MurdochSS1_FORM_EMIT(mvn, MVN) 12553b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben MurdochSS1_FORM_EMIT(nc, NC) 12563b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben MurdochSI_FORM_EMIT(ni, NI) 12573b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben MurdochRI1_FORM_EMIT(nilh, NILH) 12583b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben MurdochRI1_FORM_EMIT(nill, NILL) 12593b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben MurdochRI1_FORM_EMIT(oill, OILL) 12603b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben MurdochRI1_FORM_EMIT(tmll, TMLL) 12613b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben MurdochSS1_FORM_EMIT(tr, TR) 12623b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben MurdochS_FORM_EMIT(ts, TS) 12633b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 12643b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// ------------------------- 12653b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Load Address Instructions 12663b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// ------------------------- 12673b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Load Address Relative Long 12683b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::larl(Register r1, Label* l) { 12693b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch larl(r1, Operand(branch_offset(l))); 12703b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 12713b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 12723b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// ----------------- 12733b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Load Instructions 12743b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// ----------------- 12753b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Load Halfword Immediate (32) 12763b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::lhi(Register r, const Operand& imm) { ri_form(LHI, r, imm); } 12773b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 12783b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Load Halfword Immediate (64) 12793b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::lghi(Register r, const Operand& imm) { ri_form(LGHI, r, imm); } 12803b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 12813b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// ------------------------- 12823b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Load Logical Instructions 12833b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// ------------------------- 1284f91f0611dbaf29ca0f1d4aecb357ce243a19d2faBen Murdoch// Load On Condition R-R (32) 1285f91f0611dbaf29ca0f1d4aecb357ce243a19d2faBen Murdochvoid Assembler::locr(Condition m3, Register r1, Register r2) { 1286f91f0611dbaf29ca0f1d4aecb357ce243a19d2faBen Murdoch rrf2_form(LOCR << 16 | m3 * B12 | r1.code() * B4 | r2.code()); 1287f91f0611dbaf29ca0f1d4aecb357ce243a19d2faBen Murdoch} 1288f91f0611dbaf29ca0f1d4aecb357ce243a19d2faBen Murdoch 1289f91f0611dbaf29ca0f1d4aecb357ce243a19d2faBen Murdoch// Load On Condition R-R (64) 1290f91f0611dbaf29ca0f1d4aecb357ce243a19d2faBen Murdochvoid Assembler::locgr(Condition m3, Register r1, Register r2) { 1291f91f0611dbaf29ca0f1d4aecb357ce243a19d2faBen Murdoch rrf2_form(LOCGR << 16 | m3 * B12 | r1.code() * B4 | r2.code()); 1292f91f0611dbaf29ca0f1d4aecb357ce243a19d2faBen Murdoch} 1293f91f0611dbaf29ca0f1d4aecb357ce243a19d2faBen Murdoch 1294f91f0611dbaf29ca0f1d4aecb357ce243a19d2faBen Murdoch// Load On Condition R-M (32) 1295f91f0611dbaf29ca0f1d4aecb357ce243a19d2faBen Murdochvoid Assembler::loc(Condition m3, Register r1, const MemOperand& src) { 129662ed631aa0ff23db68a47fd423efa9c019ff2c9eBen Murdoch rsy_form(LOC, r1, m3, src.rb(), src.offset()); 1297f91f0611dbaf29ca0f1d4aecb357ce243a19d2faBen Murdoch} 1298f91f0611dbaf29ca0f1d4aecb357ce243a19d2faBen Murdoch 1299f91f0611dbaf29ca0f1d4aecb357ce243a19d2faBen Murdoch// Load On Condition R-M (64) 1300f91f0611dbaf29ca0f1d4aecb357ce243a19d2faBen Murdochvoid Assembler::locg(Condition m3, Register r1, const MemOperand& src) { 130162ed631aa0ff23db68a47fd423efa9c019ff2c9eBen Murdoch rsy_form(LOCG, r1, m3, src.rb(), src.offset()); 1302f91f0611dbaf29ca0f1d4aecb357ce243a19d2faBen Murdoch} 1303f91f0611dbaf29ca0f1d4aecb357ce243a19d2faBen Murdoch 13043b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// ------------------- 13053b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Branch Instructions 13063b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// ------------------- 13073b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Branch on Count (64) 13083b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Branch Relative and Save (32) 13093b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::bras(Register r, const Operand& opnd) { 13103b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch ri_form(BRAS, r, opnd); 13113b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 13123b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 13133b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Branch relative on Condition (32) 131462ed631aa0ff23db68a47fd423efa9c019ff2c9eBen Murdochvoid Assembler::brc(Condition c, const Operand& opnd) { ri_form(BRC, c, opnd); } 13153b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 13163b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Branch On Count (32) 13173b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::brct(Register r1, const Operand& imm) { 13183b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch // BRCT encodes # of halfwords, so divide by 2. 13193b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch int16_t numHalfwords = static_cast<int16_t>(imm.immediate()) / 2; 13203b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch Operand halfwordOp = Operand(numHalfwords); 13213b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch halfwordOp.setBits(16); 13223b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch ri_form(BRCT, r1, halfwordOp); 13233b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 13243b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 13253b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Branch On Count (32) 13263b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::brctg(Register r1, const Operand& imm) { 13273b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch // BRCTG encodes # of halfwords, so divide by 2. 13283b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch int16_t numHalfwords = static_cast<int16_t>(imm.immediate()) / 2; 13293b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch Operand halfwordOp = Operand(numHalfwords); 13303b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch halfwordOp.setBits(16); 13313b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch ri_form(BRCTG, r1, halfwordOp); 13323b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 13333b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 13343b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// -------------------- 13353b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Compare Instructions 13363b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// -------------------- 13373b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Compare Halfword Immediate (32) 13383b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::chi(Register r, const Operand& opnd) { ri_form(CHI, r, opnd); } 13393b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 13403b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Compare Halfword Immediate (64) 13413b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::cghi(Register r, const Operand& opnd) { 13423b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch ri_form(CGHI, r, opnd); 13433b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 13443b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 13453b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// ---------------------------- 13463b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Compare Logical Instructions 13473b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// ---------------------------- 13483b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Compare Immediate (Mem - Imm) (8) 13493b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::cli(const MemOperand& opnd, const Operand& imm) { 13503b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch si_form(CLI, imm, opnd.rb(), opnd.offset()); 13513b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 13523b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 13533b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Compare Immediate (Mem - Imm) (8) 13543b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::cliy(const MemOperand& opnd, const Operand& imm) { 13553b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch siy_form(CLIY, imm, opnd.rb(), opnd.offset()); 13563b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 13573b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 13583b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Compare logical - mem to mem operation 13593b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::clc(const MemOperand& opnd1, const MemOperand& opnd2, 13603b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch Length length) { 13613b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch ss_form(CLC, length - 1, opnd1.getBaseRegister(), opnd1.getDisplacement(), 13623b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch opnd2.getBaseRegister(), opnd2.getDisplacement()); 13633b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 13643b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 13653b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// ---------------------------- 13663b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Test Under Mask Instructions 13673b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// ---------------------------- 13683b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Test Under Mask (Mem - Imm) (8) 13693b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::tm(const MemOperand& opnd, const Operand& imm) { 13703b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch si_form(TM, imm, opnd.rb(), opnd.offset()); 13713b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 13723b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 13733b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Test Under Mask (Mem - Imm) (8) 13743b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::tmy(const MemOperand& opnd, const Operand& imm) { 13753b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch siy_form(TMY, imm, opnd.rb(), opnd.offset()); 13763b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 13773b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 13783b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// ------------------------------- 13793b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Rotate and Insert Selected Bits 13803b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// ------------------------------- 13813b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Rotate-And-Insert-Selected-Bits 13823b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::risbg(Register dst, Register src, const Operand& startBit, 13833b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch const Operand& endBit, const Operand& shiftAmt, 13843b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch bool zeroBits) { 13853b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch // High tag the top bit of I4/EndBit to zero out any unselected bits 13863b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch if (zeroBits) 13873b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rie_f_form(RISBG, dst, src, startBit, Operand(endBit.imm_ | 0x80), 13883b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch shiftAmt); 13893b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch else 13903b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rie_f_form(RISBG, dst, src, startBit, endBit, shiftAmt); 13913b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 13923b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 13933b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Rotate-And-Insert-Selected-Bits 13943b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::risbgn(Register dst, Register src, const Operand& startBit, 13953b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch const Operand& endBit, const Operand& shiftAmt, 13963b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch bool zeroBits) { 13973b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch // High tag the top bit of I4/EndBit to zero out any unselected bits 13983b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch if (zeroBits) 13993b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rie_f_form(RISBGN, dst, src, startBit, Operand(endBit.imm_ | 0x80), 14003b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch shiftAmt); 14013b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch else 14023b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rie_f_form(RISBGN, dst, src, startBit, endBit, shiftAmt); 14033b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 14043b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 14053b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// --------------------------- 14063b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Move Character Instructions 14073b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// --------------------------- 14083b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Move charactor - mem to mem operation 14093b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::mvc(const MemOperand& opnd1, const MemOperand& opnd2, 14103b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch uint32_t length) { 14113b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch ss_form(MVC, length - 1, opnd1.getBaseRegister(), opnd1.getDisplacement(), 14123b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch opnd2.getBaseRegister(), opnd2.getDisplacement()); 14133b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 14143b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 14153b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// ----------------------- 14163b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// 32-bit Add Instructions 14173b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// ----------------------- 14183b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Add Halfword Immediate (32) 14193b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::ahi(Register r1, const Operand& i2) { ri_form(AHI, r1, i2); } 14203b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 14213b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Add Halfword Immediate (32) 14223b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::ahik(Register r1, Register r3, const Operand& i2) { 14233b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rie_form(AHIK, r1, r3, i2); 14243b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 14253b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 14263b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Add Register-Register-Register (32) 14273b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::ark(Register r1, Register r2, Register r3) { 14283b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rrf1_form(ARK, r1, r2, r3); 14293b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 14303b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 14313b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Add Storage-Imm (32) 14323b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::asi(const MemOperand& opnd, const Operand& imm) { 14333b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(is_int8(imm.imm_)); 14343b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(is_int20(opnd.offset())); 14353b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch siy_form(ASI, Operand(0xff & imm.imm_), opnd.rb(), 0xfffff & opnd.offset()); 14363b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 14373b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 14383b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// ----------------------- 14393b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// 64-bit Add Instructions 14403b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// ----------------------- 14413b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Add Halfword Immediate (64) 14423b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::aghi(Register r1, const Operand& i2) { ri_form(AGHI, r1, i2); } 14433b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 14443b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Add Halfword Immediate (64) 14453b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::aghik(Register r1, Register r3, const Operand& i2) { 14463b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rie_form(AGHIK, r1, r3, i2); 14473b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 14483b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 14493b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Add Register-Register-Register (64) 14503b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::agrk(Register r1, Register r2, Register r3) { 14513b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rrf1_form(AGRK, r1, r2, r3); 14523b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 14533b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 14543b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Add Storage-Imm (64) 14553b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::agsi(const MemOperand& opnd, const Operand& imm) { 14563b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(is_int8(imm.imm_)); 14573b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(is_int20(opnd.offset())); 14583b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch siy_form(AGSI, Operand(0xff & imm.imm_), opnd.rb(), 0xfffff & opnd.offset()); 14593b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 14603b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 14613b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// ------------------------------- 14623b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// 32-bit Add Logical Instructions 14633b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// ------------------------------- 14643b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Add Logical Register-Register-Register (32) 14653b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::alrk(Register r1, Register r2, Register r3) { 14663b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rrf1_form(ALRK, r1, r2, r3); 14673b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 14683b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 14693b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// ------------------------------- 14703b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// 64-bit Add Logical Instructions 14713b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// ------------------------------- 14723b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Add Logical Register-Register-Register (64) 14733b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::algrk(Register r1, Register r2, Register r3) { 14743b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rrf1_form(ALGRK, r1, r2, r3); 14753b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 14763b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 14773b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// ---------------------------- 14783b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// 32-bit Subtract Instructions 14793b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// ---------------------------- 14803b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Subtract Register-Register-Register (32) 14813b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::srk(Register r1, Register r2, Register r3) { 14823b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rrf1_form(SRK, r1, r2, r3); 14833b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 14843b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 14853b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// ---------------------------- 14863b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// 64-bit Subtract Instructions 14873b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// ---------------------------- 14883b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Subtract Register-Register-Register (64) 14893b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::sgrk(Register r1, Register r2, Register r3) { 14903b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rrf1_form(SGRK, r1, r2, r3); 14913b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 14923b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 14933b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// ------------------------------------ 14943b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// 32-bit Subtract Logical Instructions 14953b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// ------------------------------------ 14963b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Subtract Logical Register-Register-Register (32) 14973b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::slrk(Register r1, Register r2, Register r3) { 14983b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rrf1_form(SLRK, r1, r2, r3); 14993b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 15003b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 15013b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// ------------------------------------ 15023b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// 64-bit Subtract Logical Instructions 15033b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// ------------------------------------ 15043b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Subtract Logical Register-Register-Register (64) 15053b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::slgrk(Register r1, Register r2, Register r3) { 15063b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rrf1_form(SLGRK, r1, r2, r3); 15073b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 15083b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 15093b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// ---------------------------- 15103b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// 32-bit Multiply Instructions 15113b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// ---------------------------- 151262ed631aa0ff23db68a47fd423efa9c019ff2c9eBen Murdoch// Multiply Halfword Immediate (32) 151362ed631aa0ff23db68a47fd423efa9c019ff2c9eBen Murdochvoid Assembler::mhi(Register r1, const Operand& opnd) { 151462ed631aa0ff23db68a47fd423efa9c019ff2c9eBen Murdoch ri_form(MHI, r1, opnd); 15153b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 15163b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 151762ed631aa0ff23db68a47fd423efa9c019ff2c9eBen Murdoch// Multiply Single Register (32) 151862ed631aa0ff23db68a47fd423efa9c019ff2c9eBen Murdochvoid Assembler::msrkc(Register r1, Register r2, Register r3) { 151962ed631aa0ff23db68a47fd423efa9c019ff2c9eBen Murdoch rrf1_form(MSRKC, r1, r2, r3); 15203b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 15213b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 152262ed631aa0ff23db68a47fd423efa9c019ff2c9eBen Murdoch// Multiply Single Register (64) 152362ed631aa0ff23db68a47fd423efa9c019ff2c9eBen Murdochvoid Assembler::msgrkc(Register r1, Register r2, Register r3) { 152462ed631aa0ff23db68a47fd423efa9c019ff2c9eBen Murdoch rrf1_form(MSGRKC, r1, r2, r3); 15253b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 15263b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 15273b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// ---------------------------- 15283b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// 64-bit Multiply Instructions 15293b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// ---------------------------- 15303b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Multiply Halfword Immediate (64) 15313b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::mghi(Register r1, const Operand& opnd) { 15323b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch ri_form(MGHI, r1, opnd); 15333b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 15343b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 15353b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// -------------------- 15363b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Bitwise Instructions 15373b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// -------------------- 15383b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// AND Register-Register-Register (32) 15393b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::nrk(Register r1, Register r2, Register r3) { 15403b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rrf1_form(NRK, r1, r2, r3); 15413b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 15423b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 15433b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// AND Register-Register-Register (64) 15443b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::ngrk(Register r1, Register r2, Register r3) { 15453b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rrf1_form(NGRK, r1, r2, r3); 15463b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 15473b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 15483b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// OR Register-Register-Register (32) 15493b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::ork(Register r1, Register r2, Register r3) { 15503b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rrf1_form(ORK, r1, r2, r3); 15513b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 15523b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 15533b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// OR Register-Register-Register (64) 15543b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::ogrk(Register r1, Register r2, Register r3) { 15553b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rrf1_form(OGRK, r1, r2, r3); 15563b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 15573b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 15583b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// XOR Register-Register-Register (32) 15593b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::xrk(Register r1, Register r2, Register r3) { 15603b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rrf1_form(XRK, r1, r2, r3); 15613b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 15623b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 15633b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// XOR Register-Register-Register (64) 15643b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::xgrk(Register r1, Register r2, Register r3) { 15653b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rrf1_form(XGRK, r1, r2, r3); 15663b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 15673b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 15683b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// XOR Storage-Storage 15693b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::xc(const MemOperand& opnd1, const MemOperand& opnd2, 15703b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch Length length) { 15713b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch ss_form(XC, length - 1, opnd1.getBaseRegister(), opnd1.getDisplacement(), 15723b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch opnd2.getBaseRegister(), opnd2.getDisplacement()); 15733b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 15743b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 15753b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::EnsureSpaceFor(int space_needed) { 15763b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch if (buffer_space() <= (kGap + space_needed)) { 15773b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch GrowBuffer(space_needed); 15783b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } 15793b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 15803b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 15813b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Rotate Left Single Logical (32) 15823b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::rll(Register r1, Register r3, Register opnd) { 15833b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(!opnd.is(r0)); 15843b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rsy_form(RLL, r1, r3, opnd, 0); 15853b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 15863b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 15873b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Rotate Left Single Logical (32) 15883b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::rll(Register r1, Register r3, const Operand& opnd) { 15893b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rsy_form(RLL, r1, r3, r0, opnd.immediate()); 15903b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 15913b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 15923b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Rotate Left Single Logical (32) 15933b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::rll(Register r1, Register r3, Register r2, 15943b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch const Operand& opnd) { 15953b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rsy_form(RLL, r1, r3, r2, opnd.immediate()); 15963b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 15973b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 15983b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Rotate Left Single Logical (64) 15993b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::rllg(Register r1, Register r3, Register opnd) { 16003b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(!opnd.is(r0)); 16013b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rsy_form(RLLG, r1, r3, opnd, 0); 16023b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 16033b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 16043b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Rotate Left Single Logical (64) 16053b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::rllg(Register r1, Register r3, const Operand& opnd) { 16063b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rsy_form(RLLG, r1, r3, r0, opnd.immediate()); 16073b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 16083b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 16093b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Rotate Left Single Logical (64) 16103b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::rllg(Register r1, Register r3, Register r2, 16113b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch const Operand& opnd) { 16123b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rsy_form(RLLG, r1, r3, r2, opnd.immediate()); 16133b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 16143b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 16153b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Shift Left Single Logical (32) 16163b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::sll(Register r1, Register opnd) { 16173b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(!opnd.is(r0)); 16183b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rs_form(SLL, r1, r0, opnd, 0); 16193b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 16203b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 16213b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Shift Left Single Logical (32) 16223b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::sll(Register r1, const Operand& opnd) { 16233b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rs_form(SLL, r1, r0, r0, opnd.immediate()); 16243b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 16253b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 16263b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Shift Left Single Logical (32) 16273b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::sllk(Register r1, Register r3, Register opnd) { 16283b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(!opnd.is(r0)); 16293b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rsy_form(SLLK, r1, r3, opnd, 0); 16303b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 16313b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 16323b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Shift Left Single Logical (32) 16333b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::sllk(Register r1, Register r3, const Operand& opnd) { 16343b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rsy_form(SLLK, r1, r3, r0, opnd.immediate()); 16353b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 16363b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 16373b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Shift Left Single Logical (64) 16383b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::sllg(Register r1, Register r3, Register opnd) { 16393b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(!opnd.is(r0)); 16403b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rsy_form(SLLG, r1, r3, opnd, 0); 16413b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 16423b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 16433b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Shift Left Single Logical (64) 16443b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::sllg(Register r1, Register r3, const Operand& opnd) { 16453b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rsy_form(SLLG, r1, r3, r0, opnd.immediate()); 16463b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 16473b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 16483b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Shift Left Double Logical (64) 16493b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::sldl(Register r1, Register b2, const Operand& opnd) { 16503b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(r1.code() % 2 == 0); 16513b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rs_form(SLDL, r1, r0, b2, opnd.immediate()); 16523b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 16533b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 16543b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Shift Right Single Logical (32) 16553b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::srl(Register r1, Register opnd) { 16563b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(!opnd.is(r0)); 16573b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rs_form(SRL, r1, r0, opnd, 0); 16583b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 16593b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 16603b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Shift Right Double Arith (64) 16613b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::srda(Register r1, Register b2, const Operand& opnd) { 16623b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(r1.code() % 2 == 0); 16633b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rs_form(SRDA, r1, r0, b2, opnd.immediate()); 16643b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 16653b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 16663b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Shift Right Double Logical (64) 16673b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::srdl(Register r1, Register b2, const Operand& opnd) { 16683b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(r1.code() % 2 == 0); 16693b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rs_form(SRDL, r1, r0, b2, opnd.immediate()); 16703b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 16713b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 16723b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Shift Right Single Logical (32) 16733b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::srl(Register r1, const Operand& opnd) { 16743b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rs_form(SRL, r1, r0, r0, opnd.immediate()); 16753b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 16763b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 16773b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Shift Right Single Logical (32) 16783b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::srlk(Register r1, Register r3, Register opnd) { 16793b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(!opnd.is(r0)); 16803b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rsy_form(SRLK, r1, r3, opnd, 0); 16813b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 16823b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 16833b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Shift Right Single Logical (32) 16843b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::srlk(Register r1, Register r3, const Operand& opnd) { 16853b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rsy_form(SRLK, r1, r3, r0, opnd.immediate()); 16863b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 16873b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 16883b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Shift Right Single Logical (64) 16893b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::srlg(Register r1, Register r3, Register opnd) { 16903b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(!opnd.is(r0)); 16913b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rsy_form(SRLG, r1, r3, opnd, 0); 16923b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 16933b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 16943b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Shift Right Single Logical (64) 16953b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::srlg(Register r1, Register r3, const Operand& opnd) { 16963b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rsy_form(SRLG, r1, r3, r0, opnd.immediate()); 16973b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 16983b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 16993b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Shift Left Single (32) 17003b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::sla(Register r1, Register opnd) { 17013b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(!opnd.is(r0)); 17023b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rs_form(SLA, r1, r0, opnd, 0); 17033b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 17043b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 17053b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Shift Left Single (32) 17063b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::sla(Register r1, const Operand& opnd) { 17073b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rs_form(SLA, r1, r0, r0, opnd.immediate()); 17083b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 17093b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 17103b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Shift Left Single (32) 17113b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::slak(Register r1, Register r3, Register opnd) { 17123b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(!opnd.is(r0)); 17133b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rsy_form(SLAK, r1, r3, opnd, 0); 17143b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 17153b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 17163b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Shift Left Single (32) 17173b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::slak(Register r1, Register r3, const Operand& opnd) { 17183b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rsy_form(SLAK, r1, r3, r0, opnd.immediate()); 17193b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 17203b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 17213b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Shift Left Single (64) 17223b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::slag(Register r1, Register r3, Register opnd) { 17233b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(!opnd.is(r0)); 17243b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rsy_form(SLAG, r1, r3, opnd, 0); 17253b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 17263b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 17273b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Shift Left Single (64) 17283b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::slag(Register r1, Register r3, const Operand& opnd) { 17293b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rsy_form(SLAG, r1, r3, r0, opnd.immediate()); 17303b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 17313b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 17323b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Shift Right Single (32) 17333b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::sra(Register r1, Register opnd) { 17343b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(!opnd.is(r0)); 17353b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rs_form(SRA, r1, r0, opnd, 0); 17363b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 17373b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 17383b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Shift Right Single (32) 17393b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::sra(Register r1, const Operand& opnd) { 17403b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rs_form(SRA, r1, r0, r0, opnd.immediate()); 17413b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 17423b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 17433b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Shift Right Single (32) 17443b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::srak(Register r1, Register r3, Register opnd) { 17453b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(!opnd.is(r0)); 17463b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rsy_form(SRAK, r1, r3, opnd, 0); 17473b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 17483b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 17493b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Shift Right Single (32) 17503b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::srak(Register r1, Register r3, const Operand& opnd) { 17513b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rsy_form(SRAK, r1, r3, r0, opnd.immediate()); 17523b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 17533b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 17543b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Shift Right Single (64) 17553b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::srag(Register r1, Register r3, Register opnd) { 17563b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(!opnd.is(r0)); 17573b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rsy_form(SRAG, r1, r3, opnd, 0); 17583b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 17593b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 17603b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::srag(Register r1, Register r3, const Operand& opnd) { 17613b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rsy_form(SRAG, r1, r3, r0, opnd.immediate()); 17623b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 17633b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 17643b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Shift Right Double 17653b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::srda(Register r1, const Operand& opnd) { 17663b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(r1.code() % 2 == 0); 17673b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rs_form(SRDA, r1, r0, r0, opnd.immediate()); 17683b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 17693b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 17703b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Shift Right Double Logical 17713b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::srdl(Register r1, const Operand& opnd) { 17723b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(r1.code() % 2 == 0); 17733b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rs_form(SRDL, r1, r0, r0, opnd.immediate()); 17743b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 17753b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 17763b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::call(Handle<Code> target, RelocInfo::Mode rmode, 17773b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch TypeFeedbackId ast_id) { 17783b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch EnsureSpace ensure_space(this); 17793b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 17803b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch int32_t target_index = emit_code_target(target, rmode, ast_id); 17813b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch brasl(r14, Operand(target_index)); 17823b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 17833b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 17843b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::jump(Handle<Code> target, RelocInfo::Mode rmode, 17853b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch Condition cond) { 17863b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch EnsureSpace ensure_space(this); 17873b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 17883b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch int32_t target_index = emit_code_target(target, rmode); 178962ed631aa0ff23db68a47fd423efa9c019ff2c9eBen Murdoch brcl(cond, Operand(target_index)); 17903b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 17913b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 17923b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// 32-bit Load Multiple - short displacement (12-bits unsigned) 17933b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::lm(Register r1, Register r2, const MemOperand& src) { 17943b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rs_form(LM, r1, r2, src.rb(), src.offset()); 17953b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 17963b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 17973b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// 32-bit Load Multiple - long displacement (20-bits signed) 17983b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::lmy(Register r1, Register r2, const MemOperand& src) { 17993b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rsy_form(LMY, r1, r2, src.rb(), src.offset()); 18003b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 18013b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 18023b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// 64-bit Load Multiple - long displacement (20-bits signed) 18033b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::lmg(Register r1, Register r2, const MemOperand& src) { 18043b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rsy_form(LMG, r1, r2, src.rb(), src.offset()); 18053b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 18063b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 18073b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Move integer (32) 18083b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::mvhi(const MemOperand& opnd1, const Operand& i2) { 18093b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch sil_form(MVHI, opnd1.getBaseRegister(), opnd1.getDisplacement(), i2); 18103b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 18113b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 18123b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Move integer (64) 18133b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::mvghi(const MemOperand& opnd1, const Operand& i2) { 18143b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch sil_form(MVGHI, opnd1.getBaseRegister(), opnd1.getDisplacement(), i2); 18153b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 18163b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 18173b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Insert Immediate (high high) 18183b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::iihh(Register r1, const Operand& opnd) { 18193b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch ri_form(IIHH, r1, opnd); 18203b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 18213b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 18223b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Insert Immediate (high low) 18233b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::iihl(Register r1, const Operand& opnd) { 18243b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch ri_form(IIHL, r1, opnd); 18253b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 18263b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 18273b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Insert Immediate (low high) 18283b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::iilh(Register r1, const Operand& opnd) { 18293b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch ri_form(IILH, r1, opnd); 18303b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 18313b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 18323b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Insert Immediate (low low) 18333b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::iill(Register r1, const Operand& opnd) { 18343b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch ri_form(IILL, r1, opnd); 18353b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 18363b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 18373b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// GPR <-> FPR Instructions 18383b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 18393b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Floating point instructions 18403b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// 18413b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Add Register-Storage (LB) 18423b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::adb(DoubleRegister r1, const MemOperand& opnd) { 18433b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rxe_form(ADB, Register::from_code(r1.code()), opnd.rx(), opnd.rb(), 18443b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch opnd.offset()); 18453b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 18463b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 18473b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Divide Register-Storage (LB) 18483b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::ddb(DoubleRegister r1, const MemOperand& opnd) { 18493b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rxe_form(DDB, Register::from_code(r1.code()), opnd.rx(), opnd.rb(), 18503b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch opnd.offset()); 18513b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 18523b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 18533b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Multiply Register-Storage (LB) 18543b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::mdb(DoubleRegister r1, const MemOperand& opnd) { 18553b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rxe_form(MDB, Register::from_code(r1.code()), opnd.rb(), opnd.rx(), 18563b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch opnd.offset()); 18573b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 18583b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 18593b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Subtract Register-Storage (LB) 18603b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::sdb(DoubleRegister r1, const MemOperand& opnd) { 18613b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rxe_form(SDB, Register::from_code(r1.code()), opnd.rx(), opnd.rb(), 18623b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch opnd.offset()); 18633b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 18643b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 186562ed631aa0ff23db68a47fd423efa9c019ff2c9eBen Murdochvoid Assembler::ceb(DoubleRegister r1, const MemOperand& opnd) { 186662ed631aa0ff23db68a47fd423efa9c019ff2c9eBen Murdoch rxe_form(CEB, Register::from_code(r1.code()), opnd.rx(), opnd.rb(), 186762ed631aa0ff23db68a47fd423efa9c019ff2c9eBen Murdoch opnd.offset()); 186862ed631aa0ff23db68a47fd423efa9c019ff2c9eBen Murdoch} 186962ed631aa0ff23db68a47fd423efa9c019ff2c9eBen Murdoch 187062ed631aa0ff23db68a47fd423efa9c019ff2c9eBen Murdochvoid Assembler::cdb(DoubleRegister r1, const MemOperand& opnd) { 187162ed631aa0ff23db68a47fd423efa9c019ff2c9eBen Murdoch rxe_form(CDB, Register::from_code(r1.code()), opnd.rx(), opnd.rb(), 187262ed631aa0ff23db68a47fd423efa9c019ff2c9eBen Murdoch opnd.offset()); 18733b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 18743b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 18753b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Square Root (LB) 18763b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::sqdb(DoubleRegister r1, const MemOperand& opnd) { 18773b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rxe_form(SQDB, Register::from_code(r1.code()), opnd.rx(), opnd.rb(), 18783b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch opnd.offset()); 18793b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 18803b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 18813b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Convert to Fixed point (64<-S) 18823b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::cgebr(Condition m, Register r1, DoubleRegister r2) { 18833b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rrfe_form(CGEBR, m, Condition(0), r1, Register::from_code(r2.code())); 18843b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 18853b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 18863b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Convert to Fixed point (64<-L) 18873b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::cgdbr(Condition m, Register r1, DoubleRegister r2) { 18883b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rrfe_form(CGDBR, m, Condition(0), r1, Register::from_code(r2.code())); 18893b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 18903b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 18913b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Convert to Fixed point (32<-L) 18923b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::cfdbr(Condition m, Register r1, DoubleRegister r2) { 18933b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rrfe_form(CFDBR, m, Condition(0), r1, Register::from_code(r2.code())); 18943b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 18953b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 18963b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Convert to Fixed Logical (64<-L) 18973b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::clgdbr(Condition m3, Condition m4, Register r1, 18983b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DoubleRegister r2) { 18993b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK_EQ(m4, Condition(0)); 19003b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rrfe_form(CLGDBR, m3, m4, r1, Register::from_code(r2.code())); 19013b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 19023b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 19033b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Convert to Fixed Logical (64<-F32) 19043b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::clgebr(Condition m3, Condition m4, Register r1, 19053b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DoubleRegister r2) { 19063b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK_EQ(m4, Condition(0)); 19073b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rrfe_form(CLGEBR, m3, m4, r1, Register::from_code(r2.code())); 19083b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 19093b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 19103b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Convert to Fixed Logical (32<-F64) 19113b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::clfdbr(Condition m3, Condition m4, Register r1, 19123b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DoubleRegister r2) { 19133b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK_EQ(m3, Condition(0)); 19143b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK_EQ(m4, Condition(0)); 19153b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rrfe_form(CLFDBR, Condition(0), Condition(0), r1, 19163b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch Register::from_code(r2.code())); 19173b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 19183b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 19193b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Convert to Fixed Logical (32<-F32) 19203b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::clfebr(Condition m3, Condition m4, Register r1, 19213b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DoubleRegister r2) { 19223b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK_EQ(m4, Condition(0)); 19233b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rrfe_form(CLFEBR, m3, Condition(0), r1, Register::from_code(r2.code())); 19243b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 19253b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 19263b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Convert from Fixed Logical (L<-64) 19273b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::celgbr(Condition m3, Condition m4, DoubleRegister r1, 19283b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch Register r2) { 19293b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK_EQ(m3, Condition(0)); 19303b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK_EQ(m4, Condition(0)); 19313b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rrfe_form(CELGBR, Condition(0), Condition(0), Register::from_code(r1.code()), 19323b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch r2); 19333b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 19343b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 19353b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Convert from Fixed Logical (F32<-32) 19363b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::celfbr(Condition m3, Condition m4, DoubleRegister r1, 19373b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch Register r2) { 19383b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK_EQ(m4, Condition(0)); 1939f91f0611dbaf29ca0f1d4aecb357ce243a19d2faBen Murdoch rrfe_form(CELFBR, m3, Condition(0), Register::from_code(r1.code()), r2); 19403b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 19413b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 19423b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Convert from Fixed Logical (L<-64) 19433b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::cdlgbr(Condition m3, Condition m4, DoubleRegister r1, 19443b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch Register r2) { 19453b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK_EQ(m3, Condition(0)); 19463b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK_EQ(m4, Condition(0)); 19473b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rrfe_form(CDLGBR, Condition(0), Condition(0), Register::from_code(r1.code()), 19483b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch r2); 19493b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 19503b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 19513b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Convert from Fixed Logical (L<-32) 19523b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::cdlfbr(Condition m3, Condition m4, DoubleRegister r1, 19533b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch Register r2) { 19543b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK_EQ(m4, Condition(0)); 19553b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rrfe_form(CDLFBR, m3, Condition(0), Register::from_code(r1.code()), r2); 19563b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 19573b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 19583b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Convert from Fixed point (S<-32) 1959f91f0611dbaf29ca0f1d4aecb357ce243a19d2faBen Murdochvoid Assembler::cefbr(Condition m3, DoubleRegister r1, Register r2) { 1960f91f0611dbaf29ca0f1d4aecb357ce243a19d2faBen Murdoch rrfe_form(CEFBR, m3, Condition(0), Register::from_code(r1.code()), r2); 19613b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 19623b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 19633b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Convert to Fixed point (32<-S) 19643b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::cfebr(Condition m3, Register r1, DoubleRegister r2) { 19653b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rrfe_form(CFEBR, m3, Condition(0), r1, Register::from_code(r2.code())); 19663b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 19673b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 19683b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Load (L <- S) 19693b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::ldeb(DoubleRegister d1, const MemOperand& opnd) { 19703b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rxe_form(LDEB, Register::from_code(d1.code()), opnd.rx(), opnd.rb(), 19713b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch opnd.offset()); 19723b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 19733b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 19743b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Load FP Integer 19753b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::fiebra(DoubleRegister d1, DoubleRegister d2, FIDBRA_MASK3 m3) { 19763b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rrf2_form(FIEBRA << 16 | m3 * B12 | d1.code() * B4 | d2.code()); 19773b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 19783b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 19793b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// Load FP Integer 19803b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::fidbra(DoubleRegister d1, DoubleRegister d2, FIDBRA_MASK3 m3) { 19813b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch rrf2_form(FIDBRA << 16 | m3 * B12 | d1.code() * B4 | d2.code()); 19823b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 19833b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 19843b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch// end of S390instructions 19853b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 19863b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochbool Assembler::IsNop(SixByteInstr instr, int type) { 19873b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK((0 == type) || (DEBUG_BREAK_NOP == type)); 19883b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch if (DEBUG_BREAK_NOP == type) { 19893b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch return ((instr & 0xffffffff) == 0xa53b0000); // oill r3, 0 19903b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } 19913b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch return ((instr & 0xffff) == 0x1800); // lr r0,r0 19923b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 19933b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 199462ed631aa0ff23db68a47fd423efa9c019ff2c9eBen Murdoch// dummy instruction reserved for special use. 199562ed631aa0ff23db68a47fd423efa9c019ff2c9eBen Murdochvoid Assembler::dumy(int r1, int x2, int b2, int d2) { 199662ed631aa0ff23db68a47fd423efa9c019ff2c9eBen Murdoch#if defined(USE_SIMULATOR) 199762ed631aa0ff23db68a47fd423efa9c019ff2c9eBen Murdoch int op = 0xE353; 199862ed631aa0ff23db68a47fd423efa9c019ff2c9eBen Murdoch uint64_t code = (static_cast<uint64_t>(op & 0xFF00)) * B32 | 199962ed631aa0ff23db68a47fd423efa9c019ff2c9eBen Murdoch (static_cast<uint64_t>(r1) & 0xF) * B36 | 200062ed631aa0ff23db68a47fd423efa9c019ff2c9eBen Murdoch (static_cast<uint64_t>(x2) & 0xF) * B32 | 200162ed631aa0ff23db68a47fd423efa9c019ff2c9eBen Murdoch (static_cast<uint64_t>(b2) & 0xF) * B28 | 200262ed631aa0ff23db68a47fd423efa9c019ff2c9eBen Murdoch (static_cast<uint64_t>(d2 & 0x0FFF)) * B16 | 200362ed631aa0ff23db68a47fd423efa9c019ff2c9eBen Murdoch (static_cast<uint64_t>(d2 & 0x0FF000)) >> 4 | 200462ed631aa0ff23db68a47fd423efa9c019ff2c9eBen Murdoch (static_cast<uint64_t>(op & 0x00FF)); 200562ed631aa0ff23db68a47fd423efa9c019ff2c9eBen Murdoch emit6bytes(code); 200662ed631aa0ff23db68a47fd423efa9c019ff2c9eBen Murdoch#endif 200762ed631aa0ff23db68a47fd423efa9c019ff2c9eBen Murdoch} 200862ed631aa0ff23db68a47fd423efa9c019ff2c9eBen Murdoch 20093b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::GrowBuffer(int needed) { 20103b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch if (!own_buffer_) FATAL("external code buffer is too small"); 20113b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 20123b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch // Compute new buffer size. 20133b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch CodeDesc desc; // the new buffer 20143b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch if (buffer_size_ < 4 * KB) { 20153b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch desc.buffer_size = 4 * KB; 20163b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } else if (buffer_size_ < 1 * MB) { 20173b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch desc.buffer_size = 2 * buffer_size_; 20183b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } else { 20193b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch desc.buffer_size = buffer_size_ + 1 * MB; 20203b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } 20213b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch int space = buffer_space() + (desc.buffer_size - buffer_size_); 20223b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch if (space < needed) { 20233b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch desc.buffer_size += needed - space; 20243b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } 20253b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch CHECK_GT(desc.buffer_size, 0); // no overflow 20263b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 20273b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch // Set up new buffer. 20283b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch desc.buffer = NewArray<byte>(desc.buffer_size); 20293b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch desc.origin = this; 20303b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 20313b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch desc.instr_size = pc_offset(); 20323b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch desc.reloc_size = (buffer_ + buffer_size_) - reloc_info_writer.pos(); 20333b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 20343b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch // Copy the data. 20353b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch intptr_t pc_delta = desc.buffer - buffer_; 20363b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch intptr_t rc_delta = 20373b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (desc.buffer + desc.buffer_size) - (buffer_ + buffer_size_); 20383b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch memmove(desc.buffer, buffer_, desc.instr_size); 20393b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch memmove(reloc_info_writer.pos() + rc_delta, reloc_info_writer.pos(), 20403b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch desc.reloc_size); 20413b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 20423b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch // Switch buffers. 20433b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DeleteArray(buffer_); 20443b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch buffer_ = desc.buffer; 20453b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch buffer_size_ = desc.buffer_size; 20463b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch pc_ += pc_delta; 20473b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch reloc_info_writer.Reposition(reloc_info_writer.pos() + rc_delta, 20483b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch reloc_info_writer.last_pc() + pc_delta); 20493b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 20503b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch // None of our relocation types are pc relative pointing outside the code 20513b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch // buffer nor pc absolute pointing inside the code buffer, so there is no need 20523b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch // to relocate any emitted relocation entries. 20533b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 20543b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 20553b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::db(uint8_t data) { 20563b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch CheckBuffer(); 20573b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch *reinterpret_cast<uint8_t*>(pc_) = data; 20583b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch pc_ += sizeof(uint8_t); 20593b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 20603b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 20613b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::dd(uint32_t data) { 20623b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch CheckBuffer(); 20633b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch *reinterpret_cast<uint32_t*>(pc_) = data; 20643b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch pc_ += sizeof(uint32_t); 20653b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 20663b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 20673b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::dq(uint64_t value) { 20683b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch CheckBuffer(); 20693b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch *reinterpret_cast<uint64_t*>(pc_) = value; 20703b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch pc_ += sizeof(uint64_t); 20713b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 20723b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 20733b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::dp(uintptr_t data) { 20743b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch CheckBuffer(); 20753b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch *reinterpret_cast<uintptr_t*>(pc_) = data; 20763b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch pc_ += sizeof(uintptr_t); 20773b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 20783b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 20793b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data) { 20803b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch if (RelocInfo::IsNone(rmode) || 20813b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch // Don't record external references unless the heap will be serialized. 20823b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch (rmode == RelocInfo::EXTERNAL_REFERENCE && !serializer_enabled() && 20833b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch !emit_debug_code())) { 20843b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch return; 20853b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } 20863b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch if (rmode == RelocInfo::CODE_TARGET_WITH_ID) { 20873b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch data = RecordedAstId().ToInt(); 20883b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch ClearRecordedAstId(); 20893b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } 20903b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DeferredRelocInfo rinfo(pc_offset(), rmode, data); 20913b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch relocations_.push_back(rinfo); 20923b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 20933b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 20943b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::emit_label_addr(Label* label) { 20953b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch CheckBuffer(); 20963b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch RecordRelocInfo(RelocInfo::INTERNAL_REFERENCE); 20973b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch int position = link(label); 20983b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch DCHECK(label->is_bound()); 20993b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch // Keep internal references relative until EmitRelocations. 21003b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch dp(position); 21013b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 21023b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 21033b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdochvoid Assembler::EmitRelocations() { 21043b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch EnsureSpaceFor(relocations_.size() * kMaxRelocSize); 21053b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 21063b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch for (std::vector<DeferredRelocInfo>::iterator it = relocations_.begin(); 21073b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch it != relocations_.end(); it++) { 21083b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch RelocInfo::Mode rmode = it->rmode(); 21093b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch Address pc = buffer_ + it->position(); 21103b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch Code* code = NULL; 21113b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch RelocInfo rinfo(isolate(), pc, rmode, it->data(), code); 21123b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 21133b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch // Fix up internal references now that they are guaranteed to be bound. 21143b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch if (RelocInfo::IsInternalReference(rmode)) { 21153b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch // Jump table entry 21163b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch intptr_t pos = reinterpret_cast<intptr_t>(Memory::Address_at(pc)); 21173b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch Memory::Address_at(pc) = buffer_ + pos; 21183b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } else if (RelocInfo::IsInternalReferenceEncoded(rmode)) { 21193b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch // mov sequence 21203b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch intptr_t pos = reinterpret_cast<intptr_t>(target_address_at(pc, code)); 21213b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch set_target_address_at(isolate(), pc, code, buffer_ + pos, 21223b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch SKIP_ICACHE_FLUSH); 21233b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } 21243b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 21253b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch reloc_info_writer.Write(&rinfo); 21263b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch } 21273b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} 21283b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch 21293b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} // namespace internal 21303b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch} // namespace v8 21313b9bc31999c9787eb726ecdbfd5796bfdec32a18Ben Murdoch#endif // V8_TARGET_ARCH_S390 2132