assembler-x64.h revision 257744e915dfc84d6d07a6b2accf8402d9ffc708
1// Copyright (c) 1994-2006 Sun Microsystems Inc. 2// All Rights Reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: 7// 8// - Redistributions of source code must retain the above copyright notice, 9// this list of conditions and the following disclaimer. 10// 11// - Redistribution in binary form must reproduce the above copyright 12// notice, this list of conditions and the following disclaimer in the 13// documentation and/or other materials provided with the distribution. 14// 15// - Neither the name of Sun Microsystems or the names of contributors may 16// be used to endorse or promote products derived from this software without 17// specific prior written permission. 18// 19// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 20// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 23// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 24// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 25// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 26// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 27// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 28// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 29// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 31// The original source code covered by the above license above has been 32// modified significantly by Google Inc. 33// Copyright 2011 the V8 project authors. All rights reserved. 34 35// A lightweight X64 Assembler. 36 37#ifndef V8_X64_ASSEMBLER_X64_H_ 38#define V8_X64_ASSEMBLER_X64_H_ 39 40#include "serialize.h" 41 42namespace v8 { 43namespace internal { 44 45// Utility functions 46 47// Test whether a 64-bit value is in a specific range. 48static inline bool is_uint32(int64_t x) { 49 static const uint64_t kMaxUInt32 = V8_UINT64_C(0xffffffff); 50 return static_cast<uint64_t>(x) <= kMaxUInt32; 51} 52 53static inline bool is_int32(int64_t x) { 54 static const int64_t kMinInt32 = -V8_INT64_C(0x80000000); 55 return is_uint32(x - kMinInt32); 56} 57 58static inline bool uint_is_int32(uint64_t x) { 59 static const uint64_t kMaxInt32 = V8_UINT64_C(0x7fffffff); 60 return x <= kMaxInt32; 61} 62 63static inline bool is_uint32(uint64_t x) { 64 static const uint64_t kMaxUInt32 = V8_UINT64_C(0xffffffff); 65 return x <= kMaxUInt32; 66} 67 68// CPU Registers. 69// 70// 1) We would prefer to use an enum, but enum values are assignment- 71// compatible with int, which has caused code-generation bugs. 72// 73// 2) We would prefer to use a class instead of a struct but we don't like 74// the register initialization to depend on the particular initialization 75// order (which appears to be different on OS X, Linux, and Windows for the 76// installed versions of C++ we tried). Using a struct permits C-style 77// "initialization". Also, the Register objects cannot be const as this 78// forces initialization stubs in MSVC, making us dependent on initialization 79// order. 80// 81// 3) By not using an enum, we are possibly preventing the compiler from 82// doing certain constant folds, which may significantly reduce the 83// code generated for some assembly instructions (because they boil down 84// to a few constants). If this is a problem, we could change the code 85// such that we use an enum in optimized mode, and the struct in debug 86// mode. This way we get the compile-time error checking in debug mode 87// and best performance in optimized code. 88// 89 90struct Register { 91 // The non-allocatable registers are: 92 // rsp - stack pointer 93 // rbp - frame pointer 94 // rsi - context register 95 // r10 - fixed scratch register 96 // r12 - smi constant register 97 // r13 - root register 98 static const int kNumRegisters = 16; 99 static const int kNumAllocatableRegisters = 10; 100 101 static int ToAllocationIndex(Register reg) { 102 return kAllocationIndexByRegisterCode[reg.code()]; 103 } 104 105 static Register FromAllocationIndex(int index) { 106 ASSERT(index >= 0 && index < kNumAllocatableRegisters); 107 Register result = { kRegisterCodeByAllocationIndex[index] }; 108 return result; 109 } 110 111 static const char* AllocationIndexToString(int index) { 112 ASSERT(index >= 0 && index < kNumAllocatableRegisters); 113 const char* const names[] = { 114 "rax", 115 "rbx", 116 "rdx", 117 "rcx", 118 "rdi", 119 "r8", 120 "r9", 121 "r11", 122 "r14", 123 "r15" 124 }; 125 return names[index]; 126 } 127 128 static Register toRegister(int code) { 129 Register r = { code }; 130 return r; 131 } 132 bool is_valid() const { return 0 <= code_ && code_ < kNumRegisters; } 133 bool is(Register reg) const { return code_ == reg.code_; } 134 int code() const { 135 ASSERT(is_valid()); 136 return code_; 137 } 138 int bit() const { 139 return 1 << code_; 140 } 141 142 // Return the high bit of the register code as a 0 or 1. Used often 143 // when constructing the REX prefix byte. 144 int high_bit() const { 145 return code_ >> 3; 146 } 147 // Return the 3 low bits of the register code. Used when encoding registers 148 // in modR/M, SIB, and opcode bytes. 149 int low_bits() const { 150 return code_ & 0x7; 151 } 152 153 // Unfortunately we can't make this private in a struct when initializing 154 // by assignment. 155 int code_; 156 157 private: 158 static const int kRegisterCodeByAllocationIndex[kNumAllocatableRegisters]; 159 static const int kAllocationIndexByRegisterCode[kNumRegisters]; 160}; 161 162const Register rax = { 0 }; 163const Register rcx = { 1 }; 164const Register rdx = { 2 }; 165const Register rbx = { 3 }; 166const Register rsp = { 4 }; 167const Register rbp = { 5 }; 168const Register rsi = { 6 }; 169const Register rdi = { 7 }; 170const Register r8 = { 8 }; 171const Register r9 = { 9 }; 172const Register r10 = { 10 }; 173const Register r11 = { 11 }; 174const Register r12 = { 12 }; 175const Register r13 = { 13 }; 176const Register r14 = { 14 }; 177const Register r15 = { 15 }; 178const Register no_reg = { -1 }; 179 180 181struct XMMRegister { 182 static const int kNumRegisters = 16; 183 static const int kNumAllocatableRegisters = 15; 184 185 static int ToAllocationIndex(XMMRegister reg) { 186 ASSERT(reg.code() != 0); 187 return reg.code() - 1; 188 } 189 190 static XMMRegister FromAllocationIndex(int index) { 191 ASSERT(0 <= index && index < kNumAllocatableRegisters); 192 XMMRegister result = { index + 1 }; 193 return result; 194 } 195 196 static const char* AllocationIndexToString(int index) { 197 ASSERT(index >= 0 && index < kNumAllocatableRegisters); 198 const char* const names[] = { 199 "xmm1", 200 "xmm2", 201 "xmm3", 202 "xmm4", 203 "xmm5", 204 "xmm6", 205 "xmm7", 206 "xmm8", 207 "xmm9", 208 "xmm10", 209 "xmm11", 210 "xmm12", 211 "xmm13", 212 "xmm14", 213 "xmm15" 214 }; 215 return names[index]; 216 } 217 218 bool is_valid() const { return 0 <= code_ && code_ < kNumRegisters; } 219 bool is(XMMRegister reg) const { return code_ == reg.code_; } 220 int code() const { 221 ASSERT(is_valid()); 222 return code_; 223 } 224 225 // Return the high bit of the register code as a 0 or 1. Used often 226 // when constructing the REX prefix byte. 227 int high_bit() const { 228 return code_ >> 3; 229 } 230 // Return the 3 low bits of the register code. Used when encoding registers 231 // in modR/M, SIB, and opcode bytes. 232 int low_bits() const { 233 return code_ & 0x7; 234 } 235 236 int code_; 237}; 238 239const XMMRegister xmm0 = { 0 }; 240const XMMRegister xmm1 = { 1 }; 241const XMMRegister xmm2 = { 2 }; 242const XMMRegister xmm3 = { 3 }; 243const XMMRegister xmm4 = { 4 }; 244const XMMRegister xmm5 = { 5 }; 245const XMMRegister xmm6 = { 6 }; 246const XMMRegister xmm7 = { 7 }; 247const XMMRegister xmm8 = { 8 }; 248const XMMRegister xmm9 = { 9 }; 249const XMMRegister xmm10 = { 10 }; 250const XMMRegister xmm11 = { 11 }; 251const XMMRegister xmm12 = { 12 }; 252const XMMRegister xmm13 = { 13 }; 253const XMMRegister xmm14 = { 14 }; 254const XMMRegister xmm15 = { 15 }; 255 256 257typedef XMMRegister DoubleRegister; 258 259 260enum Condition { 261 // any value < 0 is considered no_condition 262 no_condition = -1, 263 264 overflow = 0, 265 no_overflow = 1, 266 below = 2, 267 above_equal = 3, 268 equal = 4, 269 not_equal = 5, 270 below_equal = 6, 271 above = 7, 272 negative = 8, 273 positive = 9, 274 parity_even = 10, 275 parity_odd = 11, 276 less = 12, 277 greater_equal = 13, 278 less_equal = 14, 279 greater = 15, 280 281 // Fake conditions that are handled by the 282 // opcodes using them. 283 always = 16, 284 never = 17, 285 // aliases 286 carry = below, 287 not_carry = above_equal, 288 zero = equal, 289 not_zero = not_equal, 290 sign = negative, 291 not_sign = positive, 292 last_condition = greater 293}; 294 295 296// Returns the equivalent of !cc. 297// Negation of the default no_condition (-1) results in a non-default 298// no_condition value (-2). As long as tests for no_condition check 299// for condition < 0, this will work as expected. 300inline Condition NegateCondition(Condition cc) { 301 return static_cast<Condition>(cc ^ 1); 302} 303 304 305// Corresponds to transposing the operands of a comparison. 306inline Condition ReverseCondition(Condition cc) { 307 switch (cc) { 308 case below: 309 return above; 310 case above: 311 return below; 312 case above_equal: 313 return below_equal; 314 case below_equal: 315 return above_equal; 316 case less: 317 return greater; 318 case greater: 319 return less; 320 case greater_equal: 321 return less_equal; 322 case less_equal: 323 return greater_equal; 324 default: 325 return cc; 326 }; 327} 328 329 330// ----------------------------------------------------------------------------- 331// Machine instruction Immediates 332 333class Immediate BASE_EMBEDDED { 334 public: 335 explicit Immediate(int32_t value) : value_(value) {} 336 337 private: 338 int32_t value_; 339 340 friend class Assembler; 341}; 342 343 344// ----------------------------------------------------------------------------- 345// Machine instruction Operands 346 347enum ScaleFactor { 348 times_1 = 0, 349 times_2 = 1, 350 times_4 = 2, 351 times_8 = 3, 352 times_int_size = times_4, 353 times_pointer_size = times_8 354}; 355 356 357class Operand BASE_EMBEDDED { 358 public: 359 // [base + disp/r] 360 Operand(Register base, int32_t disp); 361 362 // [base + index*scale + disp/r] 363 Operand(Register base, 364 Register index, 365 ScaleFactor scale, 366 int32_t disp); 367 368 // [index*scale + disp/r] 369 Operand(Register index, 370 ScaleFactor scale, 371 int32_t disp); 372 373 // Offset from existing memory operand. 374 // Offset is added to existing displacement as 32-bit signed values and 375 // this must not overflow. 376 Operand(const Operand& base, int32_t offset); 377 378 // Checks whether either base or index register is the given register. 379 // Does not check the "reg" part of the Operand. 380 bool AddressUsesRegister(Register reg) const; 381 382 // Queries related to the size of the generated instruction. 383 // Whether the generated instruction will have a REX prefix. 384 bool requires_rex() const { return rex_ != 0; } 385 // Size of the ModR/M, SIB and displacement parts of the generated 386 // instruction. 387 int operand_size() const { return len_; } 388 389 private: 390 byte rex_; 391 byte buf_[6]; 392 // The number of bytes of buf_ in use. 393 byte len_; 394 395 // Set the ModR/M byte without an encoded 'reg' register. The 396 // register is encoded later as part of the emit_operand operation. 397 // set_modrm can be called before or after set_sib and set_disp*. 398 inline void set_modrm(int mod, Register rm); 399 400 // Set the SIB byte if one is needed. Sets the length to 2 rather than 1. 401 inline void set_sib(ScaleFactor scale, Register index, Register base); 402 403 // Adds operand displacement fields (offsets added to the memory address). 404 // Needs to be called after set_sib, not before it. 405 inline void set_disp8(int disp); 406 inline void set_disp32(int disp); 407 408 friend class Assembler; 409}; 410 411 412// CpuFeatures keeps track of which features are supported by the target CPU. 413// Supported features must be enabled by a Scope before use. 414// Example: 415// if (CpuFeatures::IsSupported(SSE3)) { 416// CpuFeatures::Scope fscope(SSE3); 417// // Generate SSE3 floating point code. 418// } else { 419// // Generate standard x87 or SSE2 floating point code. 420// } 421class CpuFeatures : public AllStatic { 422 public: 423 // Detect features of the target CPU. Set safe defaults if the serializer 424 // is enabled (snapshots must be portable). 425 static void Probe(); 426 427 // Check whether a feature is supported by the target CPU. 428 static bool IsSupported(CpuFeature f) { 429 ASSERT(initialized_); 430 if (f == SSE2 && !FLAG_enable_sse2) return false; 431 if (f == SSE3 && !FLAG_enable_sse3) return false; 432 if (f == CMOV && !FLAG_enable_cmov) return false; 433 if (f == RDTSC && !FLAG_enable_rdtsc) return false; 434 if (f == SAHF && !FLAG_enable_sahf) return false; 435 return (supported_ & (V8_UINT64_C(1) << f)) != 0; 436 } 437 438#ifdef DEBUG 439 // Check whether a feature is currently enabled. 440 static bool IsEnabled(CpuFeature f) { 441 ASSERT(initialized_); 442 Isolate* isolate = Isolate::UncheckedCurrent(); 443 if (isolate == NULL) { 444 // When no isolate is available, work as if we're running in 445 // release mode. 446 return IsSupported(f); 447 } 448 uint64_t enabled = isolate->enabled_cpu_features(); 449 return (enabled & (V8_UINT64_C(1) << f)) != 0; 450 } 451#endif 452 453 // Enable a specified feature within a scope. 454 class Scope BASE_EMBEDDED { 455#ifdef DEBUG 456 public: 457 explicit Scope(CpuFeature f) { 458 uint64_t mask = V8_UINT64_C(1) << f; 459 ASSERT(CpuFeatures::IsSupported(f)); 460 ASSERT(!Serializer::enabled() || 461 (CpuFeatures::found_by_runtime_probing_ & mask) == 0); 462 isolate_ = Isolate::UncheckedCurrent(); 463 old_enabled_ = 0; 464 if (isolate_ != NULL) { 465 old_enabled_ = isolate_->enabled_cpu_features(); 466 isolate_->set_enabled_cpu_features(old_enabled_ | mask); 467 } 468 } 469 ~Scope() { 470 ASSERT_EQ(Isolate::UncheckedCurrent(), isolate_); 471 if (isolate_ != NULL) { 472 isolate_->set_enabled_cpu_features(old_enabled_); 473 } 474 } 475 private: 476 Isolate* isolate_; 477 uint64_t old_enabled_; 478#else 479 public: 480 explicit Scope(CpuFeature f) {} 481#endif 482 }; 483 484 private: 485 // Safe defaults include SSE2 and CMOV for X64. It is always available, if 486 // anyone checks, but they shouldn't need to check. 487 // The required user mode extensions in X64 are (from AMD64 ABI Table A.1): 488 // fpu, tsc, cx8, cmov, mmx, sse, sse2, fxsr, syscall 489 static const uint64_t kDefaultCpuFeatures = (1 << SSE2 | 1 << CMOV); 490 491#ifdef DEBUG 492 static bool initialized_; 493#endif 494 static uint64_t supported_; 495 static uint64_t found_by_runtime_probing_; 496 497 DISALLOW_COPY_AND_ASSIGN(CpuFeatures); 498}; 499 500 501class Assembler : public AssemblerBase { 502 private: 503 // We check before assembling an instruction that there is sufficient 504 // space to write an instruction and its relocation information. 505 // The relocation writer's position must be kGap bytes above the end of 506 // the generated instructions. This leaves enough space for the 507 // longest possible x64 instruction, 15 bytes, and the longest possible 508 // relocation information encoding, RelocInfoWriter::kMaxLength == 16. 509 // (There is a 15 byte limit on x64 instruction length that rules out some 510 // otherwise valid instructions.) 511 // This allows for a single, fast space check per instruction. 512 static const int kGap = 32; 513 514 public: 515 // Create an assembler. Instructions and relocation information are emitted 516 // into a buffer, with the instructions starting from the beginning and the 517 // relocation information starting from the end of the buffer. See CodeDesc 518 // for a detailed comment on the layout (globals.h). 519 // 520 // If the provided buffer is NULL, the assembler allocates and grows its own 521 // buffer, and buffer_size determines the initial buffer size. The buffer is 522 // owned by the assembler and deallocated upon destruction of the assembler. 523 // 524 // If the provided buffer is not NULL, the assembler uses the provided buffer 525 // for code generation and assumes its size to be buffer_size. If the buffer 526 // is too small, a fatal error occurs. No deallocation of the buffer is done 527 // upon destruction of the assembler. 528 Assembler(Isolate* isolate, void* buffer, int buffer_size); 529 ~Assembler(); 530 531 // Overrides the default provided by FLAG_debug_code. 532 void set_emit_debug_code(bool value) { emit_debug_code_ = value; } 533 534 // GetCode emits any pending (non-emitted) code and fills the descriptor 535 // desc. GetCode() is idempotent; it returns the same result if no other 536 // Assembler functions are invoked in between GetCode() calls. 537 void GetCode(CodeDesc* desc); 538 539 // Read/Modify the code target in the relative branch/call instruction at pc. 540 // On the x64 architecture, we use relative jumps with a 32-bit displacement 541 // to jump to other Code objects in the Code space in the heap. 542 // Jumps to C functions are done indirectly through a 64-bit register holding 543 // the absolute address of the target. 544 // These functions convert between absolute Addresses of Code objects and 545 // the relative displacements stored in the code. 546 static inline Address target_address_at(Address pc); 547 static inline void set_target_address_at(Address pc, Address target); 548 549 // This sets the branch destination (which is in the instruction on x64). 550 // This is for calls and branches within generated code. 551 inline static void set_target_at(Address instruction_payload, 552 Address target) { 553 set_target_address_at(instruction_payload, target); 554 } 555 556 // This sets the branch destination (which is a load instruction on x64). 557 // This is for calls and branches to runtime code. 558 inline static void set_external_target_at(Address instruction_payload, 559 Address target) { 560 *reinterpret_cast<Address*>(instruction_payload) = target; 561 } 562 563 inline Handle<Object> code_target_object_handle_at(Address pc); 564 // Number of bytes taken up by the branch target in the code. 565 static const int kCallTargetSize = 4; // Use 32-bit displacement. 566 static const int kExternalTargetSize = 8; // Use 64-bit absolute. 567 // Distance between the address of the code target in the call instruction 568 // and the return address pushed on the stack. 569 static const int kCallTargetAddressOffset = 4; // Use 32-bit displacement. 570 // Distance between the start of the JS return sequence and where the 571 // 32-bit displacement of a near call would be, relative to the pushed 572 // return address. TODO: Use return sequence length instead. 573 // Should equal Debug::kX64JSReturnSequenceLength - kCallTargetAddressOffset; 574 static const int kPatchReturnSequenceAddressOffset = 13 - 4; 575 // Distance between start of patched debug break slot and where the 576 // 32-bit displacement of a near call would be, relative to the pushed 577 // return address. TODO: Use return sequence length instead. 578 // Should equal Debug::kX64JSReturnSequenceLength - kCallTargetAddressOffset; 579 static const int kPatchDebugBreakSlotAddressOffset = 13 - 4; 580 // TODO(X64): Rename this, removing the "Real", after changing the above. 581 static const int kRealPatchReturnSequenceAddressOffset = 2; 582 583 // Some x64 JS code is padded with int3 to make it large 584 // enough to hold an instruction when the debugger patches it. 585 static const int kJumpInstructionLength = 13; 586 static const int kCallInstructionLength = 13; 587 static const int kJSReturnSequenceLength = 13; 588 static const int kShortCallInstructionLength = 5; 589 590 // The debug break slot must be able to contain a call instruction. 591 static const int kDebugBreakSlotLength = kCallInstructionLength; 592 593 // One byte opcode for test eax,0xXXXXXXXX. 594 static const byte kTestEaxByte = 0xA9; 595 // One byte opcode for test al, 0xXX. 596 static const byte kTestAlByte = 0xA8; 597 // One byte opcode for nop. 598 static const byte kNopByte = 0x90; 599 600 // One byte prefix for a short conditional jump. 601 static const byte kJccShortPrefix = 0x70; 602 static const byte kJncShortOpcode = kJccShortPrefix | not_carry; 603 static const byte kJcShortOpcode = kJccShortPrefix | carry; 604 605 606 607 // --------------------------------------------------------------------------- 608 // Code generation 609 // 610 // Function names correspond one-to-one to x64 instruction mnemonics. 611 // Unless specified otherwise, instructions operate on 64-bit operands. 612 // 613 // If we need versions of an assembly instruction that operate on different 614 // width arguments, we add a single-letter suffix specifying the width. 615 // This is done for the following instructions: mov, cmp, inc, dec, 616 // add, sub, and test. 617 // There are no versions of these instructions without the suffix. 618 // - Instructions on 8-bit (byte) operands/registers have a trailing 'b'. 619 // - Instructions on 16-bit (word) operands/registers have a trailing 'w'. 620 // - Instructions on 32-bit (doubleword) operands/registers use 'l'. 621 // - Instructions on 64-bit (quadword) operands/registers use 'q'. 622 // 623 // Some mnemonics, such as "and", are the same as C++ keywords. 624 // Naming conflicts with C++ keywords are resolved by adding a trailing '_'. 625 626 // Insert the smallest number of nop instructions 627 // possible to align the pc offset to a multiple 628 // of m, where m must be a power of 2. 629 void Align(int m); 630 // Aligns code to something that's optimal for a jump target for the platform. 631 void CodeTargetAlign(); 632 633 // Stack 634 void pushfq(); 635 void popfq(); 636 637 void push(Immediate value); 638 // Push a 32 bit integer, and guarantee that it is actually pushed as a 639 // 32 bit value, the normal push will optimize the 8 bit case. 640 void push_imm32(int32_t imm32); 641 void push(Register src); 642 void push(const Operand& src); 643 644 void pop(Register dst); 645 void pop(const Operand& dst); 646 647 void enter(Immediate size); 648 void leave(); 649 650 // Moves 651 void movb(Register dst, const Operand& src); 652 void movb(Register dst, Immediate imm); 653 void movb(const Operand& dst, Register src); 654 655 // Move the low 16 bits of a 64-bit register value to a 16-bit 656 // memory location. 657 void movw(const Operand& dst, Register src); 658 659 void movl(Register dst, Register src); 660 void movl(Register dst, const Operand& src); 661 void movl(const Operand& dst, Register src); 662 void movl(const Operand& dst, Immediate imm); 663 // Load a 32-bit immediate value, zero-extended to 64 bits. 664 void movl(Register dst, Immediate imm32); 665 666 // Move 64 bit register value to 64-bit memory location. 667 void movq(const Operand& dst, Register src); 668 // Move 64 bit memory location to 64-bit register value. 669 void movq(Register dst, const Operand& src); 670 void movq(Register dst, Register src); 671 // Sign extends immediate 32-bit value to 64 bits. 672 void movq(Register dst, Immediate x); 673 // Move the offset of the label location relative to the current 674 // position (after the move) to the destination. 675 void movl(const Operand& dst, Label* src); 676 677 // Move sign extended immediate to memory location. 678 void movq(const Operand& dst, Immediate value); 679 // Instructions to load a 64-bit immediate into a register. 680 // All 64-bit immediates must have a relocation mode. 681 void movq(Register dst, void* ptr, RelocInfo::Mode rmode); 682 void movq(Register dst, int64_t value, RelocInfo::Mode rmode); 683 void movq(Register dst, const char* s, RelocInfo::Mode rmode); 684 // Moves the address of the external reference into the register. 685 void movq(Register dst, ExternalReference ext); 686 void movq(Register dst, Handle<Object> handle, RelocInfo::Mode rmode); 687 688 void movsxbq(Register dst, const Operand& src); 689 void movsxwq(Register dst, const Operand& src); 690 void movsxlq(Register dst, Register src); 691 void movsxlq(Register dst, const Operand& src); 692 void movzxbq(Register dst, const Operand& src); 693 void movzxbl(Register dst, const Operand& src); 694 void movzxwq(Register dst, const Operand& src); 695 void movzxwl(Register dst, const Operand& src); 696 697 // Repeated moves. 698 699 void repmovsb(); 700 void repmovsw(); 701 void repmovsl(); 702 void repmovsq(); 703 704 // Instruction to load from an immediate 64-bit pointer into RAX. 705 void load_rax(void* ptr, RelocInfo::Mode rmode); 706 void load_rax(ExternalReference ext); 707 708 // Conditional moves. 709 void cmovq(Condition cc, Register dst, Register src); 710 void cmovq(Condition cc, Register dst, const Operand& src); 711 void cmovl(Condition cc, Register dst, Register src); 712 void cmovl(Condition cc, Register dst, const Operand& src); 713 714 // Exchange two registers 715 void xchg(Register dst, Register src); 716 717 // Arithmetics 718 void addl(Register dst, Register src) { 719 arithmetic_op_32(0x03, dst, src); 720 } 721 722 void addl(Register dst, Immediate src) { 723 immediate_arithmetic_op_32(0x0, dst, src); 724 } 725 726 void addl(Register dst, const Operand& src) { 727 arithmetic_op_32(0x03, dst, src); 728 } 729 730 void addl(const Operand& dst, Immediate src) { 731 immediate_arithmetic_op_32(0x0, dst, src); 732 } 733 734 void addq(Register dst, Register src) { 735 arithmetic_op(0x03, dst, src); 736 } 737 738 void addq(Register dst, const Operand& src) { 739 arithmetic_op(0x03, dst, src); 740 } 741 742 void addq(const Operand& dst, Register src) { 743 arithmetic_op(0x01, src, dst); 744 } 745 746 void addq(Register dst, Immediate src) { 747 immediate_arithmetic_op(0x0, dst, src); 748 } 749 750 void addq(const Operand& dst, Immediate src) { 751 immediate_arithmetic_op(0x0, dst, src); 752 } 753 754 void sbbl(Register dst, Register src) { 755 arithmetic_op_32(0x1b, dst, src); 756 } 757 758 void sbbq(Register dst, Register src) { 759 arithmetic_op(0x1b, dst, src); 760 } 761 762 void cmpb(Register dst, Immediate src) { 763 immediate_arithmetic_op_8(0x7, dst, src); 764 } 765 766 void cmpb_al(Immediate src); 767 768 void cmpb(Register dst, Register src) { 769 arithmetic_op(0x3A, dst, src); 770 } 771 772 void cmpb(Register dst, const Operand& src) { 773 arithmetic_op(0x3A, dst, src); 774 } 775 776 void cmpb(const Operand& dst, Register src) { 777 arithmetic_op(0x38, src, dst); 778 } 779 780 void cmpb(const Operand& dst, Immediate src) { 781 immediate_arithmetic_op_8(0x7, dst, src); 782 } 783 784 void cmpw(const Operand& dst, Immediate src) { 785 immediate_arithmetic_op_16(0x7, dst, src); 786 } 787 788 void cmpw(Register dst, Immediate src) { 789 immediate_arithmetic_op_16(0x7, dst, src); 790 } 791 792 void cmpw(Register dst, const Operand& src) { 793 arithmetic_op_16(0x3B, dst, src); 794 } 795 796 void cmpw(Register dst, Register src) { 797 arithmetic_op_16(0x3B, dst, src); 798 } 799 800 void cmpw(const Operand& dst, Register src) { 801 arithmetic_op_16(0x39, src, dst); 802 } 803 804 void cmpl(Register dst, Register src) { 805 arithmetic_op_32(0x3B, dst, src); 806 } 807 808 void cmpl(Register dst, const Operand& src) { 809 arithmetic_op_32(0x3B, dst, src); 810 } 811 812 void cmpl(const Operand& dst, Register src) { 813 arithmetic_op_32(0x39, src, dst); 814 } 815 816 void cmpl(Register dst, Immediate src) { 817 immediate_arithmetic_op_32(0x7, dst, src); 818 } 819 820 void cmpl(const Operand& dst, Immediate src) { 821 immediate_arithmetic_op_32(0x7, dst, src); 822 } 823 824 void cmpq(Register dst, Register src) { 825 arithmetic_op(0x3B, dst, src); 826 } 827 828 void cmpq(Register dst, const Operand& src) { 829 arithmetic_op(0x3B, dst, src); 830 } 831 832 void cmpq(const Operand& dst, Register src) { 833 arithmetic_op(0x39, src, dst); 834 } 835 836 void cmpq(Register dst, Immediate src) { 837 immediate_arithmetic_op(0x7, dst, src); 838 } 839 840 void cmpq(const Operand& dst, Immediate src) { 841 immediate_arithmetic_op(0x7, dst, src); 842 } 843 844 void and_(Register dst, Register src) { 845 arithmetic_op(0x23, dst, src); 846 } 847 848 void and_(Register dst, const Operand& src) { 849 arithmetic_op(0x23, dst, src); 850 } 851 852 void and_(const Operand& dst, Register src) { 853 arithmetic_op(0x21, src, dst); 854 } 855 856 void and_(Register dst, Immediate src) { 857 immediate_arithmetic_op(0x4, dst, src); 858 } 859 860 void and_(const Operand& dst, Immediate src) { 861 immediate_arithmetic_op(0x4, dst, src); 862 } 863 864 void andl(Register dst, Immediate src) { 865 immediate_arithmetic_op_32(0x4, dst, src); 866 } 867 868 void andl(Register dst, Register src) { 869 arithmetic_op_32(0x23, dst, src); 870 } 871 872 void andl(Register dst, const Operand& src) { 873 arithmetic_op_32(0x23, dst, src); 874 } 875 876 void andb(Register dst, Immediate src) { 877 immediate_arithmetic_op_8(0x4, dst, src); 878 } 879 880 void decq(Register dst); 881 void decq(const Operand& dst); 882 void decl(Register dst); 883 void decl(const Operand& dst); 884 void decb(Register dst); 885 void decb(const Operand& dst); 886 887 // Sign-extends rax into rdx:rax. 888 void cqo(); 889 // Sign-extends eax into edx:eax. 890 void cdq(); 891 892 // Divide rdx:rax by src. Quotient in rax, remainder in rdx. 893 void idivq(Register src); 894 // Divide edx:eax by lower 32 bits of src. Quotient in eax, rem. in edx. 895 void idivl(Register src); 896 897 // Signed multiply instructions. 898 void imul(Register src); // rdx:rax = rax * src. 899 void imul(Register dst, Register src); // dst = dst * src. 900 void imul(Register dst, const Operand& src); // dst = dst * src. 901 void imul(Register dst, Register src, Immediate imm); // dst = src * imm. 902 // Signed 32-bit multiply instructions. 903 void imull(Register dst, Register src); // dst = dst * src. 904 void imull(Register dst, const Operand& src); // dst = dst * src. 905 void imull(Register dst, Register src, Immediate imm); // dst = src * imm. 906 907 void incq(Register dst); 908 void incq(const Operand& dst); 909 void incl(Register dst); 910 void incl(const Operand& dst); 911 912 void lea(Register dst, const Operand& src); 913 void leal(Register dst, const Operand& src); 914 915 // Multiply rax by src, put the result in rdx:rax. 916 void mul(Register src); 917 918 void neg(Register dst); 919 void neg(const Operand& dst); 920 void negl(Register dst); 921 922 void not_(Register dst); 923 void not_(const Operand& dst); 924 void notl(Register dst); 925 926 void or_(Register dst, Register src) { 927 arithmetic_op(0x0B, dst, src); 928 } 929 930 void orl(Register dst, Register src) { 931 arithmetic_op_32(0x0B, dst, src); 932 } 933 934 void or_(Register dst, const Operand& src) { 935 arithmetic_op(0x0B, dst, src); 936 } 937 938 void orl(Register dst, const Operand& src) { 939 arithmetic_op_32(0x0B, dst, src); 940 } 941 942 void or_(const Operand& dst, Register src) { 943 arithmetic_op(0x09, src, dst); 944 } 945 946 void or_(Register dst, Immediate src) { 947 immediate_arithmetic_op(0x1, dst, src); 948 } 949 950 void orl(Register dst, Immediate src) { 951 immediate_arithmetic_op_32(0x1, dst, src); 952 } 953 954 void or_(const Operand& dst, Immediate src) { 955 immediate_arithmetic_op(0x1, dst, src); 956 } 957 958 void orl(const Operand& dst, Immediate src) { 959 immediate_arithmetic_op_32(0x1, dst, src); 960 } 961 962 963 void rcl(Register dst, Immediate imm8) { 964 shift(dst, imm8, 0x2); 965 } 966 967 void rol(Register dst, Immediate imm8) { 968 shift(dst, imm8, 0x0); 969 } 970 971 void rcr(Register dst, Immediate imm8) { 972 shift(dst, imm8, 0x3); 973 } 974 975 void ror(Register dst, Immediate imm8) { 976 shift(dst, imm8, 0x1); 977 } 978 979 // Shifts dst:src left by cl bits, affecting only dst. 980 void shld(Register dst, Register src); 981 982 // Shifts src:dst right by cl bits, affecting only dst. 983 void shrd(Register dst, Register src); 984 985 // Shifts dst right, duplicating sign bit, by shift_amount bits. 986 // Shifting by 1 is handled efficiently. 987 void sar(Register dst, Immediate shift_amount) { 988 shift(dst, shift_amount, 0x7); 989 } 990 991 // Shifts dst right, duplicating sign bit, by shift_amount bits. 992 // Shifting by 1 is handled efficiently. 993 void sarl(Register dst, Immediate shift_amount) { 994 shift_32(dst, shift_amount, 0x7); 995 } 996 997 // Shifts dst right, duplicating sign bit, by cl % 64 bits. 998 void sar_cl(Register dst) { 999 shift(dst, 0x7); 1000 } 1001 1002 // Shifts dst right, duplicating sign bit, by cl % 64 bits. 1003 void sarl_cl(Register dst) { 1004 shift_32(dst, 0x7); 1005 } 1006 1007 void shl(Register dst, Immediate shift_amount) { 1008 shift(dst, shift_amount, 0x4); 1009 } 1010 1011 void shl_cl(Register dst) { 1012 shift(dst, 0x4); 1013 } 1014 1015 void shll_cl(Register dst) { 1016 shift_32(dst, 0x4); 1017 } 1018 1019 void shll(Register dst, Immediate shift_amount) { 1020 shift_32(dst, shift_amount, 0x4); 1021 } 1022 1023 void shr(Register dst, Immediate shift_amount) { 1024 shift(dst, shift_amount, 0x5); 1025 } 1026 1027 void shr_cl(Register dst) { 1028 shift(dst, 0x5); 1029 } 1030 1031 void shrl_cl(Register dst) { 1032 shift_32(dst, 0x5); 1033 } 1034 1035 void shrl(Register dst, Immediate shift_amount) { 1036 shift_32(dst, shift_amount, 0x5); 1037 } 1038 1039 void store_rax(void* dst, RelocInfo::Mode mode); 1040 void store_rax(ExternalReference ref); 1041 1042 void subq(Register dst, Register src) { 1043 arithmetic_op(0x2B, dst, src); 1044 } 1045 1046 void subq(Register dst, const Operand& src) { 1047 arithmetic_op(0x2B, dst, src); 1048 } 1049 1050 void subq(const Operand& dst, Register src) { 1051 arithmetic_op(0x29, src, dst); 1052 } 1053 1054 void subq(Register dst, Immediate src) { 1055 immediate_arithmetic_op(0x5, dst, src); 1056 } 1057 1058 void subq(const Operand& dst, Immediate src) { 1059 immediate_arithmetic_op(0x5, dst, src); 1060 } 1061 1062 void subl(Register dst, Register src) { 1063 arithmetic_op_32(0x2B, dst, src); 1064 } 1065 1066 void subl(Register dst, const Operand& src) { 1067 arithmetic_op_32(0x2B, dst, src); 1068 } 1069 1070 void subl(const Operand& dst, Immediate src) { 1071 immediate_arithmetic_op_32(0x5, dst, src); 1072 } 1073 1074 void subl(Register dst, Immediate src) { 1075 immediate_arithmetic_op_32(0x5, dst, src); 1076 } 1077 1078 void subb(Register dst, Immediate src) { 1079 immediate_arithmetic_op_8(0x5, dst, src); 1080 } 1081 1082 void testb(Register dst, Register src); 1083 void testb(Register reg, Immediate mask); 1084 void testb(const Operand& op, Immediate mask); 1085 void testb(const Operand& op, Register reg); 1086 void testl(Register dst, Register src); 1087 void testl(Register reg, Immediate mask); 1088 void testl(const Operand& op, Immediate mask); 1089 void testq(const Operand& op, Register reg); 1090 void testq(Register dst, Register src); 1091 void testq(Register dst, Immediate mask); 1092 1093 void xor_(Register dst, Register src) { 1094 if (dst.code() == src.code()) { 1095 arithmetic_op_32(0x33, dst, src); 1096 } else { 1097 arithmetic_op(0x33, dst, src); 1098 } 1099 } 1100 1101 void xorl(Register dst, Register src) { 1102 arithmetic_op_32(0x33, dst, src); 1103 } 1104 1105 void xorl(Register dst, const Operand& src) { 1106 arithmetic_op_32(0x33, dst, src); 1107 } 1108 1109 void xorl(Register dst, Immediate src) { 1110 immediate_arithmetic_op_32(0x6, dst, src); 1111 } 1112 1113 void xorl(const Operand& dst, Immediate src) { 1114 immediate_arithmetic_op_32(0x6, dst, src); 1115 } 1116 1117 void xor_(Register dst, const Operand& src) { 1118 arithmetic_op(0x33, dst, src); 1119 } 1120 1121 void xor_(const Operand& dst, Register src) { 1122 arithmetic_op(0x31, src, dst); 1123 } 1124 1125 void xor_(Register dst, Immediate src) { 1126 immediate_arithmetic_op(0x6, dst, src); 1127 } 1128 1129 void xor_(const Operand& dst, Immediate src) { 1130 immediate_arithmetic_op(0x6, dst, src); 1131 } 1132 1133 // Bit operations. 1134 void bt(const Operand& dst, Register src); 1135 void bts(const Operand& dst, Register src); 1136 1137 // Miscellaneous 1138 void clc(); 1139 void cld(); 1140 void cpuid(); 1141 void hlt(); 1142 void int3(); 1143 void nop(); 1144 void nop(int n); 1145 void rdtsc(); 1146 void ret(int imm16); 1147 void setcc(Condition cc, Register reg); 1148 1149 // Label operations & relative jumps (PPUM Appendix D) 1150 // 1151 // Takes a branch opcode (cc) and a label (L) and generates 1152 // either a backward branch or a forward branch and links it 1153 // to the label fixup chain. Usage: 1154 // 1155 // Label L; // unbound label 1156 // j(cc, &L); // forward branch to unbound label 1157 // bind(&L); // bind label to the current pc 1158 // j(cc, &L); // backward branch to bound label 1159 // bind(&L); // illegal: a label may be bound only once 1160 // 1161 // Note: The same Label can be used for forward and backward branches 1162 // but it may be bound only once. 1163 1164 void bind(Label* L); // binds an unbound label L to the current code position 1165 1166 // Calls 1167 // Call near relative 32-bit displacement, relative to next instruction. 1168 void call(Label* L); 1169 void call(Handle<Code> target, 1170 RelocInfo::Mode rmode, 1171 unsigned ast_id = kNoASTId); 1172 1173 // Calls directly to the given address using a relative offset. 1174 // Should only ever be used in Code objects for calls within the 1175 // same Code object. Should not be used when generating new code (use labels), 1176 // but only when patching existing code. 1177 void call(Address target); 1178 1179 // Call near absolute indirect, address in register 1180 void call(Register adr); 1181 1182 // Call near indirect 1183 void call(const Operand& operand); 1184 1185 // Jumps 1186 // Jump short or near relative. 1187 // Use a 32-bit signed displacement. 1188 // Unconditional jump to L 1189 void jmp(Label* L, Label::Distance distance = Label::kFar); 1190 void jmp(Handle<Code> target, RelocInfo::Mode rmode); 1191 1192 // Jump near absolute indirect (r64) 1193 void jmp(Register adr); 1194 1195 // Jump near absolute indirect (m64) 1196 void jmp(const Operand& src); 1197 1198 // Conditional jumps 1199 void j(Condition cc, 1200 Label* L, 1201 Label::Distance distance = Label::kFar); 1202 void j(Condition cc, Handle<Code> target, RelocInfo::Mode rmode); 1203 1204 // Floating-point operations 1205 void fld(int i); 1206 1207 void fld1(); 1208 void fldz(); 1209 void fldpi(); 1210 void fldln2(); 1211 1212 void fld_s(const Operand& adr); 1213 void fld_d(const Operand& adr); 1214 1215 void fstp_s(const Operand& adr); 1216 void fstp_d(const Operand& adr); 1217 void fstp(int index); 1218 1219 void fild_s(const Operand& adr); 1220 void fild_d(const Operand& adr); 1221 1222 void fist_s(const Operand& adr); 1223 1224 void fistp_s(const Operand& adr); 1225 void fistp_d(const Operand& adr); 1226 1227 void fisttp_s(const Operand& adr); 1228 void fisttp_d(const Operand& adr); 1229 1230 void fabs(); 1231 void fchs(); 1232 1233 void fadd(int i); 1234 void fsub(int i); 1235 void fmul(int i); 1236 void fdiv(int i); 1237 1238 void fisub_s(const Operand& adr); 1239 1240 void faddp(int i = 1); 1241 void fsubp(int i = 1); 1242 void fsubrp(int i = 1); 1243 void fmulp(int i = 1); 1244 void fdivp(int i = 1); 1245 void fprem(); 1246 void fprem1(); 1247 1248 void fxch(int i = 1); 1249 void fincstp(); 1250 void ffree(int i = 0); 1251 1252 void ftst(); 1253 void fucomp(int i); 1254 void fucompp(); 1255 void fucomi(int i); 1256 void fucomip(); 1257 1258 void fcompp(); 1259 void fnstsw_ax(); 1260 void fwait(); 1261 void fnclex(); 1262 1263 void fsin(); 1264 void fcos(); 1265 void fyl2x(); 1266 1267 void frndint(); 1268 1269 void sahf(); 1270 1271 // SSE2 instructions 1272 void movd(XMMRegister dst, Register src); 1273 void movd(Register dst, XMMRegister src); 1274 void movq(XMMRegister dst, Register src); 1275 void movq(Register dst, XMMRegister src); 1276 void movq(XMMRegister dst, XMMRegister src); 1277 void extractps(Register dst, XMMRegister src, byte imm8); 1278 1279 // Don't use this unless it's important to keep the 1280 // top half of the destination register unchanged. 1281 // Used movaps when moving double values and movq for integer 1282 // values in xmm registers. 1283 void movsd(XMMRegister dst, XMMRegister src); 1284 1285 void movsd(const Operand& dst, XMMRegister src); 1286 void movsd(XMMRegister dst, const Operand& src); 1287 1288 void movdqa(const Operand& dst, XMMRegister src); 1289 void movdqa(XMMRegister dst, const Operand& src); 1290 1291 void movapd(XMMRegister dst, XMMRegister src); 1292 void movaps(XMMRegister dst, XMMRegister src); 1293 1294 void movss(XMMRegister dst, const Operand& src); 1295 void movss(const Operand& dst, XMMRegister src); 1296 1297 void cvttss2si(Register dst, const Operand& src); 1298 void cvttss2si(Register dst, XMMRegister src); 1299 void cvttsd2si(Register dst, const Operand& src); 1300 void cvttsd2si(Register dst, XMMRegister src); 1301 void cvttsd2siq(Register dst, XMMRegister src); 1302 1303 void cvtlsi2sd(XMMRegister dst, const Operand& src); 1304 void cvtlsi2sd(XMMRegister dst, Register src); 1305 void cvtqsi2sd(XMMRegister dst, const Operand& src); 1306 void cvtqsi2sd(XMMRegister dst, Register src); 1307 1308 void cvtlsi2ss(XMMRegister dst, Register src); 1309 1310 void cvtss2sd(XMMRegister dst, XMMRegister src); 1311 void cvtss2sd(XMMRegister dst, const Operand& src); 1312 void cvtsd2ss(XMMRegister dst, XMMRegister src); 1313 1314 void cvtsd2si(Register dst, XMMRegister src); 1315 void cvtsd2siq(Register dst, XMMRegister src); 1316 1317 void addsd(XMMRegister dst, XMMRegister src); 1318 void subsd(XMMRegister dst, XMMRegister src); 1319 void mulsd(XMMRegister dst, XMMRegister src); 1320 void divsd(XMMRegister dst, XMMRegister src); 1321 1322 void andpd(XMMRegister dst, XMMRegister src); 1323 void orpd(XMMRegister dst, XMMRegister src); 1324 void xorpd(XMMRegister dst, XMMRegister src); 1325 void xorps(XMMRegister dst, XMMRegister src); 1326 void sqrtsd(XMMRegister dst, XMMRegister src); 1327 1328 void ucomisd(XMMRegister dst, XMMRegister src); 1329 void ucomisd(XMMRegister dst, const Operand& src); 1330 1331 enum RoundingMode { 1332 kRoundToNearest = 0x0, 1333 kRoundDown = 0x1, 1334 kRoundUp = 0x2, 1335 kRoundToZero = 0x3 1336 }; 1337 1338 void roundsd(XMMRegister dst, XMMRegister src, RoundingMode mode); 1339 1340 void movmskpd(Register dst, XMMRegister src); 1341 1342 // The first argument is the reg field, the second argument is the r/m field. 1343 void emit_sse_operand(XMMRegister dst, XMMRegister src); 1344 void emit_sse_operand(XMMRegister reg, const Operand& adr); 1345 void emit_sse_operand(XMMRegister dst, Register src); 1346 void emit_sse_operand(Register dst, XMMRegister src); 1347 1348 // Debugging 1349 void Print(); 1350 1351 // Check the code size generated from label to here. 1352 int SizeOfCodeGeneratedSince(Label* l) { return pc_offset() - l->pos(); } 1353 1354 // Mark address of the ExitJSFrame code. 1355 void RecordJSReturn(); 1356 1357 // Mark address of a debug break slot. 1358 void RecordDebugBreakSlot(); 1359 1360 // Record a comment relocation entry that can be used by a disassembler. 1361 // Use --code-comments to enable. 1362 void RecordComment(const char* msg, bool force = false); 1363 1364 // Writes a single word of data in the code stream. 1365 // Used for inline tables, e.g., jump-tables. 1366 void db(uint8_t data); 1367 void dd(uint32_t data); 1368 1369 int pc_offset() const { return static_cast<int>(pc_ - buffer_); } 1370 1371 PositionsRecorder* positions_recorder() { return &positions_recorder_; } 1372 1373 // Check if there is less than kGap bytes available in the buffer. 1374 // If this is the case, we need to grow the buffer before emitting 1375 // an instruction or relocation information. 1376 inline bool buffer_overflow() const { 1377 return pc_ >= reloc_info_writer.pos() - kGap; 1378 } 1379 1380 // Get the number of bytes available in the buffer. 1381 inline int available_space() const { 1382 return static_cast<int>(reloc_info_writer.pos() - pc_); 1383 } 1384 1385 static bool IsNop(Address addr) { return *addr == 0x90; } 1386 1387 // Avoid overflows for displacements etc. 1388 static const int kMaximalBufferSize = 512*MB; 1389 static const int kMinimalBufferSize = 4*KB; 1390 1391 protected: 1392 bool emit_debug_code() const { return emit_debug_code_; } 1393 1394 private: 1395 byte* addr_at(int pos) { return buffer_ + pos; } 1396 byte byte_at(int pos) { return buffer_[pos]; } 1397 void set_byte_at(int pos, byte value) { buffer_[pos] = value; } 1398 uint32_t long_at(int pos) { 1399 return *reinterpret_cast<uint32_t*>(addr_at(pos)); 1400 } 1401 void long_at_put(int pos, uint32_t x) { 1402 *reinterpret_cast<uint32_t*>(addr_at(pos)) = x; 1403 } 1404 1405 // code emission 1406 void GrowBuffer(); 1407 1408 void emit(byte x) { *pc_++ = x; } 1409 inline void emitl(uint32_t x); 1410 inline void emitq(uint64_t x, RelocInfo::Mode rmode); 1411 inline void emitw(uint16_t x); 1412 inline void emit_code_target(Handle<Code> target, 1413 RelocInfo::Mode rmode, 1414 unsigned ast_id = kNoASTId); 1415 void emit(Immediate x) { emitl(x.value_); } 1416 1417 // Emits a REX prefix that encodes a 64-bit operand size and 1418 // the top bit of both register codes. 1419 // High bit of reg goes to REX.R, high bit of rm_reg goes to REX.B. 1420 // REX.W is set. 1421 inline void emit_rex_64(XMMRegister reg, Register rm_reg); 1422 inline void emit_rex_64(Register reg, XMMRegister rm_reg); 1423 inline void emit_rex_64(Register reg, Register rm_reg); 1424 1425 // Emits a REX prefix that encodes a 64-bit operand size and 1426 // the top bit of the destination, index, and base register codes. 1427 // The high bit of reg is used for REX.R, the high bit of op's base 1428 // register is used for REX.B, and the high bit of op's index register 1429 // is used for REX.X. REX.W is set. 1430 inline void emit_rex_64(Register reg, const Operand& op); 1431 inline void emit_rex_64(XMMRegister reg, const Operand& op); 1432 1433 // Emits a REX prefix that encodes a 64-bit operand size and 1434 // the top bit of the register code. 1435 // The high bit of register is used for REX.B. 1436 // REX.W is set and REX.R and REX.X are clear. 1437 inline void emit_rex_64(Register rm_reg); 1438 1439 // Emits a REX prefix that encodes a 64-bit operand size and 1440 // the top bit of the index and base register codes. 1441 // The high bit of op's base register is used for REX.B, and the high 1442 // bit of op's index register is used for REX.X. 1443 // REX.W is set and REX.R clear. 1444 inline void emit_rex_64(const Operand& op); 1445 1446 // Emit a REX prefix that only sets REX.W to choose a 64-bit operand size. 1447 void emit_rex_64() { emit(0x48); } 1448 1449 // High bit of reg goes to REX.R, high bit of rm_reg goes to REX.B. 1450 // REX.W is clear. 1451 inline void emit_rex_32(Register reg, Register rm_reg); 1452 1453 // The high bit of reg is used for REX.R, the high bit of op's base 1454 // register is used for REX.B, and the high bit of op's index register 1455 // is used for REX.X. REX.W is cleared. 1456 inline void emit_rex_32(Register reg, const Operand& op); 1457 1458 // High bit of rm_reg goes to REX.B. 1459 // REX.W, REX.R and REX.X are clear. 1460 inline void emit_rex_32(Register rm_reg); 1461 1462 // High bit of base goes to REX.B and high bit of index to REX.X. 1463 // REX.W and REX.R are clear. 1464 inline void emit_rex_32(const Operand& op); 1465 1466 // High bit of reg goes to REX.R, high bit of rm_reg goes to REX.B. 1467 // REX.W is cleared. If no REX bits are set, no byte is emitted. 1468 inline void emit_optional_rex_32(Register reg, Register rm_reg); 1469 1470 // The high bit of reg is used for REX.R, the high bit of op's base 1471 // register is used for REX.B, and the high bit of op's index register 1472 // is used for REX.X. REX.W is cleared. If no REX bits are set, nothing 1473 // is emitted. 1474 inline void emit_optional_rex_32(Register reg, const Operand& op); 1475 1476 // As for emit_optional_rex_32(Register, Register), except that 1477 // the registers are XMM registers. 1478 inline void emit_optional_rex_32(XMMRegister reg, XMMRegister base); 1479 1480 // As for emit_optional_rex_32(Register, Register), except that 1481 // one of the registers is an XMM registers. 1482 inline void emit_optional_rex_32(XMMRegister reg, Register base); 1483 1484 // As for emit_optional_rex_32(Register, Register), except that 1485 // one of the registers is an XMM registers. 1486 inline void emit_optional_rex_32(Register reg, XMMRegister base); 1487 1488 // As for emit_optional_rex_32(Register, const Operand&), except that 1489 // the register is an XMM register. 1490 inline void emit_optional_rex_32(XMMRegister reg, const Operand& op); 1491 1492 // Optionally do as emit_rex_32(Register) if the register number has 1493 // the high bit set. 1494 inline void emit_optional_rex_32(Register rm_reg); 1495 1496 // Optionally do as emit_rex_32(const Operand&) if the operand register 1497 // numbers have a high bit set. 1498 inline void emit_optional_rex_32(const Operand& op); 1499 1500 1501 // Emit the ModR/M byte, and optionally the SIB byte and 1502 // 1- or 4-byte offset for a memory operand. Also encodes 1503 // the second operand of the operation, a register or operation 1504 // subcode, into the reg field of the ModR/M byte. 1505 void emit_operand(Register reg, const Operand& adr) { 1506 emit_operand(reg.low_bits(), adr); 1507 } 1508 1509 // Emit the ModR/M byte, and optionally the SIB byte and 1510 // 1- or 4-byte offset for a memory operand. Also used to encode 1511 // a three-bit opcode extension into the ModR/M byte. 1512 void emit_operand(int rm, const Operand& adr); 1513 1514 // Emit a ModR/M byte with registers coded in the reg and rm_reg fields. 1515 void emit_modrm(Register reg, Register rm_reg) { 1516 emit(0xC0 | reg.low_bits() << 3 | rm_reg.low_bits()); 1517 } 1518 1519 // Emit a ModR/M byte with an operation subcode in the reg field and 1520 // a register in the rm_reg field. 1521 void emit_modrm(int code, Register rm_reg) { 1522 ASSERT(is_uint3(code)); 1523 emit(0xC0 | code << 3 | rm_reg.low_bits()); 1524 } 1525 1526 // Emit the code-object-relative offset of the label's position 1527 inline void emit_code_relative_offset(Label* label); 1528 1529 // Emit machine code for one of the operations ADD, ADC, SUB, SBC, 1530 // AND, OR, XOR, or CMP. The encodings of these operations are all 1531 // similar, differing just in the opcode or in the reg field of the 1532 // ModR/M byte. 1533 void arithmetic_op_16(byte opcode, Register reg, Register rm_reg); 1534 void arithmetic_op_16(byte opcode, Register reg, const Operand& rm_reg); 1535 void arithmetic_op_32(byte opcode, Register reg, Register rm_reg); 1536 void arithmetic_op_32(byte opcode, Register reg, const Operand& rm_reg); 1537 void arithmetic_op(byte opcode, Register reg, Register rm_reg); 1538 void arithmetic_op(byte opcode, Register reg, const Operand& rm_reg); 1539 void immediate_arithmetic_op(byte subcode, Register dst, Immediate src); 1540 void immediate_arithmetic_op(byte subcode, const Operand& dst, Immediate src); 1541 // Operate on a byte in memory or register. 1542 void immediate_arithmetic_op_8(byte subcode, 1543 Register dst, 1544 Immediate src); 1545 void immediate_arithmetic_op_8(byte subcode, 1546 const Operand& dst, 1547 Immediate src); 1548 // Operate on a word in memory or register. 1549 void immediate_arithmetic_op_16(byte subcode, 1550 Register dst, 1551 Immediate src); 1552 void immediate_arithmetic_op_16(byte subcode, 1553 const Operand& dst, 1554 Immediate src); 1555 // Operate on a 32-bit word in memory or register. 1556 void immediate_arithmetic_op_32(byte subcode, 1557 Register dst, 1558 Immediate src); 1559 void immediate_arithmetic_op_32(byte subcode, 1560 const Operand& dst, 1561 Immediate src); 1562 1563 // Emit machine code for a shift operation. 1564 void shift(Register dst, Immediate shift_amount, int subcode); 1565 void shift_32(Register dst, Immediate shift_amount, int subcode); 1566 // Shift dst by cl % 64 bits. 1567 void shift(Register dst, int subcode); 1568 void shift_32(Register dst, int subcode); 1569 1570 void emit_farith(int b1, int b2, int i); 1571 1572 // labels 1573 // void print(Label* L); 1574 void bind_to(Label* L, int pos); 1575 1576 // record reloc info for current pc_ 1577 void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data = 0); 1578 1579 friend class CodePatcher; 1580 friend class EnsureSpace; 1581 friend class RegExpMacroAssemblerX64; 1582 1583 // Code buffer: 1584 // The buffer into which code and relocation info are generated. 1585 byte* buffer_; 1586 int buffer_size_; 1587 // True if the assembler owns the buffer, false if buffer is external. 1588 bool own_buffer_; 1589 1590 // code generation 1591 byte* pc_; // the program counter; moves forward 1592 RelocInfoWriter reloc_info_writer; 1593 1594 List< Handle<Code> > code_targets_; 1595 1596 PositionsRecorder positions_recorder_; 1597 1598 bool emit_debug_code_; 1599 1600 friend class PositionsRecorder; 1601}; 1602 1603 1604// Helper class that ensures that there is enough space for generating 1605// instructions and relocation information. The constructor makes 1606// sure that there is enough space and (in debug mode) the destructor 1607// checks that we did not generate too much. 1608class EnsureSpace BASE_EMBEDDED { 1609 public: 1610 explicit EnsureSpace(Assembler* assembler) : assembler_(assembler) { 1611 if (assembler_->buffer_overflow()) assembler_->GrowBuffer(); 1612#ifdef DEBUG 1613 space_before_ = assembler_->available_space(); 1614#endif 1615 } 1616 1617#ifdef DEBUG 1618 ~EnsureSpace() { 1619 int bytes_generated = space_before_ - assembler_->available_space(); 1620 ASSERT(bytes_generated < assembler_->kGap); 1621 } 1622#endif 1623 1624 private: 1625 Assembler* assembler_; 1626#ifdef DEBUG 1627 int space_before_; 1628#endif 1629}; 1630 1631} } // namespace v8::internal 1632 1633#endif // V8_X64_ASSEMBLER_X64_H_ 1634