assembler-x64.h revision 9dcf7e2f83591d471e88bf7d230651900b8e424b
1// Copyright (c) 1994-2006 Sun Microsystems Inc. 2// All Rights Reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: 7// 8// - Redistributions of source code must retain the above copyright notice, 9// this list of conditions and the following disclaimer. 10// 11// - Redistribution in binary form must reproduce the above copyright 12// notice, this list of conditions and the following disclaimer in the 13// documentation and/or other materials provided with the distribution. 14// 15// - Neither the name of Sun Microsystems or the names of contributors may 16// be used to endorse or promote products derived from this software without 17// specific prior written permission. 18// 19// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 20// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 23// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 24// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 25// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 26// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 27// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 28// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 29// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 31// The original source code covered by the above license above has been 32// modified significantly by Google Inc. 33// Copyright 2006-2009 the V8 project authors. All rights reserved. 34 35// A lightweight X64 Assembler. 36 37#ifndef V8_X64_ASSEMBLER_X64_H_ 38#define V8_X64_ASSEMBLER_X64_H_ 39 40#include "serialize.h" 41 42namespace v8 { 43namespace internal { 44 45// Utility functions 46 47// Test whether a 64-bit value is in a specific range. 48static inline bool is_uint32(int64_t x) { 49 static const int64_t kUInt32Mask = V8_INT64_C(0xffffffff); 50 return x == (x & kUInt32Mask); 51} 52 53static inline bool is_int32(int64_t x) { 54 static const int64_t kMinIntValue = V8_INT64_C(-0x80000000); 55 return is_uint32(x - kMinIntValue); 56} 57 58static inline bool uint_is_int32(uint64_t x) { 59 static const uint64_t kMaxIntValue = V8_UINT64_C(0x80000000); 60 return x < kMaxIntValue; 61} 62 63static inline bool is_uint32(uint64_t x) { 64 static const uint64_t kMaxUIntValue = V8_UINT64_C(0x100000000); 65 return x < kMaxUIntValue; 66} 67 68// CPU Registers. 69// 70// 1) We would prefer to use an enum, but enum values are assignment- 71// compatible with int, which has caused code-generation bugs. 72// 73// 2) We would prefer to use a class instead of a struct but we don't like 74// the register initialization to depend on the particular initialization 75// order (which appears to be different on OS X, Linux, and Windows for the 76// installed versions of C++ we tried). Using a struct permits C-style 77// "initialization". Also, the Register objects cannot be const as this 78// forces initialization stubs in MSVC, making us dependent on initialization 79// order. 80// 81// 3) By not using an enum, we are possibly preventing the compiler from 82// doing certain constant folds, which may significantly reduce the 83// code generated for some assembly instructions (because they boil down 84// to a few constants). If this is a problem, we could change the code 85// such that we use an enum in optimized mode, and the struct in debug 86// mode. This way we get the compile-time error checking in debug mode 87// and best performance in optimized code. 88// 89 90struct Register { 91 static Register toRegister(int code) { 92 Register r = { code }; 93 return r; 94 } 95 bool is_valid() const { return 0 <= code_ && code_ < 16; } 96 bool is(Register reg) const { return code_ == reg.code_; } 97 int code() const { 98 ASSERT(is_valid()); 99 return code_; 100 } 101 int bit() const { 102 return 1 << code_; 103 } 104 105 // Return the high bit of the register code as a 0 or 1. Used often 106 // when constructing the REX prefix byte. 107 int high_bit() const { 108 return code_ >> 3; 109 } 110 // Return the 3 low bits of the register code. Used when encoding registers 111 // in modR/M, SIB, and opcode bytes. 112 int low_bits() const { 113 return code_ & 0x7; 114 } 115 116 // Unfortunately we can't make this private in a struct when initializing 117 // by assignment. 118 int code_; 119}; 120 121const Register rax = { 0 }; 122const Register rcx = { 1 }; 123const Register rdx = { 2 }; 124const Register rbx = { 3 }; 125const Register rsp = { 4 }; 126const Register rbp = { 5 }; 127const Register rsi = { 6 }; 128const Register rdi = { 7 }; 129const Register r8 = { 8 }; 130const Register r9 = { 9 }; 131const Register r10 = { 10 }; 132const Register r11 = { 11 }; 133const Register r12 = { 12 }; 134const Register r13 = { 13 }; 135const Register r14 = { 14 }; 136const Register r15 = { 15 }; 137const Register no_reg = { -1 }; 138 139 140struct XMMRegister { 141 bool is_valid() const { return 0 <= code_ && code_ < 16; } 142 int code() const { 143 ASSERT(is_valid()); 144 return code_; 145 } 146 147 // Return the high bit of the register code as a 0 or 1. Used often 148 // when constructing the REX prefix byte. 149 int high_bit() const { 150 return code_ >> 3; 151 } 152 // Return the 3 low bits of the register code. Used when encoding registers 153 // in modR/M, SIB, and opcode bytes. 154 int low_bits() const { 155 return code_ & 0x7; 156 } 157 158 int code_; 159}; 160 161const XMMRegister xmm0 = { 0 }; 162const XMMRegister xmm1 = { 1 }; 163const XMMRegister xmm2 = { 2 }; 164const XMMRegister xmm3 = { 3 }; 165const XMMRegister xmm4 = { 4 }; 166const XMMRegister xmm5 = { 5 }; 167const XMMRegister xmm6 = { 6 }; 168const XMMRegister xmm7 = { 7 }; 169const XMMRegister xmm8 = { 8 }; 170const XMMRegister xmm9 = { 9 }; 171const XMMRegister xmm10 = { 10 }; 172const XMMRegister xmm11 = { 11 }; 173const XMMRegister xmm12 = { 12 }; 174const XMMRegister xmm13 = { 13 }; 175const XMMRegister xmm14 = { 14 }; 176const XMMRegister xmm15 = { 15 }; 177 178enum Condition { 179 // any value < 0 is considered no_condition 180 no_condition = -1, 181 182 overflow = 0, 183 no_overflow = 1, 184 below = 2, 185 above_equal = 3, 186 equal = 4, 187 not_equal = 5, 188 below_equal = 6, 189 above = 7, 190 negative = 8, 191 positive = 9, 192 parity_even = 10, 193 parity_odd = 11, 194 less = 12, 195 greater_equal = 13, 196 less_equal = 14, 197 greater = 15, 198 199 // Fake conditions that are handled by the 200 // opcodes using them. 201 always = 16, 202 never = 17, 203 // aliases 204 carry = below, 205 not_carry = above_equal, 206 zero = equal, 207 not_zero = not_equal, 208 sign = negative, 209 not_sign = positive, 210 last_condition = greater 211}; 212 213 214// Returns the equivalent of !cc. 215// Negation of the default no_condition (-1) results in a non-default 216// no_condition value (-2). As long as tests for no_condition check 217// for condition < 0, this will work as expected. 218inline Condition NegateCondition(Condition cc) { 219 return static_cast<Condition>(cc ^ 1); 220} 221 222 223// Corresponds to transposing the operands of a comparison. 224inline Condition ReverseCondition(Condition cc) { 225 switch (cc) { 226 case below: 227 return above; 228 case above: 229 return below; 230 case above_equal: 231 return below_equal; 232 case below_equal: 233 return above_equal; 234 case less: 235 return greater; 236 case greater: 237 return less; 238 case greater_equal: 239 return less_equal; 240 case less_equal: 241 return greater_equal; 242 default: 243 return cc; 244 }; 245} 246 247 248enum Hint { 249 no_hint = 0, 250 not_taken = 0x2e, 251 taken = 0x3e 252}; 253 254// The result of negating a hint is as if the corresponding condition 255// were negated by NegateCondition. That is, no_hint is mapped to 256// itself and not_taken and taken are mapped to each other. 257inline Hint NegateHint(Hint hint) { 258 return (hint == no_hint) 259 ? no_hint 260 : ((hint == not_taken) ? taken : not_taken); 261} 262 263 264// ----------------------------------------------------------------------------- 265// Machine instruction Immediates 266 267class Immediate BASE_EMBEDDED { 268 public: 269 explicit Immediate(int32_t value) : value_(value) {} 270 271 private: 272 int32_t value_; 273 274 friend class Assembler; 275}; 276 277 278// ----------------------------------------------------------------------------- 279// Machine instruction Operands 280 281enum ScaleFactor { 282 times_1 = 0, 283 times_2 = 1, 284 times_4 = 2, 285 times_8 = 3, 286 times_int_size = times_4, 287 times_pointer_size = times_8 288}; 289 290 291class Operand BASE_EMBEDDED { 292 public: 293 // [base + disp/r] 294 Operand(Register base, int32_t disp); 295 296 // [base + index*scale + disp/r] 297 Operand(Register base, 298 Register index, 299 ScaleFactor scale, 300 int32_t disp); 301 302 // [index*scale + disp/r] 303 Operand(Register index, 304 ScaleFactor scale, 305 int32_t disp); 306 307 // Offset from existing memory operand. 308 // Offset is added to existing displacement as 32-bit signed values and 309 // this must not overflow. 310 Operand(const Operand& base, int32_t offset); 311 312 private: 313 byte rex_; 314 byte buf_[6]; 315 // The number of bytes in buf_. 316 unsigned int len_; 317 318 // Set the ModR/M byte without an encoded 'reg' register. The 319 // register is encoded later as part of the emit_operand operation. 320 // set_modrm can be called before or after set_sib and set_disp*. 321 inline void set_modrm(int mod, Register rm); 322 323 // Set the SIB byte if one is needed. Sets the length to 2 rather than 1. 324 inline void set_sib(ScaleFactor scale, Register index, Register base); 325 326 // Adds operand displacement fields (offsets added to the memory address). 327 // Needs to be called after set_sib, not before it. 328 inline void set_disp8(int disp); 329 inline void set_disp32(int disp); 330 331 friend class Assembler; 332}; 333 334 335// CpuFeatures keeps track of which features are supported by the target CPU. 336// Supported features must be enabled by a Scope before use. 337// Example: 338// if (CpuFeatures::IsSupported(SSE3)) { 339// CpuFeatures::Scope fscope(SSE3); 340// // Generate SSE3 floating point code. 341// } else { 342// // Generate standard x87 or SSE2 floating point code. 343// } 344class CpuFeatures : public AllStatic { 345 public: 346 // Detect features of the target CPU. Set safe defaults if the serializer 347 // is enabled (snapshots must be portable). 348 static void Probe(); 349 // Check whether a feature is supported by the target CPU. 350 static bool IsSupported(CpuFeature f) { 351 if (f == SSE2 && !FLAG_enable_sse2) return false; 352 if (f == SSE3 && !FLAG_enable_sse3) return false; 353 if (f == CMOV && !FLAG_enable_cmov) return false; 354 if (f == RDTSC && !FLAG_enable_rdtsc) return false; 355 if (f == SAHF && !FLAG_enable_sahf) return false; 356 return (supported_ & (V8_UINT64_C(1) << f)) != 0; 357 } 358 // Check whether a feature is currently enabled. 359 static bool IsEnabled(CpuFeature f) { 360 return (enabled_ & (V8_UINT64_C(1) << f)) != 0; 361 } 362 // Enable a specified feature within a scope. 363 class Scope BASE_EMBEDDED { 364#ifdef DEBUG 365 public: 366 explicit Scope(CpuFeature f) { 367 uint64_t mask = (V8_UINT64_C(1) << f); 368 ASSERT(CpuFeatures::IsSupported(f)); 369 ASSERT(!Serializer::enabled() || (found_by_runtime_probing_ & mask) == 0); 370 old_enabled_ = CpuFeatures::enabled_; 371 CpuFeatures::enabled_ |= mask; 372 } 373 ~Scope() { CpuFeatures::enabled_ = old_enabled_; } 374 private: 375 uint64_t old_enabled_; 376#else 377 public: 378 explicit Scope(CpuFeature f) {} 379#endif 380 }; 381 private: 382 // Safe defaults include SSE2 and CMOV for X64. It is always available, if 383 // anyone checks, but they shouldn't need to check. 384 static const uint64_t kDefaultCpuFeatures = (1 << SSE2 | 1 << CMOV); 385 static uint64_t supported_; 386 static uint64_t enabled_; 387 static uint64_t found_by_runtime_probing_; 388}; 389 390 391class Assembler : public Malloced { 392 private: 393 // We check before assembling an instruction that there is sufficient 394 // space to write an instruction and its relocation information. 395 // The relocation writer's position must be kGap bytes above the end of 396 // the generated instructions. This leaves enough space for the 397 // longest possible x64 instruction, 15 bytes, and the longest possible 398 // relocation information encoding, RelocInfoWriter::kMaxLength == 16. 399 // (There is a 15 byte limit on x64 instruction length that rules out some 400 // otherwise valid instructions.) 401 // This allows for a single, fast space check per instruction. 402 static const int kGap = 32; 403 404 public: 405 // Create an assembler. Instructions and relocation information are emitted 406 // into a buffer, with the instructions starting from the beginning and the 407 // relocation information starting from the end of the buffer. See CodeDesc 408 // for a detailed comment on the layout (globals.h). 409 // 410 // If the provided buffer is NULL, the assembler allocates and grows its own 411 // buffer, and buffer_size determines the initial buffer size. The buffer is 412 // owned by the assembler and deallocated upon destruction of the assembler. 413 // 414 // If the provided buffer is not NULL, the assembler uses the provided buffer 415 // for code generation and assumes its size to be buffer_size. If the buffer 416 // is too small, a fatal error occurs. No deallocation of the buffer is done 417 // upon destruction of the assembler. 418 Assembler(void* buffer, int buffer_size); 419 ~Assembler(); 420 421 // GetCode emits any pending (non-emitted) code and fills the descriptor 422 // desc. GetCode() is idempotent; it returns the same result if no other 423 // Assembler functions are invoked in between GetCode() calls. 424 void GetCode(CodeDesc* desc); 425 426 // Read/Modify the code target in the relative branch/call instruction at pc. 427 // On the x64 architecture, we use relative jumps with a 32-bit displacement 428 // to jump to other Code objects in the Code space in the heap. 429 // Jumps to C functions are done indirectly through a 64-bit register holding 430 // the absolute address of the target. 431 // These functions convert between absolute Addresses of Code objects and 432 // the relative displacements stored in the code. 433 static inline Address target_address_at(Address pc); 434 static inline void set_target_address_at(Address pc, Address target); 435 436 // This sets the branch destination (which is in the instruction on x64). 437 // This is for calls and branches within generated code. 438 inline static void set_target_at(Address instruction_payload, 439 Address target) { 440 set_target_address_at(instruction_payload, target); 441 } 442 443 // This sets the branch destination (which is a load instruction on x64). 444 // This is for calls and branches to runtime code. 445 inline static void set_external_target_at(Address instruction_payload, 446 Address target) { 447 *reinterpret_cast<Address*>(instruction_payload) = target; 448 } 449 450 inline Handle<Object> code_target_object_handle_at(Address pc); 451 // Number of bytes taken up by the branch target in the code. 452 static const int kCallTargetSize = 4; // Use 32-bit displacement. 453 static const int kExternalTargetSize = 8; // Use 64-bit absolute. 454 // Distance between the address of the code target in the call instruction 455 // and the return address pushed on the stack. 456 static const int kCallTargetAddressOffset = 4; // Use 32-bit displacement. 457 // Distance between the start of the JS return sequence and where the 458 // 32-bit displacement of a near call would be, relative to the pushed 459 // return address. TODO: Use return sequence length instead. 460 // Should equal Debug::kX64JSReturnSequenceLength - kCallTargetAddressOffset; 461 static const int kPatchReturnSequenceAddressOffset = 13 - 4; 462 // Distance between start of patched debug break slot and where the 463 // 32-bit displacement of a near call would be, relative to the pushed 464 // return address. TODO: Use return sequence length instead. 465 // Should equal Debug::kX64JSReturnSequenceLength - kCallTargetAddressOffset; 466 static const int kPatchDebugBreakSlotAddressOffset = 13 - 4; 467 // TODO(X64): Rename this, removing the "Real", after changing the above. 468 static const int kRealPatchReturnSequenceAddressOffset = 2; 469 470 // The x64 JS return sequence is padded with int3 to make it large 471 // enough to hold a call instruction when the debugger patches it. 472 static const int kCallInstructionLength = 13; 473 static const int kJSReturnSequenceLength = 13; 474 475 // The debug break slot must be able to contain a call instruction. 476 static const int kDebugBreakSlotLength = kCallInstructionLength; 477 478 479 // --------------------------------------------------------------------------- 480 // Code generation 481 // 482 // Function names correspond one-to-one to x64 instruction mnemonics. 483 // Unless specified otherwise, instructions operate on 64-bit operands. 484 // 485 // If we need versions of an assembly instruction that operate on different 486 // width arguments, we add a single-letter suffix specifying the width. 487 // This is done for the following instructions: mov, cmp, inc, dec, 488 // add, sub, and test. 489 // There are no versions of these instructions without the suffix. 490 // - Instructions on 8-bit (byte) operands/registers have a trailing 'b'. 491 // - Instructions on 16-bit (word) operands/registers have a trailing 'w'. 492 // - Instructions on 32-bit (doubleword) operands/registers use 'l'. 493 // - Instructions on 64-bit (quadword) operands/registers use 'q'. 494 // 495 // Some mnemonics, such as "and", are the same as C++ keywords. 496 // Naming conflicts with C++ keywords are resolved by adding a trailing '_'. 497 498 // Insert the smallest number of nop instructions 499 // possible to align the pc offset to a multiple 500 // of m. m must be a power of 2. 501 void Align(int m); 502 // Aligns code to something that's optimal for a jump target for the platform. 503 void CodeTargetAlign(); 504 505 // Stack 506 void pushfq(); 507 void popfq(); 508 509 void push(Immediate value); 510 void push(Register src); 511 void push(const Operand& src); 512 void push(Label* label, RelocInfo::Mode relocation_mode); 513 514 void pop(Register dst); 515 void pop(const Operand& dst); 516 517 void enter(Immediate size); 518 void leave(); 519 520 // Moves 521 void movb(Register dst, const Operand& src); 522 void movb(Register dst, Immediate imm); 523 void movb(const Operand& dst, Register src); 524 525 // Move the low 16 bits of a 64-bit register value to a 16-bit 526 // memory location. 527 void movw(const Operand& dst, Register src); 528 529 void movl(Register dst, Register src); 530 void movl(Register dst, const Operand& src); 531 void movl(const Operand& dst, Register src); 532 void movl(const Operand& dst, Immediate imm); 533 // Load a 32-bit immediate value, zero-extended to 64 bits. 534 void movl(Register dst, Immediate imm32); 535 536 // Move 64 bit register value to 64-bit memory location. 537 void movq(const Operand& dst, Register src); 538 // Move 64 bit memory location to 64-bit register value. 539 void movq(Register dst, const Operand& src); 540 void movq(Register dst, Register src); 541 // Sign extends immediate 32-bit value to 64 bits. 542 void movq(Register dst, Immediate x); 543 // Move the offset of the label location relative to the current 544 // position (after the move) to the destination. 545 void movl(const Operand& dst, Label* src); 546 547 // Move sign extended immediate to memory location. 548 void movq(const Operand& dst, Immediate value); 549 // New x64 instructions to load a 64-bit immediate into a register. 550 // All 64-bit immediates must have a relocation mode. 551 void movq(Register dst, void* ptr, RelocInfo::Mode rmode); 552 void movq(Register dst, int64_t value, RelocInfo::Mode rmode); 553 void movq(Register dst, const char* s, RelocInfo::Mode rmode); 554 // Moves the address of the external reference into the register. 555 void movq(Register dst, ExternalReference ext); 556 void movq(Register dst, Handle<Object> handle, RelocInfo::Mode rmode); 557 558 void movsxbq(Register dst, const Operand& src); 559 void movsxwq(Register dst, const Operand& src); 560 void movsxlq(Register dst, Register src); 561 void movsxlq(Register dst, const Operand& src); 562 void movzxbq(Register dst, const Operand& src); 563 void movzxbl(Register dst, const Operand& src); 564 void movzxwq(Register dst, const Operand& src); 565 void movzxwl(Register dst, const Operand& src); 566 567 // Repeated moves. 568 569 void repmovsb(); 570 void repmovsw(); 571 void repmovsl(); 572 void repmovsq(); 573 574 // New x64 instruction to load from an immediate 64-bit pointer into RAX. 575 void load_rax(void* ptr, RelocInfo::Mode rmode); 576 void load_rax(ExternalReference ext); 577 578 // Conditional moves. 579 void cmovq(Condition cc, Register dst, Register src); 580 void cmovq(Condition cc, Register dst, const Operand& src); 581 void cmovl(Condition cc, Register dst, Register src); 582 void cmovl(Condition cc, Register dst, const Operand& src); 583 584 // Exchange two registers 585 void xchg(Register dst, Register src); 586 587 // Arithmetics 588 void addl(Register dst, Register src) { 589 arithmetic_op_32(0x03, dst, src); 590 } 591 592 void addl(Register dst, Immediate src) { 593 immediate_arithmetic_op_32(0x0, dst, src); 594 } 595 596 void addl(Register dst, const Operand& src) { 597 arithmetic_op_32(0x03, dst, src); 598 } 599 600 void addl(const Operand& dst, Immediate src) { 601 immediate_arithmetic_op_32(0x0, dst, src); 602 } 603 604 void addq(Register dst, Register src) { 605 arithmetic_op(0x03, dst, src); 606 } 607 608 void addq(Register dst, const Operand& src) { 609 arithmetic_op(0x03, dst, src); 610 } 611 612 void addq(const Operand& dst, Register src) { 613 arithmetic_op(0x01, src, dst); 614 } 615 616 void addq(Register dst, Immediate src) { 617 immediate_arithmetic_op(0x0, dst, src); 618 } 619 620 void addq(const Operand& dst, Immediate src) { 621 immediate_arithmetic_op(0x0, dst, src); 622 } 623 624 void sbbl(Register dst, Register src) { 625 arithmetic_op_32(0x1b, dst, src); 626 } 627 628 void cmpb(Register dst, Immediate src) { 629 immediate_arithmetic_op_8(0x7, dst, src); 630 } 631 632 void cmpb_al(Immediate src); 633 634 void cmpb(Register dst, Register src) { 635 arithmetic_op(0x3A, dst, src); 636 } 637 638 void cmpb(Register dst, const Operand& src) { 639 arithmetic_op(0x3A, dst, src); 640 } 641 642 void cmpb(const Operand& dst, Register src) { 643 arithmetic_op(0x38, src, dst); 644 } 645 646 void cmpb(const Operand& dst, Immediate src) { 647 immediate_arithmetic_op_8(0x7, dst, src); 648 } 649 650 void cmpw(const Operand& dst, Immediate src) { 651 immediate_arithmetic_op_16(0x7, dst, src); 652 } 653 654 void cmpw(Register dst, Immediate src) { 655 immediate_arithmetic_op_16(0x7, dst, src); 656 } 657 658 void cmpw(Register dst, const Operand& src) { 659 arithmetic_op_16(0x3B, dst, src); 660 } 661 662 void cmpw(Register dst, Register src) { 663 arithmetic_op_16(0x3B, dst, src); 664 } 665 666 void cmpw(const Operand& dst, Register src) { 667 arithmetic_op_16(0x39, src, dst); 668 } 669 670 void cmpl(Register dst, Register src) { 671 arithmetic_op_32(0x3B, dst, src); 672 } 673 674 void cmpl(Register dst, const Operand& src) { 675 arithmetic_op_32(0x3B, dst, src); 676 } 677 678 void cmpl(const Operand& dst, Register src) { 679 arithmetic_op_32(0x39, src, dst); 680 } 681 682 void cmpl(Register dst, Immediate src) { 683 immediate_arithmetic_op_32(0x7, dst, src); 684 } 685 686 void cmpl(const Operand& dst, Immediate src) { 687 immediate_arithmetic_op_32(0x7, dst, src); 688 } 689 690 void cmpq(Register dst, Register src) { 691 arithmetic_op(0x3B, dst, src); 692 } 693 694 void cmpq(Register dst, const Operand& src) { 695 arithmetic_op(0x3B, dst, src); 696 } 697 698 void cmpq(const Operand& dst, Register src) { 699 arithmetic_op(0x39, src, dst); 700 } 701 702 void cmpq(Register dst, Immediate src) { 703 immediate_arithmetic_op(0x7, dst, src); 704 } 705 706 void cmpq(const Operand& dst, Immediate src) { 707 immediate_arithmetic_op(0x7, dst, src); 708 } 709 710 void and_(Register dst, Register src) { 711 arithmetic_op(0x23, dst, src); 712 } 713 714 void and_(Register dst, const Operand& src) { 715 arithmetic_op(0x23, dst, src); 716 } 717 718 void and_(const Operand& dst, Register src) { 719 arithmetic_op(0x21, src, dst); 720 } 721 722 void and_(Register dst, Immediate src) { 723 immediate_arithmetic_op(0x4, dst, src); 724 } 725 726 void and_(const Operand& dst, Immediate src) { 727 immediate_arithmetic_op(0x4, dst, src); 728 } 729 730 void andl(Register dst, Immediate src) { 731 immediate_arithmetic_op_32(0x4, dst, src); 732 } 733 734 void andl(Register dst, Register src) { 735 arithmetic_op_32(0x23, dst, src); 736 } 737 738 void andb(Register dst, Immediate src) { 739 immediate_arithmetic_op_8(0x4, dst, src); 740 } 741 742 void decq(Register dst); 743 void decq(const Operand& dst); 744 void decl(Register dst); 745 void decl(const Operand& dst); 746 void decb(Register dst); 747 void decb(const Operand& dst); 748 749 // Sign-extends rax into rdx:rax. 750 void cqo(); 751 // Sign-extends eax into edx:eax. 752 void cdq(); 753 754 // Divide rdx:rax by src. Quotient in rax, remainder in rdx. 755 void idivq(Register src); 756 // Divide edx:eax by lower 32 bits of src. Quotient in eax, rem. in edx. 757 void idivl(Register src); 758 759 // Signed multiply instructions. 760 void imul(Register src); // rdx:rax = rax * src. 761 void imul(Register dst, Register src); // dst = dst * src. 762 void imul(Register dst, const Operand& src); // dst = dst * src. 763 void imul(Register dst, Register src, Immediate imm); // dst = src * imm. 764 // Signed 32-bit multiply instructions. 765 void imull(Register dst, Register src); // dst = dst * src. 766 void imull(Register dst, Register src, Immediate imm); // dst = src * imm. 767 768 void incq(Register dst); 769 void incq(const Operand& dst); 770 void incl(Register dst); 771 void incl(const Operand& dst); 772 773 void lea(Register dst, const Operand& src); 774 void leal(Register dst, const Operand& src); 775 776 // Multiply rax by src, put the result in rdx:rax. 777 void mul(Register src); 778 779 void neg(Register dst); 780 void neg(const Operand& dst); 781 void negl(Register dst); 782 783 void not_(Register dst); 784 void not_(const Operand& dst); 785 void notl(Register dst); 786 787 void or_(Register dst, Register src) { 788 arithmetic_op(0x0B, dst, src); 789 } 790 791 void orl(Register dst, Register src) { 792 arithmetic_op_32(0x0B, dst, src); 793 } 794 795 void or_(Register dst, const Operand& src) { 796 arithmetic_op(0x0B, dst, src); 797 } 798 799 void or_(const Operand& dst, Register src) { 800 arithmetic_op(0x09, src, dst); 801 } 802 803 void or_(Register dst, Immediate src) { 804 immediate_arithmetic_op(0x1, dst, src); 805 } 806 807 void orl(Register dst, Immediate src) { 808 immediate_arithmetic_op_32(0x1, dst, src); 809 } 810 811 void or_(const Operand& dst, Immediate src) { 812 immediate_arithmetic_op(0x1, dst, src); 813 } 814 815 void orl(const Operand& dst, Immediate src) { 816 immediate_arithmetic_op_32(0x1, dst, src); 817 } 818 819 820 void rcl(Register dst, Immediate imm8) { 821 shift(dst, imm8, 0x2); 822 } 823 824 void rol(Register dst, Immediate imm8) { 825 shift(dst, imm8, 0x0); 826 } 827 828 void rcr(Register dst, Immediate imm8) { 829 shift(dst, imm8, 0x3); 830 } 831 832 void ror(Register dst, Immediate imm8) { 833 shift(dst, imm8, 0x1); 834 } 835 836 // Shifts dst:src left by cl bits, affecting only dst. 837 void shld(Register dst, Register src); 838 839 // Shifts src:dst right by cl bits, affecting only dst. 840 void shrd(Register dst, Register src); 841 842 // Shifts dst right, duplicating sign bit, by shift_amount bits. 843 // Shifting by 1 is handled efficiently. 844 void sar(Register dst, Immediate shift_amount) { 845 shift(dst, shift_amount, 0x7); 846 } 847 848 // Shifts dst right, duplicating sign bit, by shift_amount bits. 849 // Shifting by 1 is handled efficiently. 850 void sarl(Register dst, Immediate shift_amount) { 851 shift_32(dst, shift_amount, 0x7); 852 } 853 854 // Shifts dst right, duplicating sign bit, by cl % 64 bits. 855 void sar_cl(Register dst) { 856 shift(dst, 0x7); 857 } 858 859 // Shifts dst right, duplicating sign bit, by cl % 64 bits. 860 void sarl_cl(Register dst) { 861 shift_32(dst, 0x7); 862 } 863 864 void shl(Register dst, Immediate shift_amount) { 865 shift(dst, shift_amount, 0x4); 866 } 867 868 void shl_cl(Register dst) { 869 shift(dst, 0x4); 870 } 871 872 void shll_cl(Register dst) { 873 shift_32(dst, 0x4); 874 } 875 876 void shll(Register dst, Immediate shift_amount) { 877 shift_32(dst, shift_amount, 0x4); 878 } 879 880 void shr(Register dst, Immediate shift_amount) { 881 shift(dst, shift_amount, 0x5); 882 } 883 884 void shr_cl(Register dst) { 885 shift(dst, 0x5); 886 } 887 888 void shrl_cl(Register dst) { 889 shift_32(dst, 0x5); 890 } 891 892 void shrl(Register dst, Immediate shift_amount) { 893 shift_32(dst, shift_amount, 0x5); 894 } 895 896 void store_rax(void* dst, RelocInfo::Mode mode); 897 void store_rax(ExternalReference ref); 898 899 void subq(Register dst, Register src) { 900 arithmetic_op(0x2B, dst, src); 901 } 902 903 void subq(Register dst, const Operand& src) { 904 arithmetic_op(0x2B, dst, src); 905 } 906 907 void subq(const Operand& dst, Register src) { 908 arithmetic_op(0x29, src, dst); 909 } 910 911 void subq(Register dst, Immediate src) { 912 immediate_arithmetic_op(0x5, dst, src); 913 } 914 915 void subq(const Operand& dst, Immediate src) { 916 immediate_arithmetic_op(0x5, dst, src); 917 } 918 919 void subl(Register dst, Register src) { 920 arithmetic_op_32(0x2B, dst, src); 921 } 922 923 void subl(Register dst, const Operand& src) { 924 arithmetic_op_32(0x2B, dst, src); 925 } 926 927 void subl(const Operand& dst, Immediate src) { 928 immediate_arithmetic_op_32(0x5, dst, src); 929 } 930 931 void subl(Register dst, Immediate src) { 932 immediate_arithmetic_op_32(0x5, dst, src); 933 } 934 935 void subb(Register dst, Immediate src) { 936 immediate_arithmetic_op_8(0x5, dst, src); 937 } 938 939 void testb(Register dst, Register src); 940 void testb(Register reg, Immediate mask); 941 void testb(const Operand& op, Immediate mask); 942 void testb(const Operand& op, Register reg); 943 void testl(Register dst, Register src); 944 void testl(Register reg, Immediate mask); 945 void testl(const Operand& op, Immediate mask); 946 void testq(const Operand& op, Register reg); 947 void testq(Register dst, Register src); 948 void testq(Register dst, Immediate mask); 949 950 void xor_(Register dst, Register src) { 951 if (dst.code() == src.code()) { 952 arithmetic_op_32(0x33, dst, src); 953 } else { 954 arithmetic_op(0x33, dst, src); 955 } 956 } 957 958 void xorl(Register dst, Register src) { 959 arithmetic_op_32(0x33, dst, src); 960 } 961 962 void xor_(Register dst, const Operand& src) { 963 arithmetic_op(0x33, dst, src); 964 } 965 966 void xor_(const Operand& dst, Register src) { 967 arithmetic_op(0x31, src, dst); 968 } 969 970 void xor_(Register dst, Immediate src) { 971 immediate_arithmetic_op(0x6, dst, src); 972 } 973 974 void xor_(const Operand& dst, Immediate src) { 975 immediate_arithmetic_op(0x6, dst, src); 976 } 977 978 // Bit operations. 979 void bt(const Operand& dst, Register src); 980 void bts(const Operand& dst, Register src); 981 982 // Miscellaneous 983 void clc(); 984 void cpuid(); 985 void hlt(); 986 void int3(); 987 void nop(); 988 void nop(int n); 989 void rdtsc(); 990 void ret(int imm16); 991 void setcc(Condition cc, Register reg); 992 993 // Label operations & relative jumps (PPUM Appendix D) 994 // 995 // Takes a branch opcode (cc) and a label (L) and generates 996 // either a backward branch or a forward branch and links it 997 // to the label fixup chain. Usage: 998 // 999 // Label L; // unbound label 1000 // j(cc, &L); // forward branch to unbound label 1001 // bind(&L); // bind label to the current pc 1002 // j(cc, &L); // backward branch to bound label 1003 // bind(&L); // illegal: a label may be bound only once 1004 // 1005 // Note: The same Label can be used for forward and backward branches 1006 // but it may be bound only once. 1007 1008 void bind(Label* L); // binds an unbound label L to the current code position 1009 1010 // Calls 1011 // Call near relative 32-bit displacement, relative to next instruction. 1012 void call(Label* L); 1013 void call(Handle<Code> target, RelocInfo::Mode rmode); 1014 1015 // Call near absolute indirect, address in register 1016 void call(Register adr); 1017 1018 // Call near indirect 1019 void call(const Operand& operand); 1020 1021 // Jumps 1022 // Jump short or near relative. 1023 // Use a 32-bit signed displacement. 1024 void jmp(Label* L); // unconditional jump to L 1025 void jmp(Handle<Code> target, RelocInfo::Mode rmode); 1026 1027 // Jump near absolute indirect (r64) 1028 void jmp(Register adr); 1029 1030 // Jump near absolute indirect (m64) 1031 void jmp(const Operand& src); 1032 1033 // Conditional jumps 1034 void j(Condition cc, Label* L); 1035 void j(Condition cc, Handle<Code> target, RelocInfo::Mode rmode); 1036 1037 // Floating-point operations 1038 void fld(int i); 1039 1040 void fld1(); 1041 void fldz(); 1042 void fldpi(); 1043 1044 void fld_s(const Operand& adr); 1045 void fld_d(const Operand& adr); 1046 1047 void fstp_s(const Operand& adr); 1048 void fstp_d(const Operand& adr); 1049 void fstp(int index); 1050 1051 void fild_s(const Operand& adr); 1052 void fild_d(const Operand& adr); 1053 1054 void fist_s(const Operand& adr); 1055 1056 void fistp_s(const Operand& adr); 1057 void fistp_d(const Operand& adr); 1058 1059 void fisttp_s(const Operand& adr); 1060 void fisttp_d(const Operand& adr); 1061 1062 void fabs(); 1063 void fchs(); 1064 1065 void fadd(int i); 1066 void fsub(int i); 1067 void fmul(int i); 1068 void fdiv(int i); 1069 1070 void fisub_s(const Operand& adr); 1071 1072 void faddp(int i = 1); 1073 void fsubp(int i = 1); 1074 void fsubrp(int i = 1); 1075 void fmulp(int i = 1); 1076 void fdivp(int i = 1); 1077 void fprem(); 1078 void fprem1(); 1079 1080 void fxch(int i = 1); 1081 void fincstp(); 1082 void ffree(int i = 0); 1083 1084 void ftst(); 1085 void fucomp(int i); 1086 void fucompp(); 1087 void fucomi(int i); 1088 void fucomip(); 1089 1090 void fcompp(); 1091 void fnstsw_ax(); 1092 void fwait(); 1093 void fnclex(); 1094 1095 void fsin(); 1096 void fcos(); 1097 1098 void frndint(); 1099 1100 void sahf(); 1101 1102 // SSE2 instructions 1103 void movd(XMMRegister dst, Register src); 1104 void movd(Register dst, XMMRegister src); 1105 void movq(XMMRegister dst, Register src); 1106 void movq(Register dst, XMMRegister src); 1107 void extractps(Register dst, XMMRegister src, byte imm8); 1108 1109 void movsd(const Operand& dst, XMMRegister src); 1110 void movsd(XMMRegister dst, XMMRegister src); 1111 void movsd(XMMRegister dst, const Operand& src); 1112 1113 void cvttss2si(Register dst, const Operand& src); 1114 void cvttsd2si(Register dst, const Operand& src); 1115 void cvttsd2siq(Register dst, XMMRegister src); 1116 1117 void cvtlsi2sd(XMMRegister dst, const Operand& src); 1118 void cvtlsi2sd(XMMRegister dst, Register src); 1119 void cvtqsi2sd(XMMRegister dst, const Operand& src); 1120 void cvtqsi2sd(XMMRegister dst, Register src); 1121 1122 void cvtss2sd(XMMRegister dst, XMMRegister src); 1123 1124 void addsd(XMMRegister dst, XMMRegister src); 1125 void subsd(XMMRegister dst, XMMRegister src); 1126 void mulsd(XMMRegister dst, XMMRegister src); 1127 void divsd(XMMRegister dst, XMMRegister src); 1128 1129 void xorpd(XMMRegister dst, XMMRegister src); 1130 void sqrtsd(XMMRegister dst, XMMRegister src); 1131 1132 void ucomisd(XMMRegister dst, XMMRegister src); 1133 1134 // The first argument is the reg field, the second argument is the r/m field. 1135 void emit_sse_operand(XMMRegister dst, XMMRegister src); 1136 void emit_sse_operand(XMMRegister reg, const Operand& adr); 1137 void emit_sse_operand(XMMRegister dst, Register src); 1138 void emit_sse_operand(Register dst, XMMRegister src); 1139 1140 // Use either movsd or movlpd. 1141 // void movdbl(XMMRegister dst, const Operand& src); 1142 // void movdbl(const Operand& dst, XMMRegister src); 1143 1144 // Debugging 1145 void Print(); 1146 1147 // Check the code size generated from label to here. 1148 int SizeOfCodeGeneratedSince(Label* l) { return pc_offset() - l->pos(); } 1149 1150 // Mark address of the ExitJSFrame code. 1151 void RecordJSReturn(); 1152 1153 // Mark address of a debug break slot. 1154 void RecordDebugBreakSlot(); 1155 1156 // Record a comment relocation entry that can be used by a disassembler. 1157 // Use --debug_code to enable. 1158 void RecordComment(const char* msg); 1159 1160 void RecordPosition(int pos); 1161 void RecordStatementPosition(int pos); 1162 bool WriteRecordedPositions(); 1163 1164 int pc_offset() const { return static_cast<int>(pc_ - buffer_); } 1165 int current_statement_position() const { return current_statement_position_; } 1166 int current_position() const { return current_position_; } 1167 1168 // Check if there is less than kGap bytes available in the buffer. 1169 // If this is the case, we need to grow the buffer before emitting 1170 // an instruction or relocation information. 1171 inline bool buffer_overflow() const { 1172 return pc_ >= reloc_info_writer.pos() - kGap; 1173 } 1174 1175 // Get the number of bytes available in the buffer. 1176 inline int available_space() const { 1177 return static_cast<int>(reloc_info_writer.pos() - pc_); 1178 } 1179 1180 static bool IsNop(Address addr) { return *addr == 0x90; } 1181 1182 // Avoid overflows for displacements etc. 1183 static const int kMaximalBufferSize = 512*MB; 1184 static const int kMinimalBufferSize = 4*KB; 1185 1186 private: 1187 byte* addr_at(int pos) { return buffer_ + pos; } 1188 byte byte_at(int pos) { return buffer_[pos]; } 1189 uint32_t long_at(int pos) { 1190 return *reinterpret_cast<uint32_t*>(addr_at(pos)); 1191 } 1192 void long_at_put(int pos, uint32_t x) { 1193 *reinterpret_cast<uint32_t*>(addr_at(pos)) = x; 1194 } 1195 1196 // code emission 1197 void GrowBuffer(); 1198 1199 void emit(byte x) { *pc_++ = x; } 1200 inline void emitl(uint32_t x); 1201 inline void emitq(uint64_t x, RelocInfo::Mode rmode); 1202 inline void emitw(uint16_t x); 1203 inline void emit_code_target(Handle<Code> target, RelocInfo::Mode rmode); 1204 void emit(Immediate x) { emitl(x.value_); } 1205 1206 // Emits a REX prefix that encodes a 64-bit operand size and 1207 // the top bit of both register codes. 1208 // High bit of reg goes to REX.R, high bit of rm_reg goes to REX.B. 1209 // REX.W is set. 1210 inline void emit_rex_64(XMMRegister reg, Register rm_reg); 1211 inline void emit_rex_64(Register reg, XMMRegister rm_reg); 1212 inline void emit_rex_64(Register reg, Register rm_reg); 1213 1214 // Emits a REX prefix that encodes a 64-bit operand size and 1215 // the top bit of the destination, index, and base register codes. 1216 // The high bit of reg is used for REX.R, the high bit of op's base 1217 // register is used for REX.B, and the high bit of op's index register 1218 // is used for REX.X. REX.W is set. 1219 inline void emit_rex_64(Register reg, const Operand& op); 1220 inline void emit_rex_64(XMMRegister reg, const Operand& op); 1221 1222 // Emits a REX prefix that encodes a 64-bit operand size and 1223 // the top bit of the register code. 1224 // The high bit of register is used for REX.B. 1225 // REX.W is set and REX.R and REX.X are clear. 1226 inline void emit_rex_64(Register rm_reg); 1227 1228 // Emits a REX prefix that encodes a 64-bit operand size and 1229 // the top bit of the index and base register codes. 1230 // The high bit of op's base register is used for REX.B, and the high 1231 // bit of op's index register is used for REX.X. 1232 // REX.W is set and REX.R clear. 1233 inline void emit_rex_64(const Operand& op); 1234 1235 // Emit a REX prefix that only sets REX.W to choose a 64-bit operand size. 1236 void emit_rex_64() { emit(0x48); } 1237 1238 // High bit of reg goes to REX.R, high bit of rm_reg goes to REX.B. 1239 // REX.W is clear. 1240 inline void emit_rex_32(Register reg, Register rm_reg); 1241 1242 // The high bit of reg is used for REX.R, the high bit of op's base 1243 // register is used for REX.B, and the high bit of op's index register 1244 // is used for REX.X. REX.W is cleared. 1245 inline void emit_rex_32(Register reg, const Operand& op); 1246 1247 // High bit of rm_reg goes to REX.B. 1248 // REX.W, REX.R and REX.X are clear. 1249 inline void emit_rex_32(Register rm_reg); 1250 1251 // High bit of base goes to REX.B and high bit of index to REX.X. 1252 // REX.W and REX.R are clear. 1253 inline void emit_rex_32(const Operand& op); 1254 1255 // High bit of reg goes to REX.R, high bit of rm_reg goes to REX.B. 1256 // REX.W is cleared. If no REX bits are set, no byte is emitted. 1257 inline void emit_optional_rex_32(Register reg, Register rm_reg); 1258 1259 // The high bit of reg is used for REX.R, the high bit of op's base 1260 // register is used for REX.B, and the high bit of op's index register 1261 // is used for REX.X. REX.W is cleared. If no REX bits are set, nothing 1262 // is emitted. 1263 inline void emit_optional_rex_32(Register reg, const Operand& op); 1264 1265 // As for emit_optional_rex_32(Register, Register), except that 1266 // the registers are XMM registers. 1267 inline void emit_optional_rex_32(XMMRegister reg, XMMRegister base); 1268 1269 // As for emit_optional_rex_32(Register, Register), except that 1270 // one of the registers is an XMM registers. 1271 inline void emit_optional_rex_32(XMMRegister reg, Register base); 1272 1273 // As for emit_optional_rex_32(Register, Register), except that 1274 // one of the registers is an XMM registers. 1275 inline void emit_optional_rex_32(Register reg, XMMRegister base); 1276 1277 // As for emit_optional_rex_32(Register, const Operand&), except that 1278 // the register is an XMM register. 1279 inline void emit_optional_rex_32(XMMRegister reg, const Operand& op); 1280 1281 // Optionally do as emit_rex_32(Register) if the register number has 1282 // the high bit set. 1283 inline void emit_optional_rex_32(Register rm_reg); 1284 1285 // Optionally do as emit_rex_32(const Operand&) if the operand register 1286 // numbers have a high bit set. 1287 inline void emit_optional_rex_32(const Operand& op); 1288 1289 1290 // Emit the ModR/M byte, and optionally the SIB byte and 1291 // 1- or 4-byte offset for a memory operand. Also encodes 1292 // the second operand of the operation, a register or operation 1293 // subcode, into the reg field of the ModR/M byte. 1294 void emit_operand(Register reg, const Operand& adr) { 1295 emit_operand(reg.low_bits(), adr); 1296 } 1297 1298 // Emit the ModR/M byte, and optionally the SIB byte and 1299 // 1- or 4-byte offset for a memory operand. Also used to encode 1300 // a three-bit opcode extension into the ModR/M byte. 1301 void emit_operand(int rm, const Operand& adr); 1302 1303 // Emit a ModR/M byte with registers coded in the reg and rm_reg fields. 1304 void emit_modrm(Register reg, Register rm_reg) { 1305 emit(0xC0 | reg.low_bits() << 3 | rm_reg.low_bits()); 1306 } 1307 1308 // Emit a ModR/M byte with an operation subcode in the reg field and 1309 // a register in the rm_reg field. 1310 void emit_modrm(int code, Register rm_reg) { 1311 ASSERT(is_uint3(code)); 1312 emit(0xC0 | code << 3 | rm_reg.low_bits()); 1313 } 1314 1315 // Emit the code-object-relative offset of the label's position 1316 inline void emit_code_relative_offset(Label* label); 1317 1318 // Emit machine code for one of the operations ADD, ADC, SUB, SBC, 1319 // AND, OR, XOR, or CMP. The encodings of these operations are all 1320 // similar, differing just in the opcode or in the reg field of the 1321 // ModR/M byte. 1322 void arithmetic_op_16(byte opcode, Register reg, Register rm_reg); 1323 void arithmetic_op_16(byte opcode, Register reg, const Operand& rm_reg); 1324 void arithmetic_op_32(byte opcode, Register reg, Register rm_reg); 1325 void arithmetic_op_32(byte opcode, Register reg, const Operand& rm_reg); 1326 void arithmetic_op(byte opcode, Register reg, Register rm_reg); 1327 void arithmetic_op(byte opcode, Register reg, const Operand& rm_reg); 1328 void immediate_arithmetic_op(byte subcode, Register dst, Immediate src); 1329 void immediate_arithmetic_op(byte subcode, const Operand& dst, Immediate src); 1330 // Operate on a byte in memory or register. 1331 void immediate_arithmetic_op_8(byte subcode, 1332 Register dst, 1333 Immediate src); 1334 void immediate_arithmetic_op_8(byte subcode, 1335 const Operand& dst, 1336 Immediate src); 1337 // Operate on a word in memory or register. 1338 void immediate_arithmetic_op_16(byte subcode, 1339 Register dst, 1340 Immediate src); 1341 void immediate_arithmetic_op_16(byte subcode, 1342 const Operand& dst, 1343 Immediate src); 1344 // Operate on a 32-bit word in memory or register. 1345 void immediate_arithmetic_op_32(byte subcode, 1346 Register dst, 1347 Immediate src); 1348 void immediate_arithmetic_op_32(byte subcode, 1349 const Operand& dst, 1350 Immediate src); 1351 1352 // Emit machine code for a shift operation. 1353 void shift(Register dst, Immediate shift_amount, int subcode); 1354 void shift_32(Register dst, Immediate shift_amount, int subcode); 1355 // Shift dst by cl % 64 bits. 1356 void shift(Register dst, int subcode); 1357 void shift_32(Register dst, int subcode); 1358 1359 void emit_farith(int b1, int b2, int i); 1360 1361 // labels 1362 // void print(Label* L); 1363 void bind_to(Label* L, int pos); 1364 void link_to(Label* L, Label* appendix); 1365 1366 // record reloc info for current pc_ 1367 void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data = 0); 1368 1369 friend class CodePatcher; 1370 friend class EnsureSpace; 1371 friend class RegExpMacroAssemblerX64; 1372 1373 // Code buffer: 1374 // The buffer into which code and relocation info are generated. 1375 byte* buffer_; 1376 int buffer_size_; 1377 // True if the assembler owns the buffer, false if buffer is external. 1378 bool own_buffer_; 1379 // A previously allocated buffer of kMinimalBufferSize bytes, or NULL. 1380 static byte* spare_buffer_; 1381 1382 // code generation 1383 byte* pc_; // the program counter; moves forward 1384 RelocInfoWriter reloc_info_writer; 1385 1386 List< Handle<Code> > code_targets_; 1387 // push-pop elimination 1388 byte* last_pc_; 1389 1390 // source position information 1391 int current_statement_position_; 1392 int current_position_; 1393 int written_statement_position_; 1394 int written_position_; 1395}; 1396 1397 1398// Helper class that ensures that there is enough space for generating 1399// instructions and relocation information. The constructor makes 1400// sure that there is enough space and (in debug mode) the destructor 1401// checks that we did not generate too much. 1402class EnsureSpace BASE_EMBEDDED { 1403 public: 1404 explicit EnsureSpace(Assembler* assembler) : assembler_(assembler) { 1405 if (assembler_->buffer_overflow()) assembler_->GrowBuffer(); 1406#ifdef DEBUG 1407 space_before_ = assembler_->available_space(); 1408#endif 1409 } 1410 1411#ifdef DEBUG 1412 ~EnsureSpace() { 1413 int bytes_generated = space_before_ - assembler_->available_space(); 1414 ASSERT(bytes_generated < assembler_->kGap); 1415 } 1416#endif 1417 1418 private: 1419 Assembler* assembler_; 1420#ifdef DEBUG 1421 int space_before_; 1422#endif 1423}; 1424 1425} } // namespace v8::internal 1426 1427#endif // V8_X64_ASSEMBLER_X64_H_ 1428