1
2/*---------------------------------------------------------------*/
3/*--- begin                                   host_ppc_defs.h ---*/
4/*---------------------------------------------------------------*/
5
6/*
7   This file is part of Valgrind, a dynamic binary instrumentation
8   framework.
9
10   Copyright (C) 2004-2017 OpenWorks LLP
11      info@open-works.net
12
13   This program is free software; you can redistribute it and/or
14   modify it under the terms of the GNU General Public License as
15   published by the Free Software Foundation; either version 2 of the
16   License, or (at your option) any later version.
17
18   This program is distributed in the hope that it will be useful, but
19   WITHOUT ANY WARRANTY; without even the implied warranty of
20   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
21   General Public License for more details.
22
23   You should have received a copy of the GNU General Public License
24   along with this program; if not, write to the Free Software
25   Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
26   02110-1301, USA.
27
28   The GNU General Public License is contained in the file COPYING.
29
30   Neither the names of the U.S. Department of Energy nor the
31   University of California nor the names of its contributors may be
32   used to endorse or promote products derived from this software
33   without prior written permission.
34*/
35
36#ifndef __VEX_HOST_PPC_DEFS_H
37#define __VEX_HOST_PPC_DEFS_H
38
39#include "libvex_basictypes.h"
40#include "libvex.h"                      // VexArch
41#include "host_generic_regs.h"           // HReg
42
43
44/* --------- Registers. --------- */
45
46#define ST_IN static inline
47
48#define GPR(_mode64, _enc, _ix64, _ix32) \
49  mkHReg(False,  (_mode64) ? HRcInt64 : HRcInt32, \
50         (_enc), (_mode64) ? (_ix64) : (_ix32))
51
52#define FPR(_mode64, _enc, _ix64, _ix32) \
53  mkHReg(False,  HRcFlt64, \
54         (_enc), (_mode64) ? (_ix64) : (_ix32))
55
56#define VR(_mode64, _enc, _ix64, _ix32) \
57  mkHReg(False,  HRcVec128, \
58         (_enc), (_mode64) ? (_ix64) : (_ix32))
59
60ST_IN HReg hregPPC_GPR3  ( Bool mode64 ) { return GPR(mode64,  3,   0,  0); }
61ST_IN HReg hregPPC_GPR4  ( Bool mode64 ) { return GPR(mode64,  4,   1,  1); }
62ST_IN HReg hregPPC_GPR5  ( Bool mode64 ) { return GPR(mode64,  5,   2,  2); }
63ST_IN HReg hregPPC_GPR6  ( Bool mode64 ) { return GPR(mode64,  6,   3,  3); }
64ST_IN HReg hregPPC_GPR7  ( Bool mode64 ) { return GPR(mode64,  7,   4,  4); }
65ST_IN HReg hregPPC_GPR8  ( Bool mode64 ) { return GPR(mode64,  8,   5,  5); }
66ST_IN HReg hregPPC_GPR9  ( Bool mode64 ) { return GPR(mode64,  9,   6,  6); }
67ST_IN HReg hregPPC_GPR10 ( Bool mode64 ) { return GPR(mode64, 10,   7,  7); }
68
69// r11 and r12 are only allocatable in 32-bit mode.  Hence the 64-bit
70// index numbering doesn't advance for these two.
71ST_IN HReg hregPPC_GPR11 ( Bool mode64 ) { return GPR(mode64, 11,   0,  8); }
72ST_IN HReg hregPPC_GPR12 ( Bool mode64 ) { return GPR(mode64, 12,   0,  9); }
73
74ST_IN HReg hregPPC_GPR14 ( Bool mode64 ) { return GPR(mode64, 14,   8, 10); }
75ST_IN HReg hregPPC_GPR15 ( Bool mode64 ) { return GPR(mode64, 15,   9, 11); }
76ST_IN HReg hregPPC_GPR16 ( Bool mode64 ) { return GPR(mode64, 16,  10, 12); }
77ST_IN HReg hregPPC_GPR17 ( Bool mode64 ) { return GPR(mode64, 17,  11, 13); }
78ST_IN HReg hregPPC_GPR18 ( Bool mode64 ) { return GPR(mode64, 18,  12, 14); }
79ST_IN HReg hregPPC_GPR19 ( Bool mode64 ) { return GPR(mode64, 19,  13, 15); }
80ST_IN HReg hregPPC_GPR20 ( Bool mode64 ) { return GPR(mode64, 20,  14, 16); }
81ST_IN HReg hregPPC_GPR21 ( Bool mode64 ) { return GPR(mode64, 21,  15, 17); }
82ST_IN HReg hregPPC_GPR22 ( Bool mode64 ) { return GPR(mode64, 22,  16, 18); }
83ST_IN HReg hregPPC_GPR23 ( Bool mode64 ) { return GPR(mode64, 23,  17, 19); }
84ST_IN HReg hregPPC_GPR24 ( Bool mode64 ) { return GPR(mode64, 24,  18, 20); }
85ST_IN HReg hregPPC_GPR25 ( Bool mode64 ) { return GPR(mode64, 25,  19, 21); }
86ST_IN HReg hregPPC_GPR26 ( Bool mode64 ) { return GPR(mode64, 26,  20, 22); }
87ST_IN HReg hregPPC_GPR27 ( Bool mode64 ) { return GPR(mode64, 27,  21, 23); }
88ST_IN HReg hregPPC_GPR28 ( Bool mode64 ) { return GPR(mode64, 28,  22, 24); }
89
90ST_IN HReg hregPPC_FPR14 ( Bool mode64 ) { return FPR(mode64, 14,  23, 25); }
91ST_IN HReg hregPPC_FPR15 ( Bool mode64 ) { return FPR(mode64, 15,  24, 26); }
92ST_IN HReg hregPPC_FPR16 ( Bool mode64 ) { return FPR(mode64, 16,  25, 27); }
93ST_IN HReg hregPPC_FPR17 ( Bool mode64 ) { return FPR(mode64, 17,  26, 28); }
94ST_IN HReg hregPPC_FPR18 ( Bool mode64 ) { return FPR(mode64, 18,  27, 29); }
95ST_IN HReg hregPPC_FPR19 ( Bool mode64 ) { return FPR(mode64, 19,  28, 30); }
96ST_IN HReg hregPPC_FPR20 ( Bool mode64 ) { return FPR(mode64, 20,  29, 31); }
97ST_IN HReg hregPPC_FPR21 ( Bool mode64 ) { return FPR(mode64, 21,  30, 32); }
98
99ST_IN HReg hregPPC_VR20  ( Bool mode64 ) { return VR (mode64, 20,  31, 33); }
100ST_IN HReg hregPPC_VR21  ( Bool mode64 ) { return VR (mode64, 21,  32, 34); }
101ST_IN HReg hregPPC_VR22  ( Bool mode64 ) { return VR (mode64, 22,  33, 35); }
102ST_IN HReg hregPPC_VR23  ( Bool mode64 ) { return VR (mode64, 23,  34, 36); }
103ST_IN HReg hregPPC_VR24  ( Bool mode64 ) { return VR (mode64, 24,  35, 37); }
104ST_IN HReg hregPPC_VR25  ( Bool mode64 ) { return VR (mode64, 25,  36, 38); }
105ST_IN HReg hregPPC_VR26  ( Bool mode64 ) { return VR (mode64, 26,  37, 39); }
106ST_IN HReg hregPPC_VR27  ( Bool mode64 ) { return VR (mode64, 27,  38, 40); }
107
108ST_IN HReg hregPPC_GPR1  ( Bool mode64 ) { return GPR(mode64,  1,  39, 41); }
109ST_IN HReg hregPPC_GPR29 ( Bool mode64 ) { return GPR(mode64, 29,  40, 42); }
110ST_IN HReg hregPPC_GPR30 ( Bool mode64 ) { return GPR(mode64, 30,  41, 43); }
111ST_IN HReg hregPPC_GPR31 ( Bool mode64 ) { return GPR(mode64, 31,  42, 44); }
112ST_IN HReg hregPPC_VR29  ( Bool mode64 ) { return VR (mode64, 29,  43, 45); }
113
114#undef ST_IN
115#undef GPR
116#undef FPR
117#undef VR
118
119#define StackFramePtr(_mode64) hregPPC_GPR1(_mode64)
120#define GuestStatePtr(_mode64) hregPPC_GPR31(_mode64)
121
122/* Num registers used for function calls */
123#define PPC_N_REGPARMS 8
124
125extern void ppHRegPPC ( HReg );
126
127
128/* --------- Condition codes --------- */
129
130/* This gives names from bitfields in CR; hence it names BI numbers */
131/* Using IBM/hardware indexing convention */
132typedef
133   enum {
134      // CR7, which we use for integer compares
135      Pcf_7LT  = 28,  /* neg  | lt          */
136      Pcf_7GT  = 29,  /* pos  | gt          */
137      Pcf_7EQ  = 30,  /* zero | equal       */
138      Pcf_7SO  = 31,  /* summary overflow   */
139      Pcf_NONE = 32   /* no condition; used with Pct_ALWAYS */
140   }
141   PPCCondFlag;
142
143typedef
144   enum {   /* Maps bc bitfield BO */
145      Pct_FALSE  = 0x4, /* associated PPCCondFlag must not be Pcf_NONE */
146      Pct_TRUE   = 0xC, /* associated PPCCondFlag must not be Pcf_NONE */
147      Pct_ALWAYS = 0x14 /* associated PPCCondFlag must be Pcf_NONE */
148   }
149   PPCCondTest;
150
151typedef
152   struct {
153      PPCCondFlag flag;
154      PPCCondTest test;
155   }
156   PPCCondCode;
157
158extern const HChar* showPPCCondCode ( PPCCondCode );
159
160/* constructor */
161extern PPCCondCode mk_PPCCondCode ( PPCCondTest, PPCCondFlag );
162
163/* false->true, true->false */
164extern PPCCondTest invertCondTest ( PPCCondTest );
165
166
167
168
169/* --------- Memory address expressions (amodes). --------- */
170
171typedef
172   enum {
173     Pam_IR=1,      /* Immediate (signed 16-bit) + Reg */
174     Pam_RR=2       /* Reg1 + Reg2     */
175   }
176   PPCAModeTag;
177
178typedef
179   struct {
180      PPCAModeTag tag;
181      union {
182         struct {
183            HReg base;
184            Int  index;
185         } IR;
186         struct {
187            HReg base;
188            HReg index;
189         } RR;
190      } Pam;
191   }
192   PPCAMode;
193
194extern PPCAMode* PPCAMode_IR ( Int,  HReg );
195extern PPCAMode* PPCAMode_RR ( HReg, HReg );
196
197extern PPCAMode* dopyPPCAMode ( PPCAMode* );
198
199extern void ppPPCAMode ( PPCAMode* );
200
201
202/* --------- Operand, which can be a reg or a u16/s16. --------- */
203/* ("RH" == "Register or Halfword immediate") */
204typedef
205   enum {
206      Prh_Imm=3,
207      Prh_Reg=4
208   }
209   PPCRHTag;
210
211typedef
212   struct {
213      PPCRHTag tag;
214      union {
215         struct {
216            Bool   syned;
217            UShort imm16;
218         } Imm;
219         struct {
220            HReg reg;
221         } Reg;
222      }
223      Prh;
224   }
225   PPCRH;
226
227extern PPCRH* PPCRH_Imm ( Bool, UShort );
228extern PPCRH* PPCRH_Reg ( HReg );
229
230extern void ppPPCRH ( PPCRH* );
231
232
233/* --------- Operand, which can be a reg or a u32/64. --------- */
234
235typedef
236   enum {
237      Pri_Imm=5,
238      Pri_Reg=6
239   }
240   PPCRITag;
241
242typedef
243   struct {
244      PPCRITag tag;
245      union {
246         ULong Imm;
247         HReg  Reg;
248      }
249      Pri;
250   }
251   PPCRI;
252
253extern PPCRI* PPCRI_Imm ( ULong );
254extern PPCRI* PPCRI_Reg( HReg );
255
256extern void ppPPCRI ( PPCRI* );
257
258
259/* --------- Operand, which can be a vector reg or a s6. --------- */
260/* ("VI" == "Vector Register or Immediate") */
261typedef
262   enum {
263      Pvi_Imm=7,
264      Pvi_Reg=8
265   }
266   PPCVI5sTag;
267
268typedef
269   struct {
270      PPCVI5sTag tag;
271      union {
272         Char Imm5s;
273         HReg Reg;
274      }
275      Pvi;
276   }
277   PPCVI5s;
278
279extern PPCVI5s* PPCVI5s_Imm ( Char );
280extern PPCVI5s* PPCVI5s_Reg ( HReg );
281
282extern void ppPPCVI5s ( PPCVI5s* );
283
284
285/* --------- Instructions. --------- */
286
287/* --------- */
288typedef
289   enum {
290      Pun_NEG,
291      Pun_NOT,
292      Pun_CLZ32,
293      Pun_CLZ64,
294      Pun_CTZ32,
295      Pun_CTZ64,
296      Pun_EXTSW
297   }
298   PPCUnaryOp;
299
300extern const HChar* showPPCUnaryOp ( PPCUnaryOp );
301
302
303/* --------- */
304typedef
305   enum {
306      Palu_INVALID,
307      Palu_ADD, Palu_SUB,
308      Palu_AND, Palu_OR, Palu_XOR,
309   }
310   PPCAluOp;
311
312extern
313const HChar* showPPCAluOp ( PPCAluOp,
314                            Bool /* is the 2nd operand an immediate? */);
315
316
317/* --------- */
318typedef
319   enum {
320      Pshft_INVALID,
321      Pshft_SHL, Pshft_SHR, Pshft_SAR,
322   }
323   PPCShftOp;
324
325extern
326const HChar* showPPCShftOp ( PPCShftOp,
327                             Bool /* is the 2nd operand an immediate? */,
328                             Bool /* is this a 32bit or 64bit op? */ );
329
330
331/* --------- */
332typedef
333   enum {
334      Pfp_INVALID,
335
336      /* Ternary */
337      Pfp_MADDD,  Pfp_MSUBD,
338      Pfp_MADDS,  Pfp_MSUBS,
339      Pfp_FPADDQ, Pfp_FPADDQRNDODD,
340      Pfp_FPSUBQ, Pfp_FPSUBQRNDODD,
341      Pfp_FPMULQ, Pfp_FPMULQRNDODD,
342      Pfp_FPDIVQ, Pfp_FPDIVQRNDODD,
343      Pfp_FPMULADDQ, Pfp_FPMULADDQRNDODD,
344      Pfp_FPMULSUBQ, Pfp_FPMULSUBQRNDODD,
345      Pfp_FPNEGMULADDQ, Pfp_FPNEGMULADDQRNDODD,
346      Pfp_FPNEGMULSUBQ, Pfp_FPNEGMULSUBQRNDODD,
347      Pfp_FPSQRTQ, Pfp_FPSQRTQRNDODD,
348      Pfp_FPQTOD, Pfp_FPQTODRNDODD,
349      Pfp_FPQTOW, Pfp_FPQTOWRNDODD,
350      Pfp_FPDTOQ,
351      Pfp_IDSTOQ,
352      Pfp_IDUTOQ,
353      Pfp_TRUNCFPQTOISD,
354      Pfp_TRUNCFPQTOISW,
355      Pfp_TRUNCFPQTOIUD,
356      Pfp_TRUNCFPQTOIUW,
357      Pfp_DFPADD, Pfp_DFPADDQ,
358      Pfp_DFPSUB, Pfp_DFPSUBQ,
359      Pfp_DFPMUL, Pfp_DFPMULQ,
360      Pfp_DFPDIV, Pfp_DFPDIVQ,
361      Pfp_DQUAQ,  Pfp_DRRNDQ,
362
363      /* Binary */
364      Pfp_ADDD, Pfp_SUBD, Pfp_MULD, Pfp_DIVD,
365      Pfp_ADDS, Pfp_SUBS, Pfp_MULS, Pfp_DIVS,
366      Pfp_DRSP, Pfp_DRDPQ, Pfp_DCTFIX, Pfp_DCTFIXQ, Pfp_DCFFIX,
367      Pfp_DQUA, Pfp_RRDTR, Pfp_DIEX, Pfp_DIEXQ, Pfp_DRINTN,
368
369      /* Unary */
370      Pfp_SQRT, Pfp_ABS, Pfp_NEG, Pfp_MOV, Pfp_RES, Pfp_RSQRTE,
371      Pfp_FRIN, Pfp_FRIM, Pfp_FRIP, Pfp_FRIZ,
372      Pfp_DSCLI, Pfp_DSCRI, Pfp_DSCLIQ, Pfp_DSCRIQ, Pfp_DCTDP,
373      Pfp_DCTQPQ, Pfp_DCFFIXQ, Pfp_DXEX, Pfp_DXEXQ,
374
375   }
376   PPCFpOp;
377
378extern const HChar* showPPCFpOp ( PPCFpOp );
379
380
381/* --------- */
382typedef
383   enum {
384      Pav_INVALID,
385
386      /* Integer Unary */
387      Pav_MOV,                             /* Mov */
388      Pav_NOT,                             /* Bitwise */
389      Pav_UNPCKH8S,  Pav_UNPCKH16S,        /* Unpack */
390      Pav_UNPCKL8S,  Pav_UNPCKL16S,
391      Pav_UNPCKHPIX, Pav_UNPCKLPIX,
392
393      /* Integer Binary */
394      Pav_AND, Pav_OR, Pav_XOR,            /* Bitwise */
395      Pav_ADDU, Pav_QADDU, Pav_QADDS,
396      Pav_SUBU, Pav_QSUBU, Pav_QSUBS,
397      Pav_MULU,
398      Pav_OMULU, Pav_OMULS, Pav_EMULU, Pav_EMULS,
399      Pav_AVGU, Pav_AVGS,
400      Pav_MAXU, Pav_MAXS,
401      Pav_MINU, Pav_MINS,
402
403      /* Compare (always affects CR field 6) */
404      Pav_CMPEQU, Pav_CMPGTU, Pav_CMPGTS,
405
406      /* Shift */
407      Pav_SHL, Pav_SHR, Pav_SAR, Pav_ROTL,
408
409      /* Pack */
410      Pav_PACKUU, Pav_QPACKUU, Pav_QPACKSU, Pav_QPACKSS,
411      Pav_PACKPXL,
412
413      /* Merge */
414      Pav_MRGHI, Pav_MRGLO,
415
416      /* Concatenation */
417      Pav_CATODD, Pav_CATEVEN,
418
419      /* Polynomial Multipy-Add */
420      Pav_POLYMULADD,
421
422      /* Cipher */
423      Pav_CIPHERV128, Pav_CIPHERLV128, Pav_NCIPHERV128, Pav_NCIPHERLV128,
424      Pav_CIPHERSUBV128,
425
426      /* Hash */
427      Pav_SHA256, Pav_SHA512,
428
429      /* BCD Arithmetic */
430      Pav_BCDAdd, Pav_BCDSub,
431
432      /* Conversion signed 128-bit value to signed BCD 128-bit */
433      Pav_I128StoBCD128,
434
435      /* Conversion signed BCD 128-bit to signed 128-bit value */
436      Pav_BCD128toI128S,
437
438      /* zero count */
439      Pav_ZEROCNTBYTE, Pav_ZEROCNTWORD, Pav_ZEROCNTHALF, Pav_ZEROCNTDBL,
440
441      /* trailing zero count */
442      Pav_TRAILINGZEROCNTBYTE, Pav_TRAILINGZEROCNTWORD,
443      Pav_TRAILINGZEROCNTHALF, Pav_TRAILINGZEROCNTDBL,
444
445      /* Vector bit matrix transpose by byte */
446      Pav_BITMTXXPOSE,
447
448      /* Vector Half-precision format to single precision conversion */
449      Pav_F16toF32x4,
450
451      /* Vector Single precision format to Half-precision conversion */
452      Pav_F32toF16x4,
453
454      /* Vector Half-precision format to Double precision conversion */
455      Pav_F16toF64x2,
456
457      /* Vector Double precision format to Half-precision conversion */
458      Pav_F64toF16x2,
459
460      /* 128 bit mult by 10 */
461      Pav_MulI128by10,
462
463      /* 128 bit mult by 10, carry out */
464      Pav_MulI128by10Carry,
465
466      /* 128 bit mult by 10 plus carry in */
467      Pav_MulI128by10E,
468
469      /* 128 bit mult by 10 plus carry in, carry out */
470      Pav_MulI128by10ECarry,
471
472      /* F128 to I128 */
473      Pav_F128toI128S,
474
475      /* Round F128 to F128 */
476      Pav_ROUNDFPQ,
477   }
478   PPCAvOp;
479
480extern const HChar* showPPCAvOp ( PPCAvOp );
481
482
483/* --------- */
484typedef
485   enum {
486      Pavfp_INVALID,
487
488      /* Floating point binary */
489      Pavfp_ADDF, Pavfp_SUBF, Pavfp_MULF,
490      Pavfp_MAXF, Pavfp_MINF,
491      Pavfp_CMPEQF, Pavfp_CMPGTF, Pavfp_CMPGEF,
492
493      /* Floating point unary */
494      Pavfp_RCPF, Pavfp_RSQRTF,
495      Pavfp_CVTU2F, Pavfp_CVTS2F, Pavfp_QCVTF2U, Pavfp_QCVTF2S,
496      Pavfp_ROUNDM, Pavfp_ROUNDP, Pavfp_ROUNDN, Pavfp_ROUNDZ,
497   }
498   PPCAvFpOp;
499
500extern const HChar* showPPCAvFpOp ( PPCAvFpOp );
501
502
503/* --------- */
504typedef
505   enum {
506      Pin_LI,         /* load word (32/64-bit) immediate (fake insn) */
507      Pin_Alu,        /* word add/sub/and/or/xor */
508      Pin_Shft,       /* word shl/shr/sar */
509      Pin_AddSubC,    /* add/sub with read/write carry */
510      Pin_Cmp,        /* word compare */
511      Pin_Unary,      /* not, neg, clz */
512      Pin_MulL,       /* widening multiply */
513      Pin_Div,        /* div */
514      Pin_Call,       /* call to address in register */
515      Pin_XDirect,    /* direct transfer to GA */
516      Pin_XIndir,     /* indirect transfer to GA */
517      Pin_XAssisted,  /* assisted transfer to GA */
518      Pin_CMov,       /* conditional move */
519      Pin_Load,       /* zero-extending load a 8|16|32|64 bit value from mem */
520      Pin_LoadL,      /* load-linked (lwarx/ldarx) 32|64 bit value from mem */
521      Pin_Store,      /* store a 8|16|32|64 bit value to mem */
522      Pin_StoreC,     /* store-conditional (stwcx./stdcx.) 32|64 bit val */
523      Pin_Set,        /* convert condition code to value 0 or 1 */
524      Pin_MfCR,       /* move from condition register to GPR */
525      Pin_MFence,     /* mem fence */
526
527      Pin_FpUnary,    /* FP unary op */
528      Pin_FpBinary,   /* FP binary op */
529      Pin_Fp128Unary,   /* FP unary op for 128-bit floating point */
530      Pin_Fp128Binary,  /* FP binary op for 128-bit floating point */
531      Pin_Fp128Trinary, /* FP trinary op for 128-bit floating point */
532      Pin_FpMulAcc,   /* FP multipy-accumulate style op */
533      Pin_FpLdSt,     /* FP load/store */
534      Pin_FpSTFIW,    /* stfiwx */
535      Pin_FpRSP,      /* FP round IEEE754 double to IEEE754 single */
536      Pin_FpCftI,     /* fcfid[u,s,us]/fctid[u]/fctiw[u] */
537      Pin_FpCMov,     /* FP floating point conditional move */
538      Pin_FpLdFPSCR,  /* mtfsf */
539      Pin_FpCmp,      /* FP compare, generating value into int reg */
540
541      Pin_RdWrLR,     /* Read/Write Link Register */
542
543      Pin_AvLdSt,     /* AV load/store (kludging for AMode_IR) */
544      Pin_AvUnary,    /* AV unary general reg=>reg */
545
546      Pin_AvBinary,   /* AV binary general reg,reg=>reg */
547      Pin_AvBinaryInt,/* AV binary  reg,int=>reg */
548      Pin_AvBin8x16,  /* AV binary, 8x4 */
549      Pin_AvBin16x8,  /* AV binary, 16x4 */
550      Pin_AvBin32x4,  /* AV binary, 32x4 */
551      Pin_AvBin64x2,  /* AV binary, 64x2 */
552
553      Pin_AvBin32Fx4, /* AV FP binary, 32Fx4 */
554      Pin_AvUn32Fx4,  /* AV FP unary,  32Fx4 */
555
556      Pin_AvPerm,     /* AV permute (shuffle) */
557      Pin_AvSel,      /* AV select */
558      Pin_AvSh,       /* AV shift left or right */
559      Pin_AvShlDbl,   /* AV shift-left double by imm */
560      Pin_AvSplat,    /* One elem repeated throughout dst */
561      Pin_AvLdVSCR,   /* mtvscr */
562      Pin_AvCMov,     /* AV conditional move */
563      Pin_AvCipherV128Unary,  /* AV Vector unary Cipher */
564      Pin_AvCipherV128Binary, /* AV Vector binary Cipher */
565      Pin_AvHashV128Binary, /* AV Vector binary Hash */
566      Pin_AvBCDV128Binary,  /* BCD Arithmetic */
567      Pin_Dfp64Unary,   /* DFP64  unary op */
568      Pin_Dfp128Unary,  /* DFP128 unary op */
569      Pin_DfpShift,     /* Decimal floating point shift by immediate value */
570      Pin_Dfp64Binary,  /* DFP64  binary op */
571      Pin_Dfp128Binary, /* DFP128 binary op */
572      Pin_DfpShift128,  /* 128-bit Decimal floating point shift by
573                         * immediate value */
574      Pin_DfpD128toD64, /* DFP 128 to DFP 64 op */
575      Pin_DfpI64StoD128, /* DFP signed integer to DFP 128 */
576      Pin_DfpRound,       /* D64 round to D64 */
577      Pin_DfpRound128,    /* D128 round to D128 */
578      Pin_ExtractExpD128, /* DFP, extract 64 bit exponent */
579      Pin_InsertExpD128,  /* DFP, insert 64 bit exponent and 128 bit binary
580                           * significand into a DFP 128-bit value*/
581      Pin_Dfp64Cmp,       /* DFP 64-bit compare, generating value into
582                           * int reg */
583      Pin_Dfp128Cmp,      /* DFP 128-bit  compare, generating value into
584                           * int reg */
585      Pin_DfpQuantize,    /* D64 quantize using register value, significance
586                           * round */
587      Pin_DfpQuantize128, /* D128 quantize using register value, significance
588                           * round */
589      Pin_EvCheck,    /* Event check */
590      Pin_ProfInc     /* 64-bit profile counter increment */
591   }
592   PPCInstrTag;
593
594/* Destinations are on the LEFT (first operand) */
595
596typedef
597   struct {
598      PPCInstrTag tag;
599      union {
600         /* Get a 32/64-bit literal into a register.
601            May turn into a number of real insns. */
602         struct {
603            HReg dst;
604            ULong imm64;
605         } LI;
606         /* Integer add/sub/and/or/xor.  Limitations:
607            - For add, the immediate, if it exists, is a signed 16.
608            - For sub, the immediate, if it exists, is a signed 16
609              which may not be -32768, since no such instruction
610              exists, and so we have to emit addi with +32768, but
611              that is not possible.
612            - For and/or/xor,  the immediate, if it exists,
613              is an unsigned 16.
614         */
615         struct {
616            PPCAluOp op;
617            HReg     dst;
618            HReg     srcL;
619            PPCRH*   srcR;
620         } Alu;
621         /* Integer shl/shr/sar.
622            Limitations: the immediate, if it exists,
623            is a signed 5-bit value between 1 and 31 inclusive.
624         */
625         struct {
626            PPCShftOp op;
627            Bool      sz32;   /* mode64 has both 32 and 64bit shft */
628            HReg      dst;
629            HReg      srcL;
630            PPCRH*    srcR;
631         } Shft;
632         /*  */
633         struct {
634            Bool isAdd;  /* else sub */
635            Bool setC;   /* else read carry */
636            HReg dst;
637            HReg srcL;
638            HReg srcR;
639         } AddSubC;
640         /* If signed, the immediate, if it exists, is a signed 16,
641            else it is an unsigned 16. */
642         struct {
643            Bool   syned;
644            Bool   sz32;    /* mode64 has both 32 and 64bit cmp */
645            UInt   crfD;
646            HReg   srcL;
647            PPCRH* srcR;
648         } Cmp;
649         /* Not, Neg, Clz32/64, Extsw */
650         struct {
651            PPCUnaryOp op;
652            HReg       dst;
653            HReg       src;
654         } Unary;
655         struct {
656            Bool syned;  /* meaningless if hi32==False */
657            Bool hi;     /* False=>low, True=>high */
658            Bool sz32;   /* mode64 has both 32 & 64bit mull */
659            HReg dst;
660            HReg srcL;
661            HReg srcR;
662         } MulL;
663         /* ppc32 div/divu instruction. */
664         struct {
665            Bool extended;
666            Bool syned;
667            Bool sz32;   /* mode64 has both 32 & 64bit div */
668            HReg dst;
669            HReg srcL;
670            HReg srcR;
671         } Div;
672         /* Pseudo-insn.  Call target (an absolute address), on given
673            condition (which could be Pct_ALWAYS).  argiregs indicates
674            which of r3 .. r10 carries argument values for this call,
675            using a bit mask (1<<N is set if rN holds an arg, for N in
676            3 .. 10 inclusive). */
677         struct {
678            PPCCondCode cond;
679            Addr64      target;
680            UInt        argiregs;
681            RetLoc      rloc;     /* where the return value will be */
682         } Call;
683         /* Update the guest CIA value, then exit requesting to chain
684            to it.  May be conditional.  Use of Addr64 in order to cope
685            with 64-bit hosts. */
686         struct {
687            Addr64      dstGA;    /* next guest address */
688            PPCAMode*   amCIA;    /* amode in guest state for CIA */
689            PPCCondCode cond;     /* can be ALWAYS */
690            Bool        toFastEP; /* chain to the slow or fast point? */
691         } XDirect;
692         /* Boring transfer to a guest address not known at JIT time.
693            Not chainable.  May be conditional. */
694         struct {
695            HReg        dstGA;
696            PPCAMode*   amCIA;
697            PPCCondCode cond; /* can be ALWAYS */
698         } XIndir;
699         /* Assisted transfer to a guest address, most general case.
700            Not chainable.  May be conditional. */
701         struct {
702            HReg        dstGA;
703            PPCAMode*   amCIA;
704            PPCCondCode cond; /* can be ALWAYS */
705            IRJumpKind  jk;
706         } XAssisted;
707         /* Mov src to dst on the given condition, which may not
708            be the bogus Pct_ALWAYS. */
709         struct {
710            PPCCondCode cond;
711            HReg        dst;
712            PPCRI*      src;
713         } CMov;
714         /* Zero extending loads.  Dst size is host word size */
715         struct {
716            UChar     sz; /* 1|2|4|8 */
717            HReg      dst;
718            PPCAMode* src;
719         } Load;
720         /* Load-and-reserve (lwarx, ldarx) */
721         struct {
722            UChar sz; /* 4|8 */
723            HReg  dst;
724            HReg  src;
725         } LoadL;
726         /* 64/32/16/8 bit stores */
727         struct {
728            UChar     sz; /* 1|2|4|8 */
729            PPCAMode* dst;
730            HReg      src;
731         } Store;
732         /* Store-conditional (stwcx., stdcx.) */
733         struct {
734            UChar sz; /* 4|8 */
735            HReg  dst;
736            HReg  src;
737         } StoreC;
738         /* Convert a ppc condition code to value 0 or 1. */
739         struct {
740            PPCCondCode cond;
741            HReg        dst;
742         } Set;
743         /* Move the entire CR to a GPR */
744         struct {
745            HReg dst;
746         } MfCR;
747         /* Mem fence.  In short, an insn which flushes all preceding
748            loads and stores as much as possible before continuing.
749            On PPC we emit a "sync". */
750         struct {
751         } MFence;
752
753         /* PPC Floating point */
754         struct {
755            PPCFpOp op;
756            HReg    dst;
757            HReg    src;
758         } FpUnary;
759         struct {
760            PPCFpOp op;
761            HReg    dst;
762            HReg    srcL;
763            HReg    srcR;
764         } FpBinary;
765         struct {
766            PPCFpOp op;
767            HReg dst;
768            HReg src;
769         } Fp128Unary;
770         struct {
771            PPCFpOp op;
772            HReg dst;
773            HReg srcL;
774            HReg srcR;
775         } Fp128Binary;
776         struct {
777            PPCFpOp op;
778            HReg dst;
779            HReg srcL;
780            HReg srcR;
781         } Fp128Trinary;
782         struct {
783            PPCFpOp op;
784            HReg    dst;
785            HReg    srcML;
786            HReg    srcMR;
787            HReg    srcAcc;
788         } FpMulAcc;
789         struct {
790            Bool      isLoad;
791            UChar     sz; /* only 4 (IEEE single) or 8 (IEEE double) */
792            HReg      reg;
793            PPCAMode* addr;
794         } FpLdSt;
795         struct {
796            HReg addr; /* int reg */
797            HReg data; /* float reg */
798         } FpSTFIW;
799         /* Round 64-bit FP value to 32-bit FP value in an FP reg. */
800         struct {
801            HReg src;
802            HReg dst;
803         } FpRSP;
804         /* fcfid[u,s,us]/fctid[u]/fctiw[u].  Only some combinations
805            of the various fields are allowed.  This is asserted for
806            and documented in the code for the constructor,
807            PPCInstr_FpCftI, in host_ppc_defs.c.  */
808         struct {
809            Bool fromI; /* True== I->F,    False== F->I */
810            Bool int32; /* True== I is 32, False== I is 64 */
811            Bool syned;
812            Bool flt64; /* True== F is 64, False== F is 32 */
813            HReg src;
814            HReg dst;
815         } FpCftI;
816         /* FP mov src to dst on the given condition. */
817         struct {
818            PPCCondCode cond;
819            HReg        dst;
820            HReg        src;
821         } FpCMov;
822         /* Load FP Status & Control Register */
823         struct {
824            HReg src;
825            UInt dfp_rm;
826         } FpLdFPSCR;
827         /* Do a compare, generating result into an int register. */
828         struct {
829            UChar crfD;
830            HReg  dst;
831            HReg  srcL;
832            HReg  srcR;
833         } FpCmp;
834
835         /* Read/Write Link Register */
836         struct {
837            Bool wrLR;
838            HReg gpr;
839         } RdWrLR;
840
841         /* Simplistic AltiVec */
842         struct {
843            Bool      isLoad;
844            UChar     sz;      /* 8|16|32|128 */
845            HReg      reg;
846            PPCAMode* addr;
847         } AvLdSt;
848         struct {
849            PPCAvOp op;
850            HReg    dst;
851            HReg    src;
852         } AvUnary;
853         struct {
854            PPCAvOp op;
855            HReg    dst;
856            HReg    srcL;
857            HReg    srcR;
858         } AvBinary;
859         struct {
860            PPCAvOp op;
861            HReg    dst;
862            HReg    src;
863            PPCRI*  val;
864         } AvBinaryInt;
865         struct {
866            PPCAvOp op;
867            HReg    dst;
868            HReg    srcL;
869            HReg    srcR;
870         } AvBin8x16;
871         struct {
872            PPCAvOp op;
873            HReg    dst;
874            HReg    srcL;
875            HReg    srcR;
876         } AvBin16x8;
877         struct {
878            PPCAvOp op;
879            HReg    dst;
880            HReg    srcL;
881            HReg    srcR;
882         } AvBin32x4;
883         /* Can only be generated for CPUs capable of ISA 2.07 or above */
884         struct {
885            PPCAvOp op;
886            HReg    dst;
887            HReg    srcL;
888            HReg    srcR;
889         } AvBin64x2;
890         struct {
891            PPCAvFpOp op;
892            HReg      dst;
893            HReg      srcL;
894            HReg      srcR;
895         } AvBin32Fx4;
896         struct {
897            PPCAvFpOp op;
898            HReg      dst;
899            HReg      src;
900         } AvUn32Fx4;
901         /* Perm,Sel,SlDbl,Splat are all weird AV permutations */
902         struct {
903            HReg dst;
904            HReg srcL;
905            HReg srcR;
906            HReg ctl;
907         } AvPerm;
908         struct {
909            HReg dst;
910            HReg srcL;
911            HReg srcR;
912            HReg ctl;
913         } AvSel;
914         struct {
915            Bool  shLeft;
916            HReg  dst;
917            PPCAMode* addr;
918         } AvSh;
919         struct {
920            UChar shift;
921            HReg  dst;
922            HReg  srcL;
923            HReg  srcR;
924         } AvShlDbl;
925         struct {
926            UChar    sz;   /* 8,16,32 */
927            HReg     dst;
928            PPCVI5s* src;
929         } AvSplat;
930         /* Mov src to dst on the given condition, which may not
931            be the bogus Xcc_ALWAYS. */
932         struct {
933            PPCCondCode cond;
934            HReg        dst;
935            HReg        src;
936         } AvCMov;
937         /* Load AltiVec Status & Control Register */
938         struct {
939            HReg src;
940         } AvLdVSCR;
941         struct {
942            PPCAvOp   op;
943            HReg      dst;
944            HReg      src;
945         } AvCipherV128Unary;
946         struct {
947            PPCAvOp     op;
948            HReg       dst;
949            HReg       src;
950            PPCRI* s_field;
951         } AvHashV128Binary;
952         struct {
953            PPCAvOp     op;
954            HReg       dst;
955            HReg      src1;
956            HReg      src2;
957         } AvBCDV128Binary;
958         struct {
959            PPCAvOp   op;
960            HReg      dst;
961            HReg      srcL;
962            HReg      srcR;
963         } AvCipherV128Binary;
964         struct {
965            PPCFpOp op;
966            HReg dst;
967            HReg src;
968         } Dfp64Unary;
969         struct {
970            PPCFpOp op;
971            HReg dst;
972            HReg srcL;
973            HReg srcR;
974         } Dfp64Binary;
975         struct {
976            PPCFpOp op;
977            HReg   dst;
978            HReg   src;
979            PPCRI* shift;
980         } DfpShift;
981         struct {
982            PPCFpOp op;
983            HReg dst_hi;
984            HReg dst_lo;
985            HReg src_hi;
986            HReg src_lo;
987         } Dfp128Unary;
988         struct {
989            /* The dst is used to pass the left source operand in and return
990             * the result.
991             */
992            PPCFpOp op;
993            HReg dst_hi;
994            HReg dst_lo;
995            HReg srcR_hi;
996            HReg srcR_lo;
997         } Dfp128Binary;
998         struct {
999            PPCFpOp op;
1000            HReg   dst_hi;
1001            HReg   dst_lo;
1002            HReg   src_hi;
1003            HReg   src_lo;
1004            PPCRI* shift;
1005         } DfpShift128;
1006         struct {
1007            HReg dst;
1008            HReg src;
1009            PPCRI* r_rmc;
1010         } DfpRound;
1011         struct {
1012            HReg dst_hi;
1013            HReg dst_lo;
1014            HReg src_hi;
1015            HReg src_lo;
1016            PPCRI* r_rmc;
1017         } DfpRound128;
1018         struct {
1019	    PPCFpOp op;
1020            HReg dst;
1021            HReg srcL;
1022            HReg srcR;
1023            PPCRI* rmc;
1024         } DfpQuantize;
1025         struct {
1026	    PPCFpOp op;
1027            HReg dst_hi;
1028            HReg dst_lo;
1029            HReg src_hi;
1030            HReg src_lo;
1031  	    PPCRI* rmc;
1032         } DfpQuantize128;
1033         struct {
1034            PPCFpOp op;
1035            HReg dst;
1036            HReg src_hi;
1037            HReg src_lo;
1038         } ExtractExpD128;
1039         struct {
1040	    PPCFpOp op;
1041            HReg dst_hi;
1042            HReg dst_lo;
1043            HReg srcL;
1044            HReg srcR_hi;
1045            HReg srcR_lo;
1046         } InsertExpD128;
1047         struct {
1048            PPCFpOp op;
1049            HReg   dst;
1050            HReg   src_hi;
1051            HReg   src_lo;
1052         } DfpD128toD64;
1053         struct {
1054            PPCFpOp op;
1055            HReg   dst_hi;
1056            HReg   dst_lo;
1057            HReg   src;
1058         } DfpI64StoD128;
1059         struct {
1060            UChar crfD;
1061            HReg  dst;
1062            HReg  srcL;
1063            HReg  srcR;
1064         } Dfp64Cmp;
1065         struct {
1066            UChar crfD;
1067            HReg  dst;
1068            HReg  srcL_hi;
1069            HReg  srcL_lo;
1070            HReg  srcR_hi;
1071            HReg  srcR_lo;
1072         } Dfp128Cmp;
1073         struct {
1074            PPCAMode* amCounter;
1075            PPCAMode* amFailAddr;
1076         } EvCheck;
1077         struct {
1078            /* No fields.  The address of the counter to inc is
1079               installed later, post-translation, by patching it in,
1080               as it is not known at translation time. */
1081         } ProfInc;
1082      } Pin;
1083   }
1084   PPCInstr;
1085
1086
1087extern PPCInstr* PPCInstr_LI         ( HReg, ULong, Bool );
1088extern PPCInstr* PPCInstr_Alu        ( PPCAluOp, HReg, HReg, PPCRH* );
1089extern PPCInstr* PPCInstr_Shft       ( PPCShftOp, Bool sz32, HReg, HReg, PPCRH* );
1090extern PPCInstr* PPCInstr_AddSubC    ( Bool, Bool, HReg, HReg, HReg );
1091extern PPCInstr* PPCInstr_Cmp        ( Bool, Bool, UInt, HReg, PPCRH* );
1092extern PPCInstr* PPCInstr_Unary      ( PPCUnaryOp op, HReg dst, HReg src );
1093extern PPCInstr* PPCInstr_MulL       ( Bool syned, Bool hi32, Bool sz32, HReg, HReg, HReg );
1094extern PPCInstr* PPCInstr_Div        ( Bool extended, Bool syned, Bool sz32, HReg dst, HReg srcL, HReg srcR );
1095extern PPCInstr* PPCInstr_Call       ( PPCCondCode, Addr64, UInt, RetLoc );
1096extern PPCInstr* PPCInstr_XDirect    ( Addr64 dstGA, PPCAMode* amCIA,
1097                                       PPCCondCode cond, Bool toFastEP );
1098extern PPCInstr* PPCInstr_XIndir     ( HReg dstGA, PPCAMode* amCIA,
1099                                       PPCCondCode cond );
1100extern PPCInstr* PPCInstr_XAssisted  ( HReg dstGA, PPCAMode* amCIA,
1101                                       PPCCondCode cond, IRJumpKind jk );
1102extern PPCInstr* PPCInstr_CMov       ( PPCCondCode, HReg dst, PPCRI* src );
1103extern PPCInstr* PPCInstr_Load       ( UChar sz,
1104                                       HReg dst, PPCAMode* src, Bool mode64 );
1105extern PPCInstr* PPCInstr_LoadL      ( UChar sz,
1106                                       HReg dst, HReg src, Bool mode64 );
1107extern PPCInstr* PPCInstr_Store      ( UChar sz, PPCAMode* dst,
1108                                       HReg src, Bool mode64 );
1109extern PPCInstr* PPCInstr_StoreC     ( UChar sz, HReg dst, HReg src,
1110                                       Bool mode64 );
1111extern PPCInstr* PPCInstr_Set        ( PPCCondCode cond, HReg dst );
1112extern PPCInstr* PPCInstr_MfCR       ( HReg dst );
1113extern PPCInstr* PPCInstr_MFence     ( void );
1114
1115extern PPCInstr* PPCInstr_Fp128Unary    ( PPCFpOp op, HReg dst, HReg src );
1116extern PPCInstr* PPCInstr_Fp128Binary   ( PPCFpOp op, HReg dst, HReg srcL, HReg srcR );
1117extern PPCInstr* PPCInstr_Fp128Trinary  ( PPCFpOp op, HReg dst, HReg srcL,
1118                                          HReg srcR);
1119
1120extern PPCInstr* PPCInstr_FpUnary    ( PPCFpOp op, HReg dst, HReg src );
1121extern PPCInstr* PPCInstr_FpBinary   ( PPCFpOp op, HReg dst, HReg srcL, HReg srcR );
1122extern PPCInstr* PPCInstr_FpMulAcc   ( PPCFpOp op, HReg dst, HReg srcML,
1123                                                   HReg srcMR, HReg srcAcc );
1124extern PPCInstr* PPCInstr_FpLdSt     ( Bool isLoad, UChar sz, HReg, PPCAMode* );
1125extern PPCInstr* PPCInstr_FpSTFIW    ( HReg addr, HReg data );
1126extern PPCInstr* PPCInstr_FpRSP      ( HReg dst, HReg src );
1127extern PPCInstr* PPCInstr_FpCftI     ( Bool fromI, Bool int32, Bool syned,
1128                                       Bool dst64, HReg dst, HReg src );
1129extern PPCInstr* PPCInstr_FpCMov     ( PPCCondCode, HReg dst, HReg src );
1130extern PPCInstr* PPCInstr_FpLdFPSCR  ( HReg src, Bool dfp_rm );
1131extern PPCInstr* PPCInstr_FpCmp      ( HReg dst, HReg srcL, HReg srcR );
1132
1133extern PPCInstr* PPCInstr_RdWrLR     ( Bool wrLR, HReg gpr );
1134
1135extern PPCInstr* PPCInstr_AvLdSt     ( Bool isLoad, UChar sz, HReg, PPCAMode* );
1136extern PPCInstr* PPCInstr_AvUnary    ( PPCAvOp op, HReg dst, HReg src );
1137extern PPCInstr* PPCInstr_AvBinary   ( PPCAvOp op, HReg dst, HReg srcL, HReg srcR );
1138extern PPCInstr* PPCInstr_AvBinaryInt( PPCAvOp op, HReg dst, HReg src, PPCRI* val );
1139extern PPCInstr* PPCInstr_AvBin8x16  ( PPCAvOp op, HReg dst, HReg srcL, HReg srcR );
1140extern PPCInstr* PPCInstr_AvBin16x8  ( PPCAvOp op, HReg dst, HReg srcL, HReg srcR );
1141extern PPCInstr* PPCInstr_AvBin32x4  ( PPCAvOp op, HReg dst, HReg srcL, HReg srcR );
1142extern PPCInstr* PPCInstr_AvBin64x2  ( PPCAvOp op, HReg dst, HReg srcL, HReg srcR );
1143extern PPCInstr* PPCInstr_AvBin32Fx4 ( PPCAvFpOp op, HReg dst, HReg srcL, HReg srcR );
1144extern PPCInstr* PPCInstr_AvUn32Fx4  ( PPCAvFpOp op, HReg dst, HReg src );
1145extern PPCInstr* PPCInstr_AvPerm     ( HReg dst, HReg srcL, HReg srcR, HReg ctl );
1146extern PPCInstr* PPCInstr_AvSel      ( HReg ctl, HReg dst, HReg srcL, HReg srcR );
1147extern PPCInstr* PPCInstr_AvSh       ( Bool shLeft, HReg dst, PPCAMode* am_addr );
1148extern PPCInstr* PPCInstr_AvShlDbl   ( UChar shift, HReg dst, HReg srcL, HReg srcR );
1149extern PPCInstr* PPCInstr_AvSplat    ( UChar sz, HReg dst, PPCVI5s* src );
1150extern PPCInstr* PPCInstr_AvCMov     ( PPCCondCode, HReg dst, HReg src );
1151extern PPCInstr* PPCInstr_AvLdVSCR   ( HReg src );
1152extern PPCInstr* PPCInstr_AvCipherV128Unary  ( PPCAvOp op, HReg dst,
1153                                               HReg srcR );
1154extern PPCInstr* PPCInstr_AvCipherV128Binary ( PPCAvOp op, HReg dst,
1155                                               HReg srcL, HReg srcR );
1156extern PPCInstr* PPCInstr_AvHashV128Binary ( PPCAvOp op, HReg dst,
1157                                             HReg src, PPCRI* s_field );
1158extern PPCInstr* PPCInstr_AvBCDV128Binary ( PPCAvOp op, HReg dst,
1159                                            HReg src1, HReg src2 );
1160extern PPCInstr* PPCInstr_Dfp64Unary  ( PPCFpOp op, HReg dst, HReg src );
1161extern PPCInstr* PPCInstr_Dfp64Binary ( PPCFpOp op, HReg dst, HReg srcL,
1162                                        HReg srcR );
1163extern PPCInstr* PPCInstr_DfpShift    ( PPCFpOp op, HReg dst, HReg src,
1164                                        PPCRI* shift );
1165extern PPCInstr* PPCInstr_Dfp128Unary  ( PPCFpOp op, HReg dst_hi, HReg dst_lo,
1166                                         HReg srcR_hi, HReg srcR_lo );
1167extern PPCInstr* PPCInstr_Dfp128Binary ( PPCFpOp op, HReg dst_hi, HReg dst_lo,
1168                                         HReg srcR_hi, HReg srcR_lo );
1169extern PPCInstr* PPCInstr_DfpShift128  ( PPCFpOp op, HReg dst_hi, HReg src_hi,
1170                                         HReg dst_lo, HReg src_lo,
1171                                         PPCRI* shift );
1172extern PPCInstr* PPCInstr_DfpD128toD64 ( PPCFpOp op, HReg dst,
1173                                         HReg dst_lo, HReg src_lo);
1174extern PPCInstr* PPCInstr_DfpI64StoD128  ( PPCFpOp op, HReg dst_hi,
1175                                           HReg dst_lo, HReg src);
1176extern PPCInstr* PPCInstr_DfpRound       ( HReg dst, HReg src, PPCRI* r_rmc );
1177extern PPCInstr* PPCInstr_DfpRound128    ( HReg dst_hi, HReg dst_lo, HReg src_hi,
1178                                           HReg src_lo, PPCRI* r_rmc );
1179extern PPCInstr* PPCInstr_DfpQuantize    ( PPCFpOp op, HReg dst, HReg srcL,
1180                                           HReg srcR, PPCRI* rmc );
1181extern PPCInstr* PPCInstr_DfpQuantize128 ( PPCFpOp op, HReg dst_hi,
1182                                           HReg dst_lo,
1183                                           HReg src_hi,
1184                                           HReg src_lo, PPCRI* rmc );
1185extern PPCInstr* PPCInstr_ExtractExpD128 ( PPCFpOp op,   HReg dst,
1186                                           HReg src_hi, HReg src_lo );
1187extern PPCInstr* PPCInstr_InsertExpD128  ( PPCFpOp op,   HReg dst_hi,
1188                                           HReg dst_lo,  HReg srcL,
1189                                           HReg srcR_hi, HReg srcR_lo );
1190extern PPCInstr* PPCInstr_Dfp64Cmp       ( HReg dst, HReg srcL, HReg srcR );
1191extern PPCInstr* PPCInstr_Dfp128Cmp      ( HReg dst, HReg srcL_hi, HReg srcL_lo,
1192                                           HReg srcR_hi, HReg srcR_lo );
1193extern PPCInstr* PPCInstr_EvCheck     ( PPCAMode* amCounter,
1194                                        PPCAMode* amFailAddr );
1195extern PPCInstr* PPCInstr_ProfInc     ( void );
1196
1197extern void ppPPCInstr(const PPCInstr*, Bool mode64);
1198
1199
1200/* Some functions that insulate the register allocator from details
1201   of the underlying instruction set. */
1202extern void getRegUsage_PPCInstr ( HRegUsage*, const PPCInstr*, Bool mode64 );
1203extern void mapRegs_PPCInstr     ( HRegRemap*, PPCInstr* , Bool mode64);
1204extern Bool isMove_PPCInstr      ( const PPCInstr*, HReg*, HReg* );
1205extern Int          emit_PPCInstr   ( /*MB_MOD*/Bool* is_profInc,
1206                                      UChar* buf, Int nbuf, const PPCInstr* i,
1207                                      Bool mode64,
1208                                      VexEndness endness_host,
1209                                      const void* disp_cp_chain_me_to_slowEP,
1210                                      const void* disp_cp_chain_me_to_fastEP,
1211                                      const void* disp_cp_xindir,
1212                                      const void* disp_cp_xassisted );
1213
1214extern void genSpill_PPC  ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2,
1215                            HReg rreg, Int offsetB, Bool mode64 );
1216extern void genReload_PPC ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2,
1217                            HReg rreg, Int offsetB, Bool mode64 );
1218
1219extern const RRegUniverse* getRRegUniverse_PPC ( Bool mode64 );
1220
1221extern HInstrArray* iselSB_PPC           ( const IRSB*,
1222                                           VexArch,
1223                                           const VexArchInfo*,
1224                                           const VexAbiInfo*,
1225                                           Int offs_Host_EvC_Counter,
1226                                           Int offs_Host_EvC_FailAddr,
1227                                           Bool chainingAllowed,
1228                                           Bool addProfInc,
1229                                           Addr max_ga );
1230
1231/* How big is an event check?  This is kind of a kludge because it
1232   depends on the offsets of host_EvC_FAILADDR and
1233   host_EvC_COUNTER. */
1234extern Int evCheckSzB_PPC (void);
1235
1236/* Perform a chaining and unchaining of an XDirect jump. */
1237extern VexInvalRange chainXDirect_PPC ( VexEndness endness_host,
1238                                        void* place_to_chain,
1239                                        const void* disp_cp_chain_me_EXPECTED,
1240                                        const void* place_to_jump_to,
1241                                        Bool  mode64 );
1242
1243extern VexInvalRange unchainXDirect_PPC ( VexEndness endness_host,
1244                                          void* place_to_unchain,
1245                                          const void* place_to_jump_to_EXPECTED,
1246                                          const void* disp_cp_chain_me,
1247                                          Bool  mode64 );
1248
1249/* Patch the counter location into an existing ProfInc point. */
1250extern VexInvalRange patchProfInc_PPC ( VexEndness endness_host,
1251                                        void*  place_to_patch,
1252                                        const ULong* location_of_counter,
1253                                        Bool   mode64 );
1254
1255
1256#endif /* ndef __VEX_HOST_PPC_DEFS_H */
1257
1258/*---------------------------------------------------------------*/
1259/*--- end                                     host_ppc_defs.h ---*/
1260/*---------------------------------------------------------------*/
1261