macro-assembler-aarch64.cc revision 85919f840e8ddd06573def57eb587cc77661e7d0
1b78f13911bfe6eda303e91ef215c87a165aae8aeAlexandre Rames// Copyright 2015, VIXL authors 2ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// All rights reserved. 3ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// 4ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// Redistribution and use in source and binary forms, with or without 5ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// modification, are permitted provided that the following conditions are met: 6ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// 7ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// * Redistributions of source code must retain the above copyright notice, 8ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// this list of conditions and the following disclaimer. 9ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// * Redistributions in binary form must reproduce the above copyright notice, 10ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// this list of conditions and the following disclaimer in the documentation 11ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// and/or other materials provided with the distribution. 12ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// * Neither the name of ARM Limited nor the names of its contributors may be 13ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// used to endorse or promote products derived from this software without 14ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// specific prior written permission. 15ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// 16ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND 17ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 20ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 23ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 2778973f258039f6e96eba85f1b5ecdb14b3c51dbbPierre Langlois#include <cctype> 28684cd2a7f5845539b58d0da7e012e39df49ceff0armvixl 29b49bdb7996e603555eba4c8b56c7325e3e737ab6Alexandre Rames#include "macro-assembler-aarch64.h" 305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 31ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlnamespace vixl { 3288c46b84df005638546de5e4e965bdcc31352f48Pierre Langloisnamespace aarch64 { 33ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 34c68cb64496485710cdb5b8480f8fee287058c93farmvixl 355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlvoid Pool::Release() { 365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (--monitor_ == 0) { 375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Ensure the pool has not been blocked for too long. 3888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_ASSERT(masm_->GetCursorOffset() < checkpoint_); 395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlvoid Pool::SetNextCheckpoint(ptrdiff_t checkpoint) { 445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl masm_->checkpoint_ = std::min(masm_->checkpoint_, checkpoint); 455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl checkpoint_ = checkpoint; 465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 496e2c8275d5f34a531fe1eef7a7aa877601be8558armvixlLiteralPool::LiteralPool(MacroAssembler* masm) 500f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl : Pool(masm), 510f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl size_(0), 520f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl first_use_(-1), 530f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl recommended_checkpoint_(kNoCheckpointRequired) {} 54c68cb64496485710cdb5b8480f8fee287058c93farmvixl 55c68cb64496485710cdb5b8480f8fee287058c93farmvixl 56c68cb64496485710cdb5b8480f8fee287058c93farmvixlLiteralPool::~LiteralPool() { 57c68cb64496485710cdb5b8480f8fee287058c93farmvixl VIXL_ASSERT(IsEmpty()); 58c68cb64496485710cdb5b8480f8fee287058c93farmvixl VIXL_ASSERT(!IsBlocked()); 59db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl for (std::vector<RawLiteral*>::iterator it = deleted_on_destruction_.begin(); 60db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl it != deleted_on_destruction_.end(); 61db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl it++) { 62db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl delete *it; 63db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl } 64c68cb64496485710cdb5b8480f8fee287058c93farmvixl} 65c68cb64496485710cdb5b8480f8fee287058c93farmvixl 66c68cb64496485710cdb5b8480f8fee287058c93farmvixl 67c68cb64496485710cdb5b8480f8fee287058c93farmvixlvoid LiteralPool::Reset() { 68c68cb64496485710cdb5b8480f8fee287058c93farmvixl std::vector<RawLiteral*>::iterator it, end; 69c68cb64496485710cdb5b8480f8fee287058c93farmvixl for (it = entries_.begin(), end = entries_.end(); it != end; ++it) { 70db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl RawLiteral* literal = *it; 71db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl if (literal->deletion_policy_ == RawLiteral::kDeletedOnPlacementByPool) { 72db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl delete literal; 73db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl } 74c68cb64496485710cdb5b8480f8fee287058c93farmvixl } 75c68cb64496485710cdb5b8480f8fee287058c93farmvixl entries_.clear(); 765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl size_ = 0; 77c68cb64496485710cdb5b8480f8fee287058c93farmvixl first_use_ = -1; 785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Pool::Reset(); 795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl recommended_checkpoint_ = kNoCheckpointRequired; 80c68cb64496485710cdb5b8480f8fee287058c93farmvixl} 81c68cb64496485710cdb5b8480f8fee287058c93farmvixl 82c68cb64496485710cdb5b8480f8fee287058c93farmvixl 83c68cb64496485710cdb5b8480f8fee287058c93farmvixlvoid LiteralPool::CheckEmitFor(size_t amount, EmitOption option) { 84c68cb64496485710cdb5b8480f8fee287058c93farmvixl if (IsEmpty() || IsBlocked()) return; 85c68cb64496485710cdb5b8480f8fee287058c93farmvixl 8688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois ptrdiff_t distance = masm_->GetCursorOffset() + amount - first_use_; 87c68cb64496485710cdb5b8480f8fee287058c93farmvixl if (distance >= kRecommendedLiteralPoolRange) { 88c68cb64496485710cdb5b8480f8fee287058c93farmvixl Emit(option); 89c68cb64496485710cdb5b8480f8fee287058c93farmvixl } 90c68cb64496485710cdb5b8480f8fee287058c93farmvixl} 91c68cb64496485710cdb5b8480f8fee287058c93farmvixl 92c68cb64496485710cdb5b8480f8fee287058c93farmvixl 9307d1aa5b941ace15deb01e5df2c79e677039c4aeAlexandre Rames// We use a subclass to access the protected `ExactAssemblyScope` constructor 9407d1aa5b941ace15deb01e5df2c79e677039c4aeAlexandre Rames// giving us control over the pools. This allows us to use this scope within 9507d1aa5b941ace15deb01e5df2c79e677039c4aeAlexandre Rames// code emitting pools without creating a circular dependency. 9607d1aa5b941ace15deb01e5df2c79e677039c4aeAlexandre Rames// We keep the constructor private to restrict usage of this helper class. 9707d1aa5b941ace15deb01e5df2c79e677039c4aeAlexandre Ramesclass ExactAssemblyScopeWithoutPoolsCheck : public ExactAssemblyScope { 9807d1aa5b941ace15deb01e5df2c79e677039c4aeAlexandre Rames private: 9907d1aa5b941ace15deb01e5df2c79e677039c4aeAlexandre Rames ExactAssemblyScopeWithoutPoolsCheck(MacroAssembler* masm, size_t size) 10007d1aa5b941ace15deb01e5df2c79e677039c4aeAlexandre Rames : ExactAssemblyScope(masm, 10107d1aa5b941ace15deb01e5df2c79e677039c4aeAlexandre Rames size, 10207d1aa5b941ace15deb01e5df2c79e677039c4aeAlexandre Rames ExactAssemblyScope::kExactSize, 10307d1aa5b941ace15deb01e5df2c79e677039c4aeAlexandre Rames ExactAssemblyScope::kIgnorePools) {} 10407d1aa5b941ace15deb01e5df2c79e677039c4aeAlexandre Rames 10507d1aa5b941ace15deb01e5df2c79e677039c4aeAlexandre Rames friend void LiteralPool::Emit(LiteralPool::EmitOption); 10607d1aa5b941ace15deb01e5df2c79e677039c4aeAlexandre Rames friend void VeneerPool::Emit(VeneerPool::EmitOption, size_t); 10707d1aa5b941ace15deb01e5df2c79e677039c4aeAlexandre Rames}; 10807d1aa5b941ace15deb01e5df2c79e677039c4aeAlexandre Rames 10907d1aa5b941ace15deb01e5df2c79e677039c4aeAlexandre Rames 110c68cb64496485710cdb5b8480f8fee287058c93farmvixlvoid LiteralPool::Emit(EmitOption option) { 111c68cb64496485710cdb5b8480f8fee287058c93farmvixl // There is an issue if we are asked to emit a blocked or empty pool. 112c68cb64496485710cdb5b8480f8fee287058c93farmvixl VIXL_ASSERT(!IsBlocked()); 113c68cb64496485710cdb5b8480f8fee287058c93farmvixl VIXL_ASSERT(!IsEmpty()); 114c68cb64496485710cdb5b8480f8fee287058c93farmvixl 11588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois size_t pool_size = GetSize(); 116c68cb64496485710cdb5b8480f8fee287058c93farmvixl size_t emit_size = pool_size; 117c68cb64496485710cdb5b8480f8fee287058c93farmvixl if (option == kBranchRequired) emit_size += kInstructionSize; 118c68cb64496485710cdb5b8480f8fee287058c93farmvixl Label end_of_pool; 119c68cb64496485710cdb5b8480f8fee287058c93farmvixl 1205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(emit_size % kInstructionSize == 0); 121de5bb0beb4a3342bb9f0d7e7fe16737a171517b0Alexandre Rames { 122de5bb0beb4a3342bb9f0d7e7fe16737a171517b0Alexandre Rames CodeBufferCheckScope guard(masm_, 123de5bb0beb4a3342bb9f0d7e7fe16737a171517b0Alexandre Rames emit_size, 124de5bb0beb4a3342bb9f0d7e7fe16737a171517b0Alexandre Rames CodeBufferCheckScope::kCheck, 125de5bb0beb4a3342bb9f0d7e7fe16737a171517b0Alexandre Rames CodeBufferCheckScope::kExactSize); 126de5bb0beb4a3342bb9f0d7e7fe16737a171517b0Alexandre Rames#ifdef VIXL_DEBUG 127de5bb0beb4a3342bb9f0d7e7fe16737a171517b0Alexandre Rames // Also explicitly disallow usage of the `MacroAssembler` here. 128de5bb0beb4a3342bb9f0d7e7fe16737a171517b0Alexandre Rames masm_->SetAllowMacroInstructions(false); 129de5bb0beb4a3342bb9f0d7e7fe16737a171517b0Alexandre Rames#endif 130de5bb0beb4a3342bb9f0d7e7fe16737a171517b0Alexandre Rames if (option == kBranchRequired) { 13107d1aa5b941ace15deb01e5df2c79e677039c4aeAlexandre Rames ExactAssemblyScopeWithoutPoolsCheck guard(masm_, kInstructionSize); 132de5bb0beb4a3342bb9f0d7e7fe16737a171517b0Alexandre Rames masm_->b(&end_of_pool); 133de5bb0beb4a3342bb9f0d7e7fe16737a171517b0Alexandre Rames } 134c68cb64496485710cdb5b8480f8fee287058c93farmvixl 135de5bb0beb4a3342bb9f0d7e7fe16737a171517b0Alexandre Rames { 136de5bb0beb4a3342bb9f0d7e7fe16737a171517b0Alexandre Rames // Marker indicating the size of the literal pool in 32-bit words. 137de5bb0beb4a3342bb9f0d7e7fe16737a171517b0Alexandre Rames VIXL_ASSERT((pool_size % kWRegSizeInBytes) == 0); 13807d1aa5b941ace15deb01e5df2c79e677039c4aeAlexandre Rames ExactAssemblyScopeWithoutPoolsCheck guard(masm_, kInstructionSize); 139de5bb0beb4a3342bb9f0d7e7fe16737a171517b0Alexandre Rames masm_->ldr(xzr, static_cast<int>(pool_size / kWRegSizeInBytes)); 140de5bb0beb4a3342bb9f0d7e7fe16737a171517b0Alexandre Rames } 141c68cb64496485710cdb5b8480f8fee287058c93farmvixl 142de5bb0beb4a3342bb9f0d7e7fe16737a171517b0Alexandre Rames // Now populate the literal pool. 143de5bb0beb4a3342bb9f0d7e7fe16737a171517b0Alexandre Rames std::vector<RawLiteral*>::iterator it, end; 144de5bb0beb4a3342bb9f0d7e7fe16737a171517b0Alexandre Rames for (it = entries_.begin(), end = entries_.end(); it != end; ++it) { 145de5bb0beb4a3342bb9f0d7e7fe16737a171517b0Alexandre Rames VIXL_ASSERT((*it)->IsUsed()); 146de5bb0beb4a3342bb9f0d7e7fe16737a171517b0Alexandre Rames masm_->place(*it); 147de5bb0beb4a3342bb9f0d7e7fe16737a171517b0Alexandre Rames } 148c68cb64496485710cdb5b8480f8fee287058c93farmvixl 149de5bb0beb4a3342bb9f0d7e7fe16737a171517b0Alexandre Rames if (option == kBranchRequired) masm_->bind(&end_of_pool); 150de5bb0beb4a3342bb9f0d7e7fe16737a171517b0Alexandre Rames#ifdef VIXL_DEBUG 151de5bb0beb4a3342bb9f0d7e7fe16737a171517b0Alexandre Rames masm_->SetAllowMacroInstructions(true); 152de5bb0beb4a3342bb9f0d7e7fe16737a171517b0Alexandre Rames#endif 153de5bb0beb4a3342bb9f0d7e7fe16737a171517b0Alexandre Rames } 154c68cb64496485710cdb5b8480f8fee287058c93farmvixl 1555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Reset(); 1565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 1575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 1585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 159db6443499376478f5281607a3923e6ffc4c8d8ecarmvixlvoid LiteralPool::AddEntry(RawLiteral* literal) { 160db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl // A literal must be registered immediately before its first use. Here we 161db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl // cannot control that it is its first use, but we check no code has been 162db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl // emitted since its last use. 16388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_ASSERT(masm_->GetCursorOffset() == literal->GetLastUse()); 1645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 16588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois UpdateFirstUse(masm_->GetCursorOffset()); 16688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_ASSERT(masm_->GetCursorOffset() >= first_use_); 1675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl entries_.push_back(literal); 16888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois size_ += literal->GetSize(); 169db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl} 170db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl 1715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 172db6443499376478f5281607a3923e6ffc4c8d8ecarmvixlvoid LiteralPool::UpdateFirstUse(ptrdiff_t use_position) { 173db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl first_use_ = std::min(first_use_, use_position); 174db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl if (first_use_ == -1) { 175db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl first_use_ = use_position; 17688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois SetNextRecommendedCheckpoint(GetNextRecommendedCheckpoint()); 177db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl SetNextCheckpoint(first_use_ + Instruction::kLoadLiteralRange); 178db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl } else { 179db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl VIXL_ASSERT(use_position > first_use_); 180db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl } 1815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 1825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 1835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 1845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlvoid VeneerPool::Reset() { 1855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Pool::Reset(); 1865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl unresolved_branches_.Reset(); 1875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 1885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 1895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 1905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlvoid VeneerPool::Release() { 1915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (--monitor_ == 0) { 1925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(IsEmpty() || 19388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois masm_->GetCursorOffset() < 19488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois unresolved_branches_.GetFirstLimit()); 1955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 196c68cb64496485710cdb5b8480f8fee287058c93farmvixl} 197c68cb64496485710cdb5b8480f8fee287058c93farmvixl 198c68cb64496485710cdb5b8480f8fee287058c93farmvixl 1995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlvoid VeneerPool::RegisterUnresolvedBranch(ptrdiff_t branch_pos, 2005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Label* label, 2015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl ImmBranchType branch_type) { 2025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(!label->IsBound()); 2035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl BranchInfo branch_info = BranchInfo(branch_pos, label, branch_type); 2045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl unresolved_branches_.insert(branch_info); 2055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl UpdateNextCheckPoint(); 2065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // TODO: In debug mode register the label with the assembler to make sure it 2075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // is bound with masm Bind and not asm bind. 2085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 2095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 2105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 2115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlvoid VeneerPool::DeleteUnresolvedBranchInfoForLabel(Label* label) { 212c68cb64496485710cdb5b8480f8fee287058c93farmvixl if (IsEmpty()) { 2135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(checkpoint_ == kNoCheckpointRequired); 2145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return; 215c68cb64496485710cdb5b8480f8fee287058c93farmvixl } 216c68cb64496485710cdb5b8480f8fee287058c93farmvixl 2175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (label->IsLinked()) { 2185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Label::LabelLinksIterator links_it(label); 2195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (; !links_it.Done(); links_it.Advance()) { 2205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl ptrdiff_t link_offset = *links_it.Current(); 22188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois Instruction* link = masm_->GetInstructionAt(link_offset); 222c68cb64496485710cdb5b8480f8fee287058c93farmvixl 2235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // ADR instructions are not handled. 22488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois if (BranchTypeUsesVeneers(link->GetBranchType())) { 22588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois BranchInfo branch_info(link_offset, label, link->GetBranchType()); 2265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl unresolved_branches_.erase(branch_info); 2275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 2285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 2295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 2305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 2315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl UpdateNextCheckPoint(); 2325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 2335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 2345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 235db6443499376478f5281607a3923e6ffc4c8d8ecarmvixlbool VeneerPool::ShouldEmitVeneer(int64_t max_reachable_pc, size_t amount) { 2365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl ptrdiff_t offset = 23788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois kPoolNonVeneerCodeSize + amount + GetMaxSize() + GetOtherPoolsMaxSize(); 23888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return (masm_->GetCursorOffset() + offset) > max_reachable_pc; 2395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 2405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 2415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 2425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlvoid VeneerPool::CheckEmitFor(size_t amount, EmitOption option) { 2435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (IsEmpty()) return; 2445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 24588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_ASSERT(masm_->GetCursorOffset() < unresolved_branches_.GetFirstLimit()); 2465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 2475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (IsBlocked()) return; 2485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 2495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (ShouldEmitVeneers(amount)) { 2505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Emit(option, amount); 2515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 2525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl UpdateNextCheckPoint(); 2535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 2545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 2555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 2565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 2575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlvoid VeneerPool::Emit(EmitOption option, size_t amount) { 2585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // There is an issue if we are asked to emit a blocked or empty pool. 2595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(!IsBlocked()); 2605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(!IsEmpty()); 2615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 2625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Label end; 2635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (option == kBranchRequired) { 26407d1aa5b941ace15deb01e5df2c79e677039c4aeAlexandre Rames ExactAssemblyScopeWithoutPoolsCheck guard(masm_, kInstructionSize); 2655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl masm_->b(&end); 2665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 2675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 2685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // We want to avoid generating veneer pools too often, so generate veneers for 2695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // branches that don't immediately require a veneer but will soon go out of 2705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // range. 2715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl static const size_t kVeneerEmissionMargin = 1 * KBytes; 2725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 2735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (BranchInfoSetIterator it(&unresolved_branches_); !it.Done();) { 2745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl BranchInfo* branch_info = it.Current(); 2755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (ShouldEmitVeneer(branch_info->max_reachable_pc_, 2765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl amount + kVeneerEmissionMargin)) { 277de5bb0beb4a3342bb9f0d7e7fe16737a171517b0Alexandre Rames CodeBufferCheckScope scope(masm_, 278de5bb0beb4a3342bb9f0d7e7fe16737a171517b0Alexandre Rames kVeneerCodeSize, 279de5bb0beb4a3342bb9f0d7e7fe16737a171517b0Alexandre Rames CodeBufferCheckScope::kCheck, 280de5bb0beb4a3342bb9f0d7e7fe16737a171517b0Alexandre Rames CodeBufferCheckScope::kExactSize); 2815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl ptrdiff_t branch_pos = branch_info->pc_offset_; 28288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois Instruction* branch = masm_->GetInstructionAt(branch_pos); 2835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Label* label = branch_info->label_; 2845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 2855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Patch the branch to point to the current position, and emit a branch 2865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // to the label. 2875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Instruction* veneer = masm_->GetCursorAddress<Instruction*>(); 2885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl branch->SetImmPCOffsetTarget(veneer); 289de5bb0beb4a3342bb9f0d7e7fe16737a171517b0Alexandre Rames { 29007d1aa5b941ace15deb01e5df2c79e677039c4aeAlexandre Rames ExactAssemblyScopeWithoutPoolsCheck guard(masm_, kInstructionSize); 291de5bb0beb4a3342bb9f0d7e7fe16737a171517b0Alexandre Rames masm_->b(label); 292de5bb0beb4a3342bb9f0d7e7fe16737a171517b0Alexandre Rames } 2935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 2945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Update the label. The branch patched does not point to it any longer. 2955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl label->DeleteLink(branch_pos); 2965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 2975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl it.DeleteCurrentAndAdvance(); 2985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 2995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl it.AdvanceToNextType(); 3005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 3015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 3025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 3035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl UpdateNextCheckPoint(); 3045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 3055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl masm_->bind(&end); 306c68cb64496485710cdb5b8480f8fee287058c93farmvixl} 307c68cb64496485710cdb5b8480f8fee287058c93farmvixl 308c68cb64496485710cdb5b8480f8fee287058c93farmvixl 309f2f550c0bfd0f15a4d1c51ff06ec898536f14205Alexandre RamesMacroAssembler::MacroAssembler(PositionIndependentCodeOption pic) 310f2f550c0bfd0f15a4d1c51ff06ec898536f14205Alexandre Rames : Assembler(pic), 311b0d7672aa9d5163ffce32f14a0fc1aa32f516f89Alexandre Rames#ifdef VIXL_DEBUG 312b0d7672aa9d5163ffce32f14a0fc1aa32f516f89Alexandre Rames allow_macro_instructions_(true), 313b0d7672aa9d5163ffce32f14a0fc1aa32f516f89Alexandre Rames#endif 3141e85b7f2e8ad2bfb233de29405aade635ed207cePierre Langlois generate_simulator_code_(VIXL_AARCH64_GENERATE_SIMULATOR_CODE), 315b0d7672aa9d5163ffce32f14a0fc1aa32f516f89Alexandre Rames sp_(sp), 316b0d7672aa9d5163ffce32f14a0fc1aa32f516f89Alexandre Rames tmp_list_(ip0, ip1), 317b0d7672aa9d5163ffce32f14a0fc1aa32f516f89Alexandre Rames fptmp_list_(d31), 318e8ce9f0ec7fe9484fca0c446ecc8a9d7929bea66Jacob Bramley current_scratch_scope_(NULL), 319b0d7672aa9d5163ffce32f14a0fc1aa32f516f89Alexandre Rames literal_pool_(this), 320b0d7672aa9d5163ffce32f14a0fc1aa32f516f89Alexandre Rames veneer_pool_(this), 321b0d7672aa9d5163ffce32f14a0fc1aa32f516f89Alexandre Rames recommended_checkpoint_(Pool::kNoCheckpointRequired) { 322b0d7672aa9d5163ffce32f14a0fc1aa32f516f89Alexandre Rames checkpoint_ = GetNextCheckPoint(); 323fd09817b8770a5e3a64a6fe4fefe85cc29805cd7Alexandre Rames#ifndef VIXL_DEBUG 324fd09817b8770a5e3a64a6fe4fefe85cc29805cd7Alexandre Rames USE(allow_macro_instructions_); 325fd09817b8770a5e3a64a6fe4fefe85cc29805cd7Alexandre Rames#endif 326b0d7672aa9d5163ffce32f14a0fc1aa32f516f89Alexandre Rames} 327b0d7672aa9d5163ffce32f14a0fc1aa32f516f89Alexandre Rames 328b0d7672aa9d5163ffce32f14a0fc1aa32f516f89Alexandre Rames 329c68cb64496485710cdb5b8480f8fee287058c93farmvixlMacroAssembler::MacroAssembler(size_t capacity, 330c68cb64496485710cdb5b8480f8fee287058c93farmvixl PositionIndependentCodeOption pic) 331c68cb64496485710cdb5b8480f8fee287058c93farmvixl : Assembler(capacity, pic), 332330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl#ifdef VIXL_DEBUG 333c68cb64496485710cdb5b8480f8fee287058c93farmvixl allow_macro_instructions_(true), 334c68cb64496485710cdb5b8480f8fee287058c93farmvixl#endif 3351e85b7f2e8ad2bfb233de29405aade635ed207cePierre Langlois generate_simulator_code_(VIXL_AARCH64_GENERATE_SIMULATOR_CODE), 336c68cb64496485710cdb5b8480f8fee287058c93farmvixl sp_(sp), 337c68cb64496485710cdb5b8480f8fee287058c93farmvixl tmp_list_(ip0, ip1), 338c68cb64496485710cdb5b8480f8fee287058c93farmvixl fptmp_list_(d31), 339e8ce9f0ec7fe9484fca0c446ecc8a9d7929bea66Jacob Bramley current_scratch_scope_(NULL), 3405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl literal_pool_(this), 341db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl veneer_pool_(this), 342db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl recommended_checkpoint_(Pool::kNoCheckpointRequired) { 34388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois checkpoint_ = GetNextCheckPoint(); 344c68cb64496485710cdb5b8480f8fee287058c93farmvixl} 345c68cb64496485710cdb5b8480f8fee287058c93farmvixl 346c68cb64496485710cdb5b8480f8fee287058c93farmvixl 3470f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixlMacroAssembler::MacroAssembler(byte* buffer, 348c68cb64496485710cdb5b8480f8fee287058c93farmvixl size_t capacity, 349c68cb64496485710cdb5b8480f8fee287058c93farmvixl PositionIndependentCodeOption pic) 350c68cb64496485710cdb5b8480f8fee287058c93farmvixl : Assembler(buffer, capacity, pic), 351330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl#ifdef VIXL_DEBUG 352c68cb64496485710cdb5b8480f8fee287058c93farmvixl allow_macro_instructions_(true), 353c68cb64496485710cdb5b8480f8fee287058c93farmvixl#endif 3541e85b7f2e8ad2bfb233de29405aade635ed207cePierre Langlois generate_simulator_code_(VIXL_AARCH64_GENERATE_SIMULATOR_CODE), 355c68cb64496485710cdb5b8480f8fee287058c93farmvixl sp_(sp), 356c68cb64496485710cdb5b8480f8fee287058c93farmvixl tmp_list_(ip0, ip1), 357c68cb64496485710cdb5b8480f8fee287058c93farmvixl fptmp_list_(d31), 358e8ce9f0ec7fe9484fca0c446ecc8a9d7929bea66Jacob Bramley current_scratch_scope_(NULL), 3595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl literal_pool_(this), 360db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl veneer_pool_(this), 361db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl recommended_checkpoint_(Pool::kNoCheckpointRequired) { 36288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois checkpoint_ = GetNextCheckPoint(); 363c68cb64496485710cdb5b8480f8fee287058c93farmvixl} 364c68cb64496485710cdb5b8480f8fee287058c93farmvixl 365c68cb64496485710cdb5b8480f8fee287058c93farmvixl 3660f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixlMacroAssembler::~MacroAssembler() {} 367c68cb64496485710cdb5b8480f8fee287058c93farmvixl 368c68cb64496485710cdb5b8480f8fee287058c93farmvixl 369c68cb64496485710cdb5b8480f8fee287058c93farmvixlvoid MacroAssembler::Reset() { 370c68cb64496485710cdb5b8480f8fee287058c93farmvixl Assembler::Reset(); 371c68cb64496485710cdb5b8480f8fee287058c93farmvixl 372c68cb64496485710cdb5b8480f8fee287058c93farmvixl VIXL_ASSERT(!literal_pool_.IsBlocked()); 373c68cb64496485710cdb5b8480f8fee287058c93farmvixl literal_pool_.Reset(); 3745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl veneer_pool_.Reset(); 375c68cb64496485710cdb5b8480f8fee287058c93farmvixl 37688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois checkpoint_ = GetNextCheckPoint(); 377c68cb64496485710cdb5b8480f8fee287058c93farmvixl} 378c68cb64496485710cdb5b8480f8fee287058c93farmvixl 379c68cb64496485710cdb5b8480f8fee287058c93farmvixl 380c68cb64496485710cdb5b8480f8fee287058c93farmvixlvoid MacroAssembler::FinalizeCode() { 381c68cb64496485710cdb5b8480f8fee287058c93farmvixl if (!literal_pool_.IsEmpty()) literal_pool_.Emit(); 3825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(veneer_pool_.IsEmpty()); 383c68cb64496485710cdb5b8480f8fee287058c93farmvixl 384c68cb64496485710cdb5b8480f8fee287058c93farmvixl Assembler::FinalizeCode(); 385c68cb64496485710cdb5b8480f8fee287058c93farmvixl} 386c68cb64496485710cdb5b8480f8fee287058c93farmvixl 387c68cb64496485710cdb5b8480f8fee287058c93farmvixl 3885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlvoid MacroAssembler::CheckEmitFor(size_t amount) { 3899fbd11bbc6a56071f455df28e08854a848f46c3bAlexandre Rames CheckEmitPoolsFor(amount); 3906a049f97861bd71c69d81f643e42308d28c5de31Alexandre Rames GetBuffer()->EnsureSpaceFor(amount); 3919fbd11bbc6a56071f455df28e08854a848f46c3bAlexandre Rames} 3929fbd11bbc6a56071f455df28e08854a848f46c3bAlexandre Rames 3935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 3949fbd11bbc6a56071f455df28e08854a848f46c3bAlexandre Ramesvoid MacroAssembler::CheckEmitPoolsFor(size_t amount) { 3959fbd11bbc6a56071f455df28e08854a848f46c3bAlexandre Rames literal_pool_.CheckEmitFor(amount); 3969fbd11bbc6a56071f455df28e08854a848f46c3bAlexandre Rames veneer_pool_.CheckEmitFor(amount); 39788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois checkpoint_ = GetNextCheckPoint(); 3985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 3995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 4005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 401330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixlint MacroAssembler::MoveImmediateHelper(MacroAssembler* masm, 4020f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const Register& rd, 403330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl uint64_t imm) { 404330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl bool emit_code = (masm != NULL); 40588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_ASSERT(IsUint32(imm) || IsInt32(imm) || rd.Is64Bits()); 406330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl // The worst case for size is mov 64-bit immediate to sp: 407330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl // * up to 4 instructions to materialise the constant 408330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl // * 1 instruction to move to sp 409330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl MacroEmissionCheckScope guard(masm); 410330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl 411330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl // Immediates on Aarch64 can be produced using an initial value, and zero to 412330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl // three move keep operations. 413330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl // 414330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl // Initial values can be generated with: 415330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl // 1. 64-bit move zero (movz). 416330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl // 2. 32-bit move inverted (movn). 417330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl // 3. 64-bit move inverted. 418330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl // 4. 32-bit orr immediate. 419330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl // 5. 64-bit orr immediate. 420330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl // Move-keep may then be used to modify each of the 16-bit half words. 421330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl // 422330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl // The code below supports all five initial value generators, and 423330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl // applying move-keep operations to move-zero and move-inverted initial 424330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl // values. 425330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl 426330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl // Try to move the immediate in one instruction, and if that fails, switch to 427330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl // using multiple instructions. 428330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl if (OneInstrMoveImmediateHelper(masm, rd, imm)) { 429330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl return 1; 430330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl } else { 431330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl int instruction_count = 0; 43288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois unsigned reg_size = rd.GetSizeInBits(); 433330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl 434330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl // Generic immediate case. Imm will be represented by 435330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl // [imm3, imm2, imm1, imm0], where each imm is 16 bits. 436330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl // A move-zero or move-inverted is generated for the first non-zero or 437330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl // non-0xffff immX, and a move-keep for subsequent non-zero immX. 438330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl 439330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl uint64_t ignored_halfword = 0; 440330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl bool invert_move = false; 441330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl // If the number of 0xffff halfwords is greater than the number of 0x0000 442330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl // halfwords, it's more efficient to use move-inverted. 443330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl if (CountClearHalfWords(~imm, reg_size) > 444330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl CountClearHalfWords(imm, reg_size)) { 445330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl ignored_halfword = 0xffff; 446330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl invert_move = true; 447330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl } 448330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl 449330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl // Mov instructions can't move values into the stack pointer, so set up a 450330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl // temporary register, if needed. 451330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl UseScratchRegisterScope temps; 452330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl Register temp; 453330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl if (emit_code) { 454330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl temps.Open(masm); 455330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl temp = rd.IsSP() ? temps.AcquireSameSizeAs(rd) : rd; 456330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl } 457330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl 458330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl // Iterate through the halfwords. Use movn/movz for the first non-ignored 459330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl // halfword, and movk for subsequent halfwords. 460330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl VIXL_ASSERT((reg_size % 16) == 0); 461330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl bool first_mov_done = false; 4620f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl for (unsigned i = 0; i < (reg_size / 16); i++) { 463330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl uint64_t imm16 = (imm >> (16 * i)) & 0xffff; 464330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl if (imm16 != ignored_halfword) { 465330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl if (!first_mov_done) { 466330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl if (invert_move) { 467330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl if (emit_code) masm->movn(temp, ~imm16 & 0xffff, 16 * i); 468330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl instruction_count++; 469330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl } else { 470330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl if (emit_code) masm->movz(temp, imm16, 16 * i); 471330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl instruction_count++; 472330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl } 473330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl first_mov_done = true; 474330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl } else { 475330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl // Construct a wider constant. 476330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl if (emit_code) masm->movk(temp, imm16, 16 * i); 477330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl instruction_count++; 478330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl } 479330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl } 480330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl } 481330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl 482330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl VIXL_ASSERT(first_mov_done); 483330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl 484330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl // Move the temporary if the original destination register was the stack 485330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl // pointer. 486330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl if (rd.IsSP()) { 487330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl if (emit_code) masm->mov(rd, temp); 488330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl instruction_count++; 489330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl } 490330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl return instruction_count; 491330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl } 492330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl} 493330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl 494330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl 495330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixlbool MacroAssembler::OneInstrMoveImmediateHelper(MacroAssembler* masm, 496330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl const Register& dst, 497330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl int64_t imm) { 498330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl bool emit_code = masm != NULL; 499330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl unsigned n, imm_s, imm_r; 50088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int reg_size = dst.GetSizeInBits(); 501330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl 502330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl if (IsImmMovz(imm, reg_size) && !dst.IsSP()) { 503330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl // Immediate can be represented in a move zero instruction. Movz can't write 504330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl // to the stack pointer. 505330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl if (emit_code) { 506330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl masm->movz(dst, imm); 507330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl } 508330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl return true; 509330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl } else if (IsImmMovn(imm, reg_size) && !dst.IsSP()) { 510330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl // Immediate can be represented in a move negative instruction. Movn can't 511330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl // write to the stack pointer. 512330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl if (emit_code) { 513330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl masm->movn(dst, dst.Is64Bits() ? ~imm : (~imm & kWRegMask)); 514330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl } 515330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl return true; 516330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl } else if (IsImmLogical(imm, reg_size, &n, &imm_s, &imm_r)) { 517330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl // Immediate can be represented in a logical orr instruction. 518330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl VIXL_ASSERT(!dst.IsZero()); 519330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl if (emit_code) { 5200f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl masm->LogicalImmediate(dst, 5210f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl AppropriateZeroRegFor(dst), 5220f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl n, 5230f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl imm_s, 5240f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl imm_r, 5250f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl ORR); 526330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl } 527330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl return true; 528330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl } 529330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl return false; 530330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl} 531330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl 532330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl 533b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixlvoid MacroAssembler::B(Label* label, BranchType type, Register reg, int bit) { 534b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT((reg.Is(NoReg) || (type >= kBranchTypeFirstUsingReg)) && 535b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl ((bit == -1) || (type >= kBranchTypeFirstUsingBit))); 536b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl if (kBranchTypeFirstCondition <= type && type <= kBranchTypeLastCondition) { 537b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl B(static_cast<Condition>(type), label); 538b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl } else { 539b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl switch (type) { 5400f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case always: 5410f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl B(label); 5420f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 5430f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case never: 5440f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 5450f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case reg_zero: 5460f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl Cbz(reg, label); 5470f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 5480f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case reg_not_zero: 5490f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl Cbnz(reg, label); 5500f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 5510f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case reg_bit_clear: 5520f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl Tbz(reg, bit, label); 5530f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 5540f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case reg_bit_set: 5550f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl Tbnz(reg, bit, label); 5560f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 557b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl default: 558b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_UNREACHABLE(); 559b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl } 560b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl } 561b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl} 562b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 5635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 5645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlvoid MacroAssembler::B(Label* label) { 5655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SingleEmissionCheckScope guard(this); 5665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl b(label); 5675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 5685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 5695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 5705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlvoid MacroAssembler::B(Label* label, Condition cond) { 5715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(allow_macro_instructions_); 5725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT((cond != al) && (cond != nv)); 5735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl EmissionCheckScope guard(this, 2 * kInstructionSize); 5745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 5755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (label->IsBound() && LabelIsOutOfRange(label, CondBranchType)) { 5765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Label done; 5775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl b(&done, InvertCondition(cond)); 5785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl b(label); 5795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl bind(&done); 5805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 5815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (!label->IsBound()) { 58288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois veneer_pool_.RegisterUnresolvedBranch(GetCursorOffset(), 5835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl label, 5845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl CondBranchType); 5855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 5865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl b(label, cond); 5875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 5885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 5895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 5905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 5915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlvoid MacroAssembler::Cbnz(const Register& rt, Label* label) { 5925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(allow_macro_instructions_); 5935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(!rt.IsZero()); 5945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl EmissionCheckScope guard(this, 2 * kInstructionSize); 5955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 5965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (label->IsBound() && LabelIsOutOfRange(label, CondBranchType)) { 5975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Label done; 5985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl cbz(rt, &done); 5995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl b(label); 6005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl bind(&done); 6015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 6025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (!label->IsBound()) { 60388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois veneer_pool_.RegisterUnresolvedBranch(GetCursorOffset(), 6045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl label, 6055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl CompareBranchType); 6065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 6075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl cbnz(rt, label); 6085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 6095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 6105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 6115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 6125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlvoid MacroAssembler::Cbz(const Register& rt, Label* label) { 6135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(allow_macro_instructions_); 6145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(!rt.IsZero()); 6155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl EmissionCheckScope guard(this, 2 * kInstructionSize); 6165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 6175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (label->IsBound() && LabelIsOutOfRange(label, CondBranchType)) { 6185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Label done; 6195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl cbnz(rt, &done); 6205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl b(label); 6215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl bind(&done); 6225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 6235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (!label->IsBound()) { 62488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois veneer_pool_.RegisterUnresolvedBranch(GetCursorOffset(), 6255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl label, 6265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl CompareBranchType); 6275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 6285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl cbz(rt, label); 6295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 6305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 6315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 6325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 6335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlvoid MacroAssembler::Tbnz(const Register& rt, unsigned bit_pos, Label* label) { 6345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(allow_macro_instructions_); 6355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(!rt.IsZero()); 6365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl EmissionCheckScope guard(this, 2 * kInstructionSize); 6375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 6385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (label->IsBound() && LabelIsOutOfRange(label, TestBranchType)) { 6395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Label done; 6405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl tbz(rt, bit_pos, &done); 6415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl b(label); 6425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl bind(&done); 6435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 6445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (!label->IsBound()) { 64588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois veneer_pool_.RegisterUnresolvedBranch(GetCursorOffset(), 6465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl label, 6475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl TestBranchType); 6485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 6495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl tbnz(rt, bit_pos, label); 6505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 6515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 6525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 6535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 6545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlvoid MacroAssembler::Tbz(const Register& rt, unsigned bit_pos, Label* label) { 6555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(allow_macro_instructions_); 6565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(!rt.IsZero()); 6575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl EmissionCheckScope guard(this, 2 * kInstructionSize); 6585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 6595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (label->IsBound() && LabelIsOutOfRange(label, TestBranchType)) { 6605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Label done; 6615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl tbnz(rt, bit_pos, &done); 6625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl b(label); 6635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl bind(&done); 6645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 6655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (!label->IsBound()) { 66688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois veneer_pool_.RegisterUnresolvedBranch(GetCursorOffset(), 6675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl label, 6685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl TestBranchType); 6695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 6705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl tbz(rt, bit_pos, label); 6715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 6725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 6735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 6745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 6755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlvoid MacroAssembler::Bind(Label* label) { 6765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(allow_macro_instructions_); 6775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl veneer_pool_.DeleteUnresolvedBranchInfoForLabel(label); 6785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl bind(label); 6795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 6805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 6815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 6825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl// Bind a label to a specified offset from the start of the buffer. 6835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlvoid MacroAssembler::BindToOffset(Label* label, ptrdiff_t offset) { 6845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(allow_macro_instructions_); 6855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl veneer_pool_.DeleteUnresolvedBranchInfoForLabel(label); 6865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Assembler::BindToOffset(label, offset); 6875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 6885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 6895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 690ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlvoid MacroAssembler::And(const Register& rd, 691ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl const Register& rn, 692f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl const Operand& operand) { 693b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT(allow_macro_instructions_); 694f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl LogicalMacro(rd, rn, operand, AND); 695f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl} 696f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl 697f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl 698f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixlvoid MacroAssembler::Ands(const Register& rd, 699f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl const Register& rn, 700f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl const Operand& operand) { 701b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT(allow_macro_instructions_); 702f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl LogicalMacro(rd, rn, operand, ANDS); 703ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl} 704ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 705ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 7060f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixlvoid MacroAssembler::Tst(const Register& rn, const Operand& operand) { 707b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT(allow_macro_instructions_); 708f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl Ands(AppropriateZeroRegFor(rn), rn, operand); 709ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl} 710ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 711ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 712ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlvoid MacroAssembler::Bic(const Register& rd, 713ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl const Register& rn, 714f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl const Operand& operand) { 715b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT(allow_macro_instructions_); 716f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl LogicalMacro(rd, rn, operand, BIC); 717f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl} 718f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl 719f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl 720f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixlvoid MacroAssembler::Bics(const Register& rd, 721f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl const Register& rn, 722f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl const Operand& operand) { 723b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT(allow_macro_instructions_); 724f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl LogicalMacro(rd, rn, operand, BICS); 725ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl} 726ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 727ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 728ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlvoid MacroAssembler::Orr(const Register& rd, 729ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl const Register& rn, 730ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl const Operand& operand) { 731b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT(allow_macro_instructions_); 732ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LogicalMacro(rd, rn, operand, ORR); 733ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl} 734ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 735ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 736ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlvoid MacroAssembler::Orn(const Register& rd, 737ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl const Register& rn, 738ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl const Operand& operand) { 739b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT(allow_macro_instructions_); 740ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LogicalMacro(rd, rn, operand, ORN); 741ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl} 742ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 743ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 744ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlvoid MacroAssembler::Eor(const Register& rd, 745ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl const Register& rn, 746ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl const Operand& operand) { 747b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT(allow_macro_instructions_); 748ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LogicalMacro(rd, rn, operand, EOR); 749ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl} 750ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 751ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 752ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlvoid MacroAssembler::Eon(const Register& rd, 753ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl const Register& rn, 754ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl const Operand& operand) { 755b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT(allow_macro_instructions_); 756ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LogicalMacro(rd, rn, operand, EON); 757ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl} 758ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 759ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 760ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlvoid MacroAssembler::LogicalMacro(const Register& rd, 761ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl const Register& rn, 762ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl const Operand& operand, 763ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LogicalOp op) { 764c68cb64496485710cdb5b8480f8fee287058c93farmvixl // The worst case for size is logical immediate to sp: 765c68cb64496485710cdb5b8480f8fee287058c93farmvixl // * up to 4 instructions to materialise the constant 766c68cb64496485710cdb5b8480f8fee287058c93farmvixl // * 1 instruction to do the operation 767c68cb64496485710cdb5b8480f8fee287058c93farmvixl // * 1 instruction to move to sp 768c68cb64496485710cdb5b8480f8fee287058c93farmvixl MacroEmissionCheckScope guard(this); 769b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl UseScratchRegisterScope temps(this); 770b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 771ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl if (operand.IsImmediate()) { 77285919f840e8ddd06573def57eb587cc77661e7d0Jacob Bramley uint64_t immediate = operand.GetImmediate(); 77388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois unsigned reg_size = rd.GetSizeInBits(); 774ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 775ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // If the operation is NOT, invert the operation and immediate. 776ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl if ((op & NOT) == NOT) { 777ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl op = static_cast<LogicalOp>(op & ~NOT); 778ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl immediate = ~immediate; 779ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 780ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 7814a102baf640077d6794c0b33bb976f94b86c532barmvixl // Ignore the top 32 bits of an immediate if we're moving to a W register. 7824a102baf640077d6794c0b33bb976f94b86c532barmvixl if (rd.Is32Bits()) { 7834a102baf640077d6794c0b33bb976f94b86c532barmvixl // Check that the top 32 bits are consistent. 7844a102baf640077d6794c0b33bb976f94b86c532barmvixl VIXL_ASSERT(((immediate >> kWRegSize) == 0) || 78585919f840e8ddd06573def57eb587cc77661e7d0Jacob Bramley ((immediate >> kWRegSize) == 0xffffffff)); 7864a102baf640077d6794c0b33bb976f94b86c532barmvixl immediate &= kWRegMask; 7874a102baf640077d6794c0b33bb976f94b86c532barmvixl } 7884a102baf640077d6794c0b33bb976f94b86c532barmvixl 78988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_ASSERT(rd.Is64Bits() || IsUint32(immediate)); 7904a102baf640077d6794c0b33bb976f94b86c532barmvixl 791ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // Special cases for all set or all clear immediates. 792ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl if (immediate == 0) { 793ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl switch (op) { 794ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl case AND: 795ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl Mov(rd, 0); 796ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl return; 7976e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl case ORR: 7986e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl VIXL_FALLTHROUGH(); 799ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl case EOR: 800ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl Mov(rd, rn); 801ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl return; 8026e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl case ANDS: 8036e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl VIXL_FALLTHROUGH(); 804ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl case BICS: 805ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl break; 806ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl default: 807b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_UNREACHABLE(); 808ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 80985919f840e8ddd06573def57eb587cc77661e7d0Jacob Bramley } else if ((rd.Is64Bits() && (immediate == UINT64_C(0xffffffffffffffff))) || 81085919f840e8ddd06573def57eb587cc77661e7d0Jacob Bramley (rd.Is32Bits() && (immediate == UINT64_C(0x00000000ffffffff)))) { 811ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl switch (op) { 812ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl case AND: 813ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl Mov(rd, rn); 814ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl return; 815ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl case ORR: 816ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl Mov(rd, immediate); 817ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl return; 818ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl case EOR: 819ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl Mvn(rd, rn); 820ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl return; 8216e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl case ANDS: 8226e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl VIXL_FALLTHROUGH(); 823ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl case BICS: 824ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl break; 825ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl default: 826b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_UNREACHABLE(); 827ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 828ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 829ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 830ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl unsigned n, imm_s, imm_r; 831ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl if (IsImmLogical(immediate, reg_size, &n, &imm_s, &imm_r)) { 832ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // Immediate can be encoded in the instruction. 833ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LogicalImmediate(rd, rn, n, imm_s, imm_r, op); 834ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } else { 835ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // Immediate can't be encoded: synthesize using move immediate. 836b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl Register temp = temps.AcquireSameSizeAs(rn); 8374a102baf640077d6794c0b33bb976f94b86c532barmvixl Operand imm_operand = MoveImmediateForShiftedOp(temp, immediate); 8384a102baf640077d6794c0b33bb976f94b86c532barmvixl 839ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl if (rd.Is(sp)) { 840ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // If rd is the stack pointer we cannot use it as the destination 841ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // register so we use the temp register as an intermediate again. 8424a102baf640077d6794c0b33bb976f94b86c532barmvixl Logical(temp, rn, imm_operand, op); 843ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl Mov(sp, temp); 844ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } else { 8454a102baf640077d6794c0b33bb976f94b86c532barmvixl Logical(rd, rn, imm_operand, op); 846ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 847ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 848ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } else if (operand.IsExtendedRegister()) { 84988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_ASSERT(operand.GetRegister().GetSizeInBits() <= rd.GetSizeInBits()); 850ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // Add/sub extended supports shift <= 4. We want to support exactly the 851ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // same modes here. 85288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_ASSERT(operand.GetShiftAmount() <= 4); 85388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_ASSERT( 85488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois operand.GetRegister().Is64Bits() || 85588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois ((operand.GetExtend() != UXTX) && (operand.GetExtend() != SXTX))); 856b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 85788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois temps.Exclude(operand.GetRegister()); 858b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl Register temp = temps.AcquireSameSizeAs(rn); 8590f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl EmitExtendShift(temp, 86088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois operand.GetRegister(), 86188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois operand.GetExtend(), 86288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois operand.GetShiftAmount()); 863ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl Logical(rd, rn, Operand(temp), op); 864ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } else { 865ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // The operand can be encoded in the instruction. 866b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT(operand.IsShiftedRegister()); 867ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl Logical(rd, rn, operand, op); 868ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 869ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl} 870ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 871ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 872f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixlvoid MacroAssembler::Mov(const Register& rd, 873f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl const Operand& operand, 874f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl DiscardMoveMode discard_mode) { 875b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT(allow_macro_instructions_); 876c68cb64496485710cdb5b8480f8fee287058c93farmvixl // The worst case for size is mov immediate with up to 4 instructions. 877c68cb64496485710cdb5b8480f8fee287058c93farmvixl MacroEmissionCheckScope guard(this); 878c68cb64496485710cdb5b8480f8fee287058c93farmvixl 879ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl if (operand.IsImmediate()) { 880ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // Call the macro assembler for generic immediates. 88188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois Mov(rd, operand.GetImmediate()); 88288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } else if (operand.IsShiftedRegister() && (operand.GetShiftAmount() != 0)) { 883ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // Emit a shift instruction if moving a shifted register. This operation 884ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // could also be achieved using an orr instruction (like orn used by Mvn), 885ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // but using a shift instruction makes the disassembly clearer. 88688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois EmitShift(rd, 88788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois operand.GetRegister(), 88888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois operand.GetShift(), 88988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois operand.GetShiftAmount()); 890ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } else if (operand.IsExtendedRegister()) { 891ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // Emit an extend instruction if moving an extended register. This handles 892ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // extend with post-shift operations, too. 8930f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl EmitExtendShift(rd, 89488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois operand.GetRegister(), 89588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois operand.GetExtend(), 89688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois operand.GetShiftAmount()); 897ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } else { 8981c78c34397f2c08c012733cc661076e8bd029eabAlexandre Rames Mov(rd, operand.GetRegister(), discard_mode); 899ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 900ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl} 901ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 902ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 9035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlvoid MacroAssembler::Movi16bitHelper(const VRegister& vd, uint64_t imm) { 90488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_ASSERT(IsUint16(imm)); 9055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int byte1 = (imm & 0xff); 9065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int byte2 = ((imm >> 8) & 0xff); 9075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (byte1 == byte2) { 9085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl movi(vd.Is64Bits() ? vd.V8B() : vd.V16B(), byte1); 9095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else if (byte1 == 0) { 9105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl movi(vd, byte2, LSL, 8); 9115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else if (byte2 == 0) { 9125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl movi(vd, byte1); 9135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else if (byte1 == 0xff) { 9145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl mvni(vd, ~byte2 & 0xff, LSL, 8); 9155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else if (byte2 == 0xff) { 9165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl mvni(vd, ~byte1 & 0xff); 9175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 9185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl UseScratchRegisterScope temps(this); 9195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Register temp = temps.AcquireW(); 9205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl movz(temp, imm); 9215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dup(vd, temp); 9225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 9235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 9245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 9255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 9265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlvoid MacroAssembler::Movi32bitHelper(const VRegister& vd, uint64_t imm) { 92788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_ASSERT(IsUint32(imm)); 9285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 9295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint8_t bytes[sizeof(imm)]; 9305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl memcpy(bytes, &imm, sizeof(imm)); 9315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 9325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // All bytes are either 0x00 or 0xff. 9335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl { 9345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl bool all0orff = true; 9355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < 4; ++i) { 9365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if ((bytes[i] != 0) && (bytes[i] != 0xff)) { 9375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl all0orff = false; 9385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl break; 9395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 9405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 9415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 9425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (all0orff == true) { 9435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl movi(vd.Is64Bits() ? vd.V1D() : vd.V2D(), ((imm << 32) | imm)); 9445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return; 9455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 9465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 9475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 9485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Of the 4 bytes, only one byte is non-zero. 9495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < 4; i++) { 9505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if ((imm & (0xff << (i * 8))) == imm) { 9515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl movi(vd, bytes[i], LSL, i * 8); 9525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return; 9535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 9545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 9555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 9565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Of the 4 bytes, only one byte is not 0xff. 9575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < 4; i++) { 9585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint32_t mask = ~(0xff << (i * 8)); 9595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if ((imm & mask) == mask) { 9605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl mvni(vd, ~bytes[i] & 0xff, LSL, i * 8); 9615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return; 9625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 9635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 9645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 9655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Immediate is of the form 0x00MMFFFF. 9665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if ((imm & 0xff00ffff) == 0x0000ffff) { 9675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl movi(vd, bytes[2], MSL, 16); 9685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return; 9695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 9705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 9715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Immediate is of the form 0x0000MMFF. 9725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if ((imm & 0xffff00ff) == 0x000000ff) { 9735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl movi(vd, bytes[1], MSL, 8); 9745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return; 9755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 9765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 9775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Immediate is of the form 0xFFMM0000. 9785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if ((imm & 0xff00ffff) == 0xff000000) { 9795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl mvni(vd, ~bytes[2] & 0xff, MSL, 16); 9805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return; 9815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 9825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Immediate is of the form 0xFFFFMM00. 9835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if ((imm & 0xffff00ff) == 0xffff0000) { 9845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl mvni(vd, ~bytes[1] & 0xff, MSL, 8); 9855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return; 9865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 9875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 9885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Top and bottom 16-bits are equal. 9895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (((imm >> 16) & 0xffff) == (imm & 0xffff)) { 9905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Movi16bitHelper(vd.Is64Bits() ? vd.V4H() : vd.V8H(), imm & 0xffff); 9915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return; 9925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 9935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 9945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Default case. 9955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl { 9965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl UseScratchRegisterScope temps(this); 9975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Register temp = temps.AcquireW(); 9985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Mov(temp, imm); 9995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dup(vd, temp); 10005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 10015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 10025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 10035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 10045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlvoid MacroAssembler::Movi64bitHelper(const VRegister& vd, uint64_t imm) { 10055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // All bytes are either 0x00 or 0xff. 10065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl { 10075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl bool all0orff = true; 10085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < 8; ++i) { 10095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int byteval = (imm >> (i * 8)) & 0xff; 10105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (byteval != 0 && byteval != 0xff) { 10115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl all0orff = false; 10125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl break; 10135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 10145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 10155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (all0orff == true) { 10165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl movi(vd, imm); 10175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return; 10185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 10195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 10205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 10215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Top and bottom 32-bits are equal. 10225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (((imm >> 32) & 0xffffffff) == (imm & 0xffffffff)) { 10235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Movi32bitHelper(vd.Is64Bits() ? vd.V2S() : vd.V4S(), imm & 0xffffffff); 10245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return; 10255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 10265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 10275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Default case. 10285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl { 10295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl UseScratchRegisterScope temps(this); 10305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Register temp = temps.AcquireX(); 10315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Mov(temp, imm); 10325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (vd.Is1D()) { 10335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl mov(vd.D(), 0, temp); 10345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 10355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dup(vd.V2D(), temp); 10365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 10375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 10385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 10395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 10405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 10415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlvoid MacroAssembler::Movi(const VRegister& vd, 10425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t imm, 10435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Shift shift, 10445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift_amount) { 10455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(allow_macro_instructions_); 10465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl MacroEmissionCheckScope guard(this); 10475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (shift_amount != 0 || shift != LSL) { 10485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl movi(vd, imm, shift, shift_amount); 10495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else if (vd.Is8B() || vd.Is16B()) { 10505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // 8-bit immediate. 105188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_ASSERT(IsUint8(imm)); 10525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl movi(vd, imm); 10535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else if (vd.Is4H() || vd.Is8H()) { 10545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // 16-bit immediate. 10555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Movi16bitHelper(vd, imm); 10565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else if (vd.Is2S() || vd.Is4S()) { 10575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // 32-bit immediate. 10585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Movi32bitHelper(vd, imm); 10595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 10605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // 64-bit immediate. 10615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Movi64bitHelper(vd, imm); 10625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 10635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 10645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 10655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 10660f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixlvoid MacroAssembler::Movi(const VRegister& vd, uint64_t hi, uint64_t lo) { 10675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // TODO: Move 128-bit values in a more efficient way. 10685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(vd.Is128Bits()); 10695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl UseScratchRegisterScope temps(this); 10705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Movi(vd.V2D(), lo); 10715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Register temp = temps.AcquireX(); 10725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Mov(temp, hi); 10735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Ins(vd.V2D(), 1, temp); 10745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 10755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 10765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 1077ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlvoid MacroAssembler::Mvn(const Register& rd, const Operand& operand) { 1078b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT(allow_macro_instructions_); 1079c68cb64496485710cdb5b8480f8fee287058c93farmvixl // The worst case for size is mvn immediate with up to 4 instructions. 1080c68cb64496485710cdb5b8480f8fee287058c93farmvixl MacroEmissionCheckScope guard(this); 1081c68cb64496485710cdb5b8480f8fee287058c93farmvixl 1082ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl if (operand.IsImmediate()) { 1083ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // Call the macro assembler for generic immediates. 108488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois Mvn(rd, operand.GetImmediate()); 1085ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } else if (operand.IsExtendedRegister()) { 1086b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl UseScratchRegisterScope temps(this); 108788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois temps.Exclude(operand.GetRegister()); 1088b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 1089ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // Emit two instructions for the extend case. This differs from Mov, as 1090ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // the extend and invert can't be achieved in one instruction. 1091b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl Register temp = temps.AcquireSameSizeAs(rd); 10920f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl EmitExtendShift(temp, 109388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois operand.GetRegister(), 109488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois operand.GetExtend(), 109588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois operand.GetShiftAmount()); 1096ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl mvn(rd, Operand(temp)); 1097ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } else { 1098ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // Otherwise, register and shifted register cases can be handled by the 1099ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // assembler directly, using orn. 1100ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl mvn(rd, operand); 1101ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 1102ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl} 1103ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 1104ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 1105ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlvoid MacroAssembler::Mov(const Register& rd, uint64_t imm) { 1106b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT(allow_macro_instructions_); 1107330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl MoveImmediateHelper(this, rd, imm); 1108ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl} 1109ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 1110ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 1111ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlvoid MacroAssembler::Ccmp(const Register& rn, 1112ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl const Operand& operand, 1113ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl StatusFlags nzcv, 1114ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl Condition cond) { 1115b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT(allow_macro_instructions_); 111688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois if (operand.IsImmediate() && (operand.GetImmediate() < 0)) { 111788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois ConditionalCompareMacro(rn, -operand.GetImmediate(), nzcv, cond, CCMN); 1118f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl } else { 1119f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl ConditionalCompareMacro(rn, operand, nzcv, cond, CCMP); 1120f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl } 1121ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl} 1122ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 1123ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 1124ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlvoid MacroAssembler::Ccmn(const Register& rn, 1125ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl const Operand& operand, 1126ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl StatusFlags nzcv, 1127ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl Condition cond) { 1128b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT(allow_macro_instructions_); 112988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois if (operand.IsImmediate() && (operand.GetImmediate() < 0)) { 113088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois ConditionalCompareMacro(rn, -operand.GetImmediate(), nzcv, cond, CCMP); 1131f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl } else { 1132f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl ConditionalCompareMacro(rn, operand, nzcv, cond, CCMN); 1133f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl } 1134ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl} 1135ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 1136ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 1137ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlvoid MacroAssembler::ConditionalCompareMacro(const Register& rn, 1138ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl const Operand& operand, 1139ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl StatusFlags nzcv, 1140ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl Condition cond, 1141ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl ConditionalCompareOp op) { 1142b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT((cond != al) && (cond != nv)); 1143c68cb64496485710cdb5b8480f8fee287058c93farmvixl // The worst case for size is ccmp immediate: 1144c68cb64496485710cdb5b8480f8fee287058c93farmvixl // * up to 4 instructions to materialise the constant 1145c68cb64496485710cdb5b8480f8fee287058c93farmvixl // * 1 instruction for ccmp 1146c68cb64496485710cdb5b8480f8fee287058c93farmvixl MacroEmissionCheckScope guard(this); 1147c68cb64496485710cdb5b8480f8fee287058c93farmvixl 114888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois if ((operand.IsShiftedRegister() && (operand.GetShiftAmount() == 0)) || 114988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois (operand.IsImmediate() && 115088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois IsImmConditionalCompare(operand.GetImmediate()))) { 1151ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // The immediate can be encoded in the instruction, or the operand is an 1152ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // unshifted register: call the assembler. 1153ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl ConditionalCompare(rn, operand, nzcv, cond, op); 1154ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } else { 1155b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl UseScratchRegisterScope temps(this); 1156ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // The operand isn't directly supported by the instruction: perform the 1157ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // operation on a temporary register. 1158b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl Register temp = temps.AcquireSameSizeAs(rn); 1159f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl Mov(temp, operand); 1160f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl ConditionalCompare(rn, temp, nzcv, cond, op); 1161f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl } 1162f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl} 1163f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl 1164f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl 11650f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixlvoid MacroAssembler::CselHelper(MacroAssembler* masm, 11660f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const Register& rd, 11670f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl Operand left, 11680f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl Operand right, 11690f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl Condition cond, 11700f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl bool* should_synthesise_left, 11710f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl bool* should_synthesise_right) { 11720f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl bool emit_code = (masm != NULL); 11730f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl 11740f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl VIXL_ASSERT(!emit_code || masm->allow_macro_instructions_); 1175b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT((cond != al) && (cond != nv)); 11760f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl VIXL_ASSERT(!rd.IsZero() && !rd.IsSP()); 117788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_ASSERT(left.IsImmediate() || !left.GetRegister().IsSP()); 117888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_ASSERT(right.IsImmediate() || !right.GetRegister().IsSP()); 11790f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl 11800f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl if (should_synthesise_left != NULL) *should_synthesise_left = false; 11810f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl if (should_synthesise_right != NULL) *should_synthesise_right = false; 11820f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl 11830f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl // The worst case for size occurs when the inputs are two non encodable 11840f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl // constants: 11850f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl // * up to 4 instructions to materialise the left constant 11860f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl // * up to 4 instructions to materialise the right constant 1187c68cb64496485710cdb5b8480f8fee287058c93farmvixl // * 1 instruction for csel 11880f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl EmissionCheckScope guard(masm, 9 * kInstructionSize); 11890f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl UseScratchRegisterScope temps; 11900f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl if (masm != NULL) { 11910f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl temps.Open(masm); 11920f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl } 11930f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl 11940f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl // Try to handle cases where both inputs are immediates. 11950f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl bool left_is_immediate = left.IsImmediate() || left.IsZero(); 11960f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl bool right_is_immediate = right.IsImmediate() || right.IsZero(); 11970f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl if (left_is_immediate && right_is_immediate && 11980f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl CselSubHelperTwoImmediates(masm, 11990f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl rd, 12000f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl left.GetEquivalentImmediate(), 12010f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl right.GetEquivalentImmediate(), 12020f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl cond, 12030f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl should_synthesise_left, 12040f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl should_synthesise_right)) { 12050f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl return; 12060f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl } 1207c68cb64496485710cdb5b8480f8fee287058c93farmvixl 12080f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl // Handle cases where one of the two inputs is -1, 0, or 1. 12090f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl bool left_is_small_immediate = 12100f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl left_is_immediate && ((-1 <= left.GetEquivalentImmediate()) && 12110f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl (left.GetEquivalentImmediate() <= 1)); 12120f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl bool right_is_small_immediate = 12130f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl right_is_immediate && ((-1 <= right.GetEquivalentImmediate()) && 12140f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl (right.GetEquivalentImmediate() <= 1)); 12150f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl if (right_is_small_immediate || left_is_small_immediate) { 12160f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl bool swapped_inputs = false; 12170f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl if (!right_is_small_immediate) { 12180f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl std::swap(left, right); 12190f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl cond = InvertCondition(cond); 12200f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl swapped_inputs = true; 12210f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl } 12220f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl CselSubHelperRightSmallImmediate(masm, 12230f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl &temps, 12240f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl rd, 12250f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl left, 12260f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl right, 12270f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl cond, 12280f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl swapped_inputs ? should_synthesise_right 12290f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl : should_synthesise_left); 12300f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl return; 12310f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl } 12320f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl 12330f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl // Otherwise both inputs need to be available in registers. Synthesise them 12340f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl // if necessary and emit the `csel`. 12350f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl if (!left.IsPlainRegister()) { 12360f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl if (emit_code) { 12370f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl Register temp = temps.AcquireSameSizeAs(rd); 12380f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl masm->Mov(temp, left); 12390f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl left = temp; 12400f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl } 12410f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl if (should_synthesise_left != NULL) *should_synthesise_left = true; 12420f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl } 12430f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl if (!right.IsPlainRegister()) { 12440f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl if (emit_code) { 12450f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl Register temp = temps.AcquireSameSizeAs(rd); 12460f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl masm->Mov(temp, right); 12470f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl right = temp; 12480f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl } 12490f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl if (should_synthesise_right != NULL) *should_synthesise_right = true; 12500f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl } 12510f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl if (emit_code) { 12520f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl VIXL_ASSERT(left.IsPlainRegister() && right.IsPlainRegister()); 125388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois if (left.GetRegister().Is(right.GetRegister())) { 125488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois masm->Mov(rd, left.GetRegister()); 12550f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl } else { 125688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois masm->csel(rd, left.GetRegister(), right.GetRegister(), cond); 12570f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl } 12580f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl } 12590f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl} 12600f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl 12610f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl 12620f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixlbool MacroAssembler::CselSubHelperTwoImmediates(MacroAssembler* masm, 12630f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const Register& rd, 12640f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl int64_t left, 12650f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl int64_t right, 12660f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl Condition cond, 12670f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl bool* should_synthesise_left, 12680f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl bool* should_synthesise_right) { 12690f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl bool emit_code = (masm != NULL); 12700f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl if (should_synthesise_left != NULL) *should_synthesise_left = false; 12710f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl if (should_synthesise_right != NULL) *should_synthesise_right = false; 12720f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl 12730f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl if (left == right) { 12740f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl if (emit_code) masm->Mov(rd, left); 12750f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl return true; 12760f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl } else if (left == -right) { 12770f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl if (should_synthesise_right != NULL) *should_synthesise_right = true; 12780f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl if (emit_code) { 12790f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl masm->Mov(rd, right); 12800f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl masm->Cneg(rd, rd, cond); 12810f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl } 12820f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl return true; 12830f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl } 12840f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl 12850f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl if (CselSubHelperTwoOrderedImmediates(masm, rd, left, right, cond)) { 12860f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl return true; 12870f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl } else { 12880f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl std::swap(left, right); 12890f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl if (CselSubHelperTwoOrderedImmediates(masm, 12900f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl rd, 12910f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl left, 12920f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl right, 12930f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl InvertCondition(cond))) { 12940f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl return true; 12950f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl } 12960f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl } 12970f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl 12980f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl // TODO: Handle more situations. For example handle `csel rd, #5, #6, cond` 12990f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl // with `cinc`. 13000f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl return false; 13010f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl} 13020f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl 13030f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl 13040f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixlbool MacroAssembler::CselSubHelperTwoOrderedImmediates(MacroAssembler* masm, 13050f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const Register& rd, 13060f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl int64_t left, 13070f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl int64_t right, 13080f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl Condition cond) { 13090f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl bool emit_code = (masm != NULL); 13100f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl 1311dd47fed5e4cd380a8a5a3dd4ab80d8531a5e7c93Alexandre Rames if ((left == 1) && (right == 0)) { 13120f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl if (emit_code) masm->cset(rd, cond); 13130f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl return true; 1314dd47fed5e4cd380a8a5a3dd4ab80d8531a5e7c93Alexandre Rames } else if ((left == -1) && (right == 0)) { 1315dd47fed5e4cd380a8a5a3dd4ab80d8531a5e7c93Alexandre Rames if (emit_code) masm->csetm(rd, cond); 13160f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl return true; 13170f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl } 13180f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl return false; 13190f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl} 13200f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl 13210f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl 13220f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixlvoid MacroAssembler::CselSubHelperRightSmallImmediate( 13230f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl MacroAssembler* masm, 13240f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl UseScratchRegisterScope* temps, 13250f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const Register& rd, 13260f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const Operand& left, 13270f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const Operand& right, 13280f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl Condition cond, 13290f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl bool* should_synthesise_left) { 13300f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl bool emit_code = (masm != NULL); 13310f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl VIXL_ASSERT((right.IsImmediate() || right.IsZero()) && 13320f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl (-1 <= right.GetEquivalentImmediate()) && 13330f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl (right.GetEquivalentImmediate() <= 1)); 13340f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl Register left_register; 13350f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl 13360f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl if (left.IsPlainRegister()) { 133788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois left_register = left.GetRegister(); 13380f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl } else { 13390f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl if (emit_code) { 13400f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl left_register = temps->AcquireSameSizeAs(rd); 13410f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl masm->Mov(left_register, left); 13420f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl } 13430f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl if (should_synthesise_left != NULL) *should_synthesise_left = true; 13440f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl } 13450f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl if (emit_code) { 13460f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl int64_t imm = right.GetEquivalentImmediate(); 13470f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl Register zr = AppropriateZeroRegFor(rd); 1348f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl if (imm == 0) { 13490f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl masm->csel(rd, left_register, zr, cond); 1350f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl } else if (imm == 1) { 13510f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl masm->csinc(rd, left_register, zr, cond); 1352ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } else { 13530f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl VIXL_ASSERT(imm == -1); 13540f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl masm->csinv(rd, left_register, zr, cond); 1355ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 1356ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 1357ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl} 1358ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 1359ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 1360ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlvoid MacroAssembler::Add(const Register& rd, 1361ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl const Register& rn, 13626e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl const Operand& operand, 13636e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl FlagsUpdate S) { 1364b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT(allow_macro_instructions_); 136588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois if (operand.IsImmediate() && (operand.GetImmediate() < 0) && 136688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois IsImmAddSub(-operand.GetImmediate())) { 136788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois AddSubMacro(rd, rn, -operand.GetImmediate(), S, SUB); 1368ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } else { 13696e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl AddSubMacro(rd, rn, operand, S, ADD); 1370f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl } 1371f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl} 1372f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl 1373f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl 1374f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixlvoid MacroAssembler::Adds(const Register& rd, 1375f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl const Register& rn, 1376f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl const Operand& operand) { 13776e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl Add(rd, rn, operand, SetFlags); 1378ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl} 1379ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 1380ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 1381ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlvoid MacroAssembler::Sub(const Register& rd, 1382ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl const Register& rn, 13836e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl const Operand& operand, 13846e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl FlagsUpdate S) { 1385b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT(allow_macro_instructions_); 138688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois if (operand.IsImmediate() && (operand.GetImmediate() < 0) && 138788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois IsImmAddSub(-operand.GetImmediate())) { 138888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois AddSubMacro(rd, rn, -operand.GetImmediate(), S, ADD); 1389f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl } else { 13906e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl AddSubMacro(rd, rn, operand, S, SUB); 1391f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl } 1392f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl} 1393f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl 1394f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl 1395f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixlvoid MacroAssembler::Subs(const Register& rd, 1396f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl const Register& rn, 1397f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl const Operand& operand) { 13986e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl Sub(rd, rn, operand, SetFlags); 1399ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl} 1400ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 1401ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 1402ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlvoid MacroAssembler::Cmn(const Register& rn, const Operand& operand) { 1403b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT(allow_macro_instructions_); 1404f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl Adds(AppropriateZeroRegFor(rn), rn, operand); 1405ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl} 1406ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 1407ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 1408ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlvoid MacroAssembler::Cmp(const Register& rn, const Operand& operand) { 1409b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT(allow_macro_instructions_); 1410f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl Subs(AppropriateZeroRegFor(rn), rn, operand); 1411ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl} 1412ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 1413ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 14140f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixlvoid MacroAssembler::Fcmp(const FPRegister& fn, 14150f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl double value, 14166e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl FPTrapFlags trap) { 1417b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT(allow_macro_instructions_); 1418c68cb64496485710cdb5b8480f8fee287058c93farmvixl // The worst case for size is: 1419c68cb64496485710cdb5b8480f8fee287058c93farmvixl // * 1 to materialise the constant, using literal pool if necessary 14206e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // * 1 instruction for fcmp{e} 1421c68cb64496485710cdb5b8480f8fee287058c93farmvixl MacroEmissionCheckScope guard(this); 1422b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl if (value != 0.0) { 1423b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl UseScratchRegisterScope temps(this); 1424b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl FPRegister tmp = temps.AcquireSameSizeAs(fn); 1425b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl Fmov(tmp, value); 14266e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl FPCompareMacro(fn, tmp, trap); 1427b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl } else { 14286e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl FPCompareMacro(fn, value, trap); 1429b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl } 1430b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl} 1431b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 1432b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 14336e2c8275d5f34a531fe1eef7a7aa877601be8558armvixlvoid MacroAssembler::Fcmpe(const FPRegister& fn, double value) { 14346e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl Fcmp(fn, value, EnableTrap); 14356e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl} 14366e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 14376e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 14385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlvoid MacroAssembler::Fmov(VRegister vd, double imm) { 1439b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT(allow_macro_instructions_); 1440c68cb64496485710cdb5b8480f8fee287058c93farmvixl // Floating point immediates are loaded through the literal pool. 1441c68cb64496485710cdb5b8480f8fee287058c93farmvixl MacroEmissionCheckScope guard(this); 1442c68cb64496485710cdb5b8480f8fee287058c93farmvixl 14435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (vd.Is1S() || vd.Is2S() || vd.Is4S()) { 14445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Fmov(vd, static_cast<float>(imm)); 1445b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl return; 1446b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl } 1447b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 14485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(vd.Is1D() || vd.Is2D()); 1449b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl if (IsImmFP64(imm)) { 14505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl fmov(vd, imm); 1451b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl } else { 145288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois uint64_t rawbits = DoubleToRawbits(imm); 14535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (vd.IsScalar()) { 14545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (rawbits == 0) { 14555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl fmov(vd, xzr); 14565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 1457db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl ldr(vd, 1458db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl new Literal<double>(imm, 1459db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl &literal_pool_, 1460db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl RawLiteral::kDeletedOnPlacementByPool)); 14615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 14625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 14635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // TODO: consider NEON support for load literal. 14645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Movi(vd, rawbits); 14655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 1466b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl } 1467b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl} 1468b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 1469b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 14705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlvoid MacroAssembler::Fmov(VRegister vd, float imm) { 1471b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT(allow_macro_instructions_); 1472c68cb64496485710cdb5b8480f8fee287058c93farmvixl // Floating point immediates are loaded through the literal pool. 1473c68cb64496485710cdb5b8480f8fee287058c93farmvixl MacroEmissionCheckScope guard(this); 1474c68cb64496485710cdb5b8480f8fee287058c93farmvixl 14755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (vd.Is1D() || vd.Is2D()) { 14765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Fmov(vd, static_cast<double>(imm)); 1477b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl return; 1478b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl } 1479b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 14805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(vd.Is1S() || vd.Is2S() || vd.Is4S()); 1481b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl if (IsImmFP32(imm)) { 14825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl fmov(vd, imm); 1483b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl } else { 148488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois uint32_t rawbits = FloatToRawbits(imm); 14855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (vd.IsScalar()) { 14865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (rawbits == 0) { 14875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl fmov(vd, wzr); 14885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 1489db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl ldr(vd, 1490db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl new Literal<float>(imm, 1491db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl &literal_pool_, 1492db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl RawLiteral::kDeletedOnPlacementByPool)); 14935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 14945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 14955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // TODO: consider NEON support for load literal. 14965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Movi(vd, rawbits); 14975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 1498b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl } 1499b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl} 1500b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 1501b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 15020f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixlvoid MacroAssembler::Neg(const Register& rd, const Operand& operand) { 1503b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT(allow_macro_instructions_); 1504ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl if (operand.IsImmediate()) { 150588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois Mov(rd, -operand.GetImmediate()); 1506ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } else { 1507f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl Sub(rd, AppropriateZeroRegFor(rd), operand); 1508ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 1509ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl} 1510ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 1511ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 15120f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixlvoid MacroAssembler::Negs(const Register& rd, const Operand& operand) { 1513b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT(allow_macro_instructions_); 1514f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl Subs(rd, AppropriateZeroRegFor(rd), operand); 1515f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl} 1516f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl 1517f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl 15184a102baf640077d6794c0b33bb976f94b86c532barmvixlbool MacroAssembler::TryOneInstrMoveImmediate(const Register& dst, 15194a102baf640077d6794c0b33bb976f94b86c532barmvixl int64_t imm) { 1520330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl return OneInstrMoveImmediateHelper(this, dst, imm); 15214a102baf640077d6794c0b33bb976f94b86c532barmvixl} 15224a102baf640077d6794c0b33bb976f94b86c532barmvixl 15234a102baf640077d6794c0b33bb976f94b86c532barmvixl 15244a102baf640077d6794c0b33bb976f94b86c532barmvixlOperand MacroAssembler::MoveImmediateForShiftedOp(const Register& dst, 15254a102baf640077d6794c0b33bb976f94b86c532barmvixl int64_t imm) { 152688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int reg_size = dst.GetSizeInBits(); 15274a102baf640077d6794c0b33bb976f94b86c532barmvixl 15284a102baf640077d6794c0b33bb976f94b86c532barmvixl // Encode the immediate in a single move instruction, if possible. 15294a102baf640077d6794c0b33bb976f94b86c532barmvixl if (TryOneInstrMoveImmediate(dst, imm)) { 15304a102baf640077d6794c0b33bb976f94b86c532barmvixl // The move was successful; nothing to do here. 15314a102baf640077d6794c0b33bb976f94b86c532barmvixl } else { 15324a102baf640077d6794c0b33bb976f94b86c532barmvixl // Pre-shift the immediate to the least-significant bits of the register. 15334a102baf640077d6794c0b33bb976f94b86c532barmvixl int shift_low = CountTrailingZeros(imm, reg_size); 15344a102baf640077d6794c0b33bb976f94b86c532barmvixl int64_t imm_low = imm >> shift_low; 15354a102baf640077d6794c0b33bb976f94b86c532barmvixl 15364a102baf640077d6794c0b33bb976f94b86c532barmvixl // Pre-shift the immediate to the most-significant bits of the register, 15374a102baf640077d6794c0b33bb976f94b86c532barmvixl // inserting set bits in the least-significant bits. 15384a102baf640077d6794c0b33bb976f94b86c532barmvixl int shift_high = CountLeadingZeros(imm, reg_size); 15395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int64_t imm_high = (imm << shift_high) | ((INT64_C(1) << shift_high) - 1); 15404a102baf640077d6794c0b33bb976f94b86c532barmvixl 15414a102baf640077d6794c0b33bb976f94b86c532barmvixl if (TryOneInstrMoveImmediate(dst, imm_low)) { 15424a102baf640077d6794c0b33bb976f94b86c532barmvixl // The new immediate has been moved into the destination's low bits: 15434a102baf640077d6794c0b33bb976f94b86c532barmvixl // return a new leftward-shifting operand. 15444a102baf640077d6794c0b33bb976f94b86c532barmvixl return Operand(dst, LSL, shift_low); 15454a102baf640077d6794c0b33bb976f94b86c532barmvixl } else if (TryOneInstrMoveImmediate(dst, imm_high)) { 15464a102baf640077d6794c0b33bb976f94b86c532barmvixl // The new immediate has been moved into the destination's high bits: 15474a102baf640077d6794c0b33bb976f94b86c532barmvixl // return a new rightward-shifting operand. 15484a102baf640077d6794c0b33bb976f94b86c532barmvixl return Operand(dst, LSR, shift_high); 15494a102baf640077d6794c0b33bb976f94b86c532barmvixl } else { 15504a102baf640077d6794c0b33bb976f94b86c532barmvixl Mov(dst, imm); 15514a102baf640077d6794c0b33bb976f94b86c532barmvixl } 15524a102baf640077d6794c0b33bb976f94b86c532barmvixl } 15534a102baf640077d6794c0b33bb976f94b86c532barmvixl return Operand(dst); 15544a102baf640077d6794c0b33bb976f94b86c532barmvixl} 15554a102baf640077d6794c0b33bb976f94b86c532barmvixl 15564a102baf640077d6794c0b33bb976f94b86c532barmvixl 15574e7c93cc256c7719d69279d64e4f5d09044b8b2cAlexandre Ramesvoid MacroAssembler::Move(const GenericOperand& dst, 15584e7c93cc256c7719d69279d64e4f5d09044b8b2cAlexandre Rames const GenericOperand& src) { 15594e7c93cc256c7719d69279d64e4f5d09044b8b2cAlexandre Rames if (dst.Equals(src)) { 15604e7c93cc256c7719d69279d64e4f5d09044b8b2cAlexandre Rames return; 15614e7c93cc256c7719d69279d64e4f5d09044b8b2cAlexandre Rames } 15624e7c93cc256c7719d69279d64e4f5d09044b8b2cAlexandre Rames 15634e7c93cc256c7719d69279d64e4f5d09044b8b2cAlexandre Rames VIXL_ASSERT(dst.IsValid() && src.IsValid()); 15644e7c93cc256c7719d69279d64e4f5d09044b8b2cAlexandre Rames 15654e7c93cc256c7719d69279d64e4f5d09044b8b2cAlexandre Rames // The sizes of the operands must match exactly. 15664e7c93cc256c7719d69279d64e4f5d09044b8b2cAlexandre Rames VIXL_ASSERT(dst.GetSizeInBits() == src.GetSizeInBits()); 1567f5348cedd702124c90fc75e75d0195e2e485c620Pierre Langlois VIXL_ASSERT(dst.GetSizeInBits() <= kXRegSize); 1568f5348cedd702124c90fc75e75d0195e2e485c620Pierre Langlois int operand_size = static_cast<int>(dst.GetSizeInBits()); 15694e7c93cc256c7719d69279d64e4f5d09044b8b2cAlexandre Rames 15704e7c93cc256c7719d69279d64e4f5d09044b8b2cAlexandre Rames if (dst.IsCPURegister() && src.IsCPURegister()) { 15714e7c93cc256c7719d69279d64e4f5d09044b8b2cAlexandre Rames CPURegister dst_reg = dst.GetCPURegister(); 15724e7c93cc256c7719d69279d64e4f5d09044b8b2cAlexandre Rames CPURegister src_reg = src.GetCPURegister(); 15734e7c93cc256c7719d69279d64e4f5d09044b8b2cAlexandre Rames if (dst_reg.IsRegister() && src_reg.IsRegister()) { 15744e7c93cc256c7719d69279d64e4f5d09044b8b2cAlexandre Rames Mov(Register(dst_reg), Register(src_reg)); 15754e7c93cc256c7719d69279d64e4f5d09044b8b2cAlexandre Rames } else if (dst_reg.IsVRegister() && src_reg.IsVRegister()) { 15764e7c93cc256c7719d69279d64e4f5d09044b8b2cAlexandre Rames Fmov(VRegister(dst_reg), VRegister(src_reg)); 15774e7c93cc256c7719d69279d64e4f5d09044b8b2cAlexandre Rames } else { 15784e7c93cc256c7719d69279d64e4f5d09044b8b2cAlexandre Rames if (dst_reg.IsRegister()) { 15794e7c93cc256c7719d69279d64e4f5d09044b8b2cAlexandre Rames Fmov(Register(dst_reg), VRegister(src_reg)); 15804e7c93cc256c7719d69279d64e4f5d09044b8b2cAlexandre Rames } else { 15814e7c93cc256c7719d69279d64e4f5d09044b8b2cAlexandre Rames Fmov(VRegister(dst_reg), Register(src_reg)); 15824e7c93cc256c7719d69279d64e4f5d09044b8b2cAlexandre Rames } 15834e7c93cc256c7719d69279d64e4f5d09044b8b2cAlexandre Rames } 15844e7c93cc256c7719d69279d64e4f5d09044b8b2cAlexandre Rames return; 15854e7c93cc256c7719d69279d64e4f5d09044b8b2cAlexandre Rames } 15864e7c93cc256c7719d69279d64e4f5d09044b8b2cAlexandre Rames 15874e7c93cc256c7719d69279d64e4f5d09044b8b2cAlexandre Rames if (dst.IsMemOperand() && src.IsMemOperand()) { 15884e7c93cc256c7719d69279d64e4f5d09044b8b2cAlexandre Rames UseScratchRegisterScope temps(this); 15894e7c93cc256c7719d69279d64e4f5d09044b8b2cAlexandre Rames CPURegister temp = temps.AcquireCPURegisterOfSize(operand_size); 15904e7c93cc256c7719d69279d64e4f5d09044b8b2cAlexandre Rames Ldr(temp, src.GetMemOperand()); 15914e7c93cc256c7719d69279d64e4f5d09044b8b2cAlexandre Rames Str(temp, dst.GetMemOperand()); 15924e7c93cc256c7719d69279d64e4f5d09044b8b2cAlexandre Rames return; 15934e7c93cc256c7719d69279d64e4f5d09044b8b2cAlexandre Rames } 15944e7c93cc256c7719d69279d64e4f5d09044b8b2cAlexandre Rames 15954e7c93cc256c7719d69279d64e4f5d09044b8b2cAlexandre Rames if (dst.IsCPURegister()) { 15964e7c93cc256c7719d69279d64e4f5d09044b8b2cAlexandre Rames Ldr(dst.GetCPURegister(), src.GetMemOperand()); 15974e7c93cc256c7719d69279d64e4f5d09044b8b2cAlexandre Rames } else { 15984e7c93cc256c7719d69279d64e4f5d09044b8b2cAlexandre Rames Str(src.GetCPURegister(), dst.GetMemOperand()); 15994e7c93cc256c7719d69279d64e4f5d09044b8b2cAlexandre Rames } 16004e7c93cc256c7719d69279d64e4f5d09044b8b2cAlexandre Rames} 16014e7c93cc256c7719d69279d64e4f5d09044b8b2cAlexandre Rames 16024e7c93cc256c7719d69279d64e4f5d09044b8b2cAlexandre Rames 16035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlvoid MacroAssembler::ComputeAddress(const Register& dst, 16045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const MemOperand& mem_op) { 16055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // We cannot handle pre-indexing or post-indexing. 160688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_ASSERT(mem_op.GetAddrMode() == Offset); 160788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois Register base = mem_op.GetBaseRegister(); 16085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (mem_op.IsImmediateOffset()) { 160988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois Add(dst, base, mem_op.GetOffset()); 16105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 16115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(mem_op.IsRegisterOffset()); 161288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois Register reg_offset = mem_op.GetRegisterOffset(); 161388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois Shift shift = mem_op.GetShift(); 161488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois Extend extend = mem_op.GetExtend(); 16155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (shift == NO_SHIFT) { 16165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(extend != NO_EXTEND); 161788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois Add(dst, base, Operand(reg_offset, extend, mem_op.GetShiftAmount())); 16185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 16195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(extend == NO_EXTEND); 162088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois Add(dst, base, Operand(reg_offset, shift, mem_op.GetShiftAmount())); 16215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 16225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 16235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 16245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 16255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 1626ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlvoid MacroAssembler::AddSubMacro(const Register& rd, 1627ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl const Register& rn, 1628ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl const Operand& operand, 1629ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FlagsUpdate S, 1630ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl AddSubOp op) { 1631c68cb64496485710cdb5b8480f8fee287058c93farmvixl // Worst case is add/sub immediate: 1632c68cb64496485710cdb5b8480f8fee287058c93farmvixl // * up to 4 instructions to materialise the constant 1633c68cb64496485710cdb5b8480f8fee287058c93farmvixl // * 1 instruction for add/sub 1634c68cb64496485710cdb5b8480f8fee287058c93farmvixl MacroEmissionCheckScope guard(this); 1635c68cb64496485710cdb5b8480f8fee287058c93farmvixl 1636f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl if (operand.IsZero() && rd.Is(rn) && rd.Is64Bits() && rn.Is64Bits() && 1637f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl (S == LeaveFlags)) { 1638f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl // The instruction would be a nop. Avoid generating useless code. 1639f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl return; 1640f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl } 1641f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl 164288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois if ((operand.IsImmediate() && !IsImmAddSub(operand.GetImmediate())) || 16430f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl (rn.IsZero() && !operand.IsShiftedRegister()) || 164488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois (operand.IsShiftedRegister() && (operand.GetShift() == ROR))) { 1645b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl UseScratchRegisterScope temps(this); 1646b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl Register temp = temps.AcquireSameSizeAs(rn); 16474a102baf640077d6794c0b33bb976f94b86c532barmvixl if (operand.IsImmediate()) { 16484a102baf640077d6794c0b33bb976f94b86c532barmvixl Operand imm_operand = 164988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois MoveImmediateForShiftedOp(temp, operand.GetImmediate()); 16504a102baf640077d6794c0b33bb976f94b86c532barmvixl AddSub(rd, rn, imm_operand, S, op); 16514a102baf640077d6794c0b33bb976f94b86c532barmvixl } else { 16524a102baf640077d6794c0b33bb976f94b86c532barmvixl Mov(temp, operand); 16534a102baf640077d6794c0b33bb976f94b86c532barmvixl AddSub(rd, rn, temp, S, op); 16544a102baf640077d6794c0b33bb976f94b86c532barmvixl } 1655ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } else { 1656ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl AddSub(rd, rn, operand, S, op); 1657ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 1658ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl} 1659ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 1660ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 1661ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlvoid MacroAssembler::Adc(const Register& rd, 1662ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl const Register& rn, 1663f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl const Operand& operand) { 1664b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT(allow_macro_instructions_); 1665f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl AddSubWithCarryMacro(rd, rn, operand, LeaveFlags, ADC); 1666f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl} 1667f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl 1668f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl 1669f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixlvoid MacroAssembler::Adcs(const Register& rd, 1670f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl const Register& rn, 1671f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl const Operand& operand) { 1672b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT(allow_macro_instructions_); 1673f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl AddSubWithCarryMacro(rd, rn, operand, SetFlags, ADC); 1674ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl} 1675ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 1676ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 1677ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlvoid MacroAssembler::Sbc(const Register& rd, 1678ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl const Register& rn, 1679f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl const Operand& operand) { 1680b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT(allow_macro_instructions_); 1681f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl AddSubWithCarryMacro(rd, rn, operand, LeaveFlags, SBC); 1682f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl} 1683f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl 1684f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl 1685f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixlvoid MacroAssembler::Sbcs(const Register& rd, 1686f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl const Register& rn, 1687f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl const Operand& operand) { 1688b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT(allow_macro_instructions_); 1689f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl AddSubWithCarryMacro(rd, rn, operand, SetFlags, SBC); 1690ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl} 1691ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 1692ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 16930f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixlvoid MacroAssembler::Ngc(const Register& rd, const Operand& operand) { 1694b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT(allow_macro_instructions_); 1695ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl Register zr = AppropriateZeroRegFor(rd); 1696f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl Sbc(rd, zr, operand); 1697f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl} 1698f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl 1699f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl 17000f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixlvoid MacroAssembler::Ngcs(const Register& rd, const Operand& operand) { 1701b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT(allow_macro_instructions_); 1702f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl Register zr = AppropriateZeroRegFor(rd); 1703f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl Sbcs(rd, zr, operand); 1704ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl} 1705ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 1706ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 1707ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlvoid MacroAssembler::AddSubWithCarryMacro(const Register& rd, 1708ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl const Register& rn, 1709ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl const Operand& operand, 1710ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FlagsUpdate S, 1711ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl AddSubWithCarryOp op) { 171288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_ASSERT(rd.GetSizeInBits() == rn.GetSizeInBits()); 1713c68cb64496485710cdb5b8480f8fee287058c93farmvixl // Worst case is addc/subc immediate: 1714c68cb64496485710cdb5b8480f8fee287058c93farmvixl // * up to 4 instructions to materialise the constant 1715c68cb64496485710cdb5b8480f8fee287058c93farmvixl // * 1 instruction for add/sub 1716c68cb64496485710cdb5b8480f8fee287058c93farmvixl MacroEmissionCheckScope guard(this); 1717b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl UseScratchRegisterScope temps(this); 1718ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 1719ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl if (operand.IsImmediate() || 172088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois (operand.IsShiftedRegister() && (operand.GetShift() == ROR))) { 1721ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // Add/sub with carry (immediate or ROR shifted register.) 1722b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl Register temp = temps.AcquireSameSizeAs(rn); 1723ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl Mov(temp, operand); 1724ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl AddSubWithCarry(rd, rn, Operand(temp), S, op); 172588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } else if (operand.IsShiftedRegister() && (operand.GetShiftAmount() != 0)) { 1726ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // Add/sub with carry (shifted register). 172788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_ASSERT(operand.GetRegister().GetSizeInBits() == rd.GetSizeInBits()); 172888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_ASSERT(operand.GetShift() != ROR); 172988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_ASSERT( 173088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois IsUintN(rd.GetSizeInBits() == kXRegSize ? kXRegSizeLog2 : kWRegSizeLog2, 173188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois operand.GetShiftAmount())); 173288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois temps.Exclude(operand.GetRegister()); 1733b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl Register temp = temps.AcquireSameSizeAs(rn); 173488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois EmitShift(temp, 173588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois operand.GetRegister(), 173688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois operand.GetShift(), 173788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois operand.GetShiftAmount()); 1738ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl AddSubWithCarry(rd, rn, Operand(temp), S, op); 1739ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } else if (operand.IsExtendedRegister()) { 1740ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // Add/sub with carry (extended register). 174188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_ASSERT(operand.GetRegister().GetSizeInBits() <= rd.GetSizeInBits()); 1742ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // Add/sub extended supports a shift <= 4. We want to support exactly the 1743ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // same modes. 174488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_ASSERT(operand.GetShiftAmount() <= 4); 174588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_ASSERT( 174688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois operand.GetRegister().Is64Bits() || 174788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois ((operand.GetExtend() != UXTX) && (operand.GetExtend() != SXTX))); 174888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois temps.Exclude(operand.GetRegister()); 1749b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl Register temp = temps.AcquireSameSizeAs(rn); 17500f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl EmitExtendShift(temp, 175188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois operand.GetRegister(), 175288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois operand.GetExtend(), 175388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois operand.GetShiftAmount()); 1754ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl AddSubWithCarry(rd, rn, Operand(temp), S, op); 1755ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } else { 1756ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // The addressing mode is directly supported by the instruction. 1757ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl AddSubWithCarry(rd, rn, operand, S, op); 1758ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 1759ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl} 1760ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 1761ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 17620f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl#define DEFINE_FUNCTION(FN, REGTYPE, REG, OP) \ 17630f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl void MacroAssembler::FN(const REGTYPE REG, const MemOperand& addr) { \ 17640f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl VIXL_ASSERT(allow_macro_instructions_); \ 17650f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LoadStoreMacro(REG, addr, OP); \ 17660f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl } 1767ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlLS_MACRO_LIST(DEFINE_FUNCTION) 1768ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl#undef DEFINE_FUNCTION 1769ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 1770330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl 1771ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlvoid MacroAssembler::LoadStoreMacro(const CPURegister& rt, 1772ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl const MemOperand& addr, 1773ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LoadStoreOp op) { 1774c68cb64496485710cdb5b8480f8fee287058c93farmvixl // Worst case is ldr/str pre/post index: 1775c68cb64496485710cdb5b8480f8fee287058c93farmvixl // * 1 instruction for ldr/str 1776c68cb64496485710cdb5b8480f8fee287058c93farmvixl // * up to 4 instructions to materialise the constant 1777c68cb64496485710cdb5b8480f8fee287058c93farmvixl // * 1 instruction to update the base 1778c68cb64496485710cdb5b8480f8fee287058c93farmvixl MacroEmissionCheckScope guard(this); 1779c68cb64496485710cdb5b8480f8fee287058c93farmvixl 178088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int64_t offset = addr.GetOffset(); 17815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl unsigned access_size = CalcLSDataSize(op); 1782ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 1783ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // Check if an immediate offset fits in the immediate field of the 1784ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // appropriate instruction. If not, emit two instructions to perform 1785ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // the operation. 17865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (addr.IsImmediateOffset() && !IsImmLSScaled(offset, access_size) && 1787ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl !IsImmLSUnscaled(offset)) { 1788ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // Immediate offset that can't be encoded using unsigned or unscaled 1789ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // addressing modes. 1790b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl UseScratchRegisterScope temps(this); 179188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois Register temp = temps.AcquireSameSizeAs(addr.GetBaseRegister()); 179288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois Mov(temp, addr.GetOffset()); 179388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois LoadStore(rt, MemOperand(addr.GetBaseRegister(), temp), op); 1794ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } else if (addr.IsPostIndex() && !IsImmLSUnscaled(offset)) { 1795ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // Post-index beyond unscaled addressing range. 179688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois LoadStore(rt, MemOperand(addr.GetBaseRegister()), op); 179788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois Add(addr.GetBaseRegister(), addr.GetBaseRegister(), Operand(offset)); 1798ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } else if (addr.IsPreIndex() && !IsImmLSUnscaled(offset)) { 1799ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // Pre-index beyond unscaled addressing range. 180088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois Add(addr.GetBaseRegister(), addr.GetBaseRegister(), Operand(offset)); 180188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois LoadStore(rt, MemOperand(addr.GetBaseRegister()), op); 1802ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } else { 1803ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // Encodable in one load/store instruction. 1804ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl LoadStore(rt, addr, op); 1805ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 1806ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl} 1807ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 1808ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 18090f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl#define DEFINE_FUNCTION(FN, REGTYPE, REG, REG2, OP) \ 18100f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl void MacroAssembler::FN(const REGTYPE REG, \ 18110f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const REGTYPE REG2, \ 18120f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const MemOperand& addr) { \ 18130f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl VIXL_ASSERT(allow_macro_instructions_); \ 18140f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LoadStorePairMacro(REG, REG2, addr, OP); \ 18150f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl } 1816c68cb64496485710cdb5b8480f8fee287058c93farmvixlLSPAIR_MACRO_LIST(DEFINE_FUNCTION) 1817c68cb64496485710cdb5b8480f8fee287058c93farmvixl#undef DEFINE_FUNCTION 1818c68cb64496485710cdb5b8480f8fee287058c93farmvixl 1819c68cb64496485710cdb5b8480f8fee287058c93farmvixlvoid MacroAssembler::LoadStorePairMacro(const CPURegister& rt, 1820c68cb64496485710cdb5b8480f8fee287058c93farmvixl const CPURegister& rt2, 1821c68cb64496485710cdb5b8480f8fee287058c93farmvixl const MemOperand& addr, 1822c68cb64496485710cdb5b8480f8fee287058c93farmvixl LoadStorePairOp op) { 1823c68cb64496485710cdb5b8480f8fee287058c93farmvixl // TODO(all): Should we support register offset for load-store-pair? 1824c68cb64496485710cdb5b8480f8fee287058c93farmvixl VIXL_ASSERT(!addr.IsRegisterOffset()); 1825c68cb64496485710cdb5b8480f8fee287058c93farmvixl // Worst case is ldp/stp immediate: 1826c68cb64496485710cdb5b8480f8fee287058c93farmvixl // * 1 instruction for ldp/stp 1827c68cb64496485710cdb5b8480f8fee287058c93farmvixl // * up to 4 instructions to materialise the constant 1828c68cb64496485710cdb5b8480f8fee287058c93farmvixl // * 1 instruction to update the base 1829c68cb64496485710cdb5b8480f8fee287058c93farmvixl MacroEmissionCheckScope guard(this); 1830c68cb64496485710cdb5b8480f8fee287058c93farmvixl 183188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int64_t offset = addr.GetOffset(); 18325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl unsigned access_size = CalcLSPairDataSize(op); 1833c68cb64496485710cdb5b8480f8fee287058c93farmvixl 1834c68cb64496485710cdb5b8480f8fee287058c93farmvixl // Check if the offset fits in the immediate field of the appropriate 1835c68cb64496485710cdb5b8480f8fee287058c93farmvixl // instruction. If not, emit two instructions to perform the operation. 18365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (IsImmLSPair(offset, access_size)) { 1837c68cb64496485710cdb5b8480f8fee287058c93farmvixl // Encodable in one load/store pair instruction. 1838c68cb64496485710cdb5b8480f8fee287058c93farmvixl LoadStorePair(rt, rt2, addr, op); 1839c68cb64496485710cdb5b8480f8fee287058c93farmvixl } else { 184088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois Register base = addr.GetBaseRegister(); 1841c68cb64496485710cdb5b8480f8fee287058c93farmvixl if (addr.IsImmediateOffset()) { 1842c68cb64496485710cdb5b8480f8fee287058c93farmvixl UseScratchRegisterScope temps(this); 1843c68cb64496485710cdb5b8480f8fee287058c93farmvixl Register temp = temps.AcquireSameSizeAs(base); 1844c68cb64496485710cdb5b8480f8fee287058c93farmvixl Add(temp, base, offset); 1845c68cb64496485710cdb5b8480f8fee287058c93farmvixl LoadStorePair(rt, rt2, MemOperand(temp), op); 1846c68cb64496485710cdb5b8480f8fee287058c93farmvixl } else if (addr.IsPostIndex()) { 1847c68cb64496485710cdb5b8480f8fee287058c93farmvixl LoadStorePair(rt, rt2, MemOperand(base), op); 1848c68cb64496485710cdb5b8480f8fee287058c93farmvixl Add(base, base, offset); 1849c68cb64496485710cdb5b8480f8fee287058c93farmvixl } else { 1850c68cb64496485710cdb5b8480f8fee287058c93farmvixl VIXL_ASSERT(addr.IsPreIndex()); 1851c68cb64496485710cdb5b8480f8fee287058c93farmvixl Add(base, base, offset); 1852c68cb64496485710cdb5b8480f8fee287058c93farmvixl LoadStorePair(rt, rt2, MemOperand(base), op); 1853c68cb64496485710cdb5b8480f8fee287058c93farmvixl } 1854c68cb64496485710cdb5b8480f8fee287058c93farmvixl } 1855c68cb64496485710cdb5b8480f8fee287058c93farmvixl} 1856c68cb64496485710cdb5b8480f8fee287058c93farmvixl 1857330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl 1858330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixlvoid MacroAssembler::Prfm(PrefetchOperation op, const MemOperand& addr) { 1859330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl MacroEmissionCheckScope guard(this); 1860330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl 1861330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl // There are no pre- or post-index modes for prfm. 1862330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl VIXL_ASSERT(addr.IsImmediateOffset() || addr.IsRegisterOffset()); 1863330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl 1864330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl // The access size is implicitly 8 bytes for all prefetch operations. 18655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl unsigned size = kXRegSizeInBytesLog2; 1866330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl 1867330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl // Check if an immediate offset fits in the immediate field of the 1868330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl // appropriate instruction. If not, emit two instructions to perform 1869330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl // the operation. 187088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois if (addr.IsImmediateOffset() && !IsImmLSScaled(addr.GetOffset(), size) && 187188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois !IsImmLSUnscaled(addr.GetOffset())) { 1872330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl // Immediate offset that can't be encoded using unsigned or unscaled 1873330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl // addressing modes. 1874330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl UseScratchRegisterScope temps(this); 187588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois Register temp = temps.AcquireSameSizeAs(addr.GetBaseRegister()); 187688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois Mov(temp, addr.GetOffset()); 187788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois Prefetch(op, MemOperand(addr.GetBaseRegister(), temp)); 1878330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl } else { 1879330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl // Simple register-offsets are encodable in one instruction. 1880330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl Prefetch(op, addr); 1881330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl } 1882330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl} 1883330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl 1884330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl 18850f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixlvoid MacroAssembler::Push(const CPURegister& src0, 18860f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const CPURegister& src1, 18870f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const CPURegister& src2, 18880f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const CPURegister& src3) { 1889b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT(allow_macro_instructions_); 1890b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT(AreSameSizeAndType(src0, src1, src2, src3)); 1891b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT(src0.IsValid()); 1892ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 1893ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl int count = 1 + src1.IsValid() + src2.IsValid() + src3.IsValid(); 189488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int size = src0.GetSizeInBytes(); 1895ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 1896ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl PrepareForPush(count, size); 1897ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl PushHelper(count, size, src0, src1, src2, src3); 1898ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl} 1899ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 1900ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 19010f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixlvoid MacroAssembler::Pop(const CPURegister& dst0, 19020f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const CPURegister& dst1, 19030f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const CPURegister& dst2, 19040f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const CPURegister& dst3) { 1905ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // It is not valid to pop into the same register more than once in one 1906ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // instruction, not even into the zero register. 1907b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT(allow_macro_instructions_); 1908b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT(!AreAliased(dst0, dst1, dst2, dst3)); 1909b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT(AreSameSizeAndType(dst0, dst1, dst2, dst3)); 1910b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT(dst0.IsValid()); 1911ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 1912ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl int count = 1 + dst1.IsValid() + dst2.IsValid() + dst3.IsValid(); 191388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int size = dst0.GetSizeInBytes(); 1914ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 1915ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl PrepareForPop(count, size); 1916ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl PopHelper(count, size, dst0, dst1, dst2, dst3); 1917ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl} 1918ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 1919ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 1920ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlvoid MacroAssembler::PushCPURegList(CPURegList registers) { 192188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_ASSERT(!registers.Overlaps(*GetScratchRegisterList())); 192288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_ASSERT(!registers.Overlaps(*GetScratchFPRegisterList())); 1923b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT(allow_macro_instructions_); 19246e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 192588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int reg_size = registers.GetRegisterSizeInBytes(); 192688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois PrepareForPush(registers.GetCount(), reg_size); 19276e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 19286e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // Bump the stack pointer and store two registers at the bottom. 192988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int size = registers.GetTotalSizeInBytes(); 19306e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl const CPURegister& bottom_0 = registers.PopLowestIndex(); 19316e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl const CPURegister& bottom_1 = registers.PopLowestIndex(); 19326e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if (bottom_0.IsValid() && bottom_1.IsValid()) { 19336e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl Stp(bottom_0, bottom_1, MemOperand(StackPointer(), -size, PreIndex)); 19346e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } else if (bottom_0.IsValid()) { 19356e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl Str(bottom_0, MemOperand(StackPointer(), -size, PreIndex)); 19366e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 19376e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 19386e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl int offset = 2 * reg_size; 1939ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl while (!registers.IsEmpty()) { 19406e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl const CPURegister& src0 = registers.PopLowestIndex(); 19416e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl const CPURegister& src1 = registers.PopLowestIndex(); 19426e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if (src1.IsValid()) { 19436e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl Stp(src0, src1, MemOperand(StackPointer(), offset)); 19446e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } else { 19456e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl Str(src0, MemOperand(StackPointer(), offset)); 19466e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 19476e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl offset += 2 * reg_size; 1948ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 1949ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl} 1950ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 1951ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 1952ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlvoid MacroAssembler::PopCPURegList(CPURegList registers) { 195388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_ASSERT(!registers.Overlaps(*GetScratchRegisterList())); 195488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_ASSERT(!registers.Overlaps(*GetScratchFPRegisterList())); 1955b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT(allow_macro_instructions_); 19566e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 195788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int reg_size = registers.GetRegisterSizeInBytes(); 195888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois PrepareForPop(registers.GetCount(), reg_size); 19596e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 19606e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 196188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int size = registers.GetTotalSizeInBytes(); 19626e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl const CPURegister& bottom_0 = registers.PopLowestIndex(); 19636e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl const CPURegister& bottom_1 = registers.PopLowestIndex(); 19646e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 19656e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl int offset = 2 * reg_size; 1966ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl while (!registers.IsEmpty()) { 1967ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl const CPURegister& dst0 = registers.PopLowestIndex(); 1968ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl const CPURegister& dst1 = registers.PopLowestIndex(); 19696e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if (dst1.IsValid()) { 19706e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl Ldp(dst0, dst1, MemOperand(StackPointer(), offset)); 19716e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } else { 19726e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl Ldr(dst0, MemOperand(StackPointer(), offset)); 19736e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 19746e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl offset += 2 * reg_size; 19756e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 19766e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 19776e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // Load the two registers at the bottom and drop the stack pointer. 19786e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if (bottom_0.IsValid() && bottom_1.IsValid()) { 19796e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl Ldp(bottom_0, bottom_1, MemOperand(StackPointer(), size, PostIndex)); 19806e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } else if (bottom_0.IsValid()) { 19816e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl Ldr(bottom_0, MemOperand(StackPointer(), size, PostIndex)); 1982ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 1983ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl} 1984ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 1985ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 1986ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlvoid MacroAssembler::PushMultipleTimes(int count, Register src) { 1987b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT(allow_macro_instructions_); 198888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int size = src.GetSizeInBytes(); 1989ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 1990ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl PrepareForPush(count, size); 1991ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // Push up to four registers at a time if possible because if the current 1992ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // stack pointer is sp and the register size is 32, registers must be pushed 1993ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // in blocks of four in order to maintain the 16-byte alignment for sp. 1994ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl while (count >= 4) { 1995ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl PushHelper(4, size, src, src, src, src); 1996ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl count -= 4; 1997ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 1998ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl if (count >= 2) { 1999ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl PushHelper(2, size, src, src, NoReg, NoReg); 2000ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl count -= 2; 2001ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 2002ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl if (count == 1) { 2003ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl PushHelper(1, size, src, NoReg, NoReg, NoReg); 2004ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl count -= 1; 2005ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 2006b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT(count == 0); 2007ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl} 2008ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 2009ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 20100f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixlvoid MacroAssembler::PushHelper(int count, 20110f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl int size, 2012ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl const CPURegister& src0, 2013ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl const CPURegister& src1, 2014ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl const CPURegister& src2, 2015ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl const CPURegister& src3) { 2016ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // Ensure that we don't unintentionally modify scratch or debug registers. 2017c68cb64496485710cdb5b8480f8fee287058c93farmvixl // Worst case for size is 2 stp. 201807d1aa5b941ace15deb01e5df2c79e677039c4aeAlexandre Rames ExactAssemblyScope scope(this, 201907d1aa5b941ace15deb01e5df2c79e677039c4aeAlexandre Rames 2 * kInstructionSize, 202007d1aa5b941ace15deb01e5df2c79e677039c4aeAlexandre Rames ExactAssemblyScope::kMaximumSize); 2021ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 2022b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT(AreSameSizeAndType(src0, src1, src2, src3)); 202388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_ASSERT(size == src0.GetSizeInBytes()); 2024ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 2025ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // When pushing multiple registers, the store order is chosen such that 2026ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // Push(a, b) is equivalent to Push(a) followed by Push(b). 2027ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl switch (count) { 2028ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl case 1: 2029b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT(src1.IsNone() && src2.IsNone() && src3.IsNone()); 2030ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl str(src0, MemOperand(StackPointer(), -1 * size, PreIndex)); 2031ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl break; 2032ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl case 2: 2033b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT(src2.IsNone() && src3.IsNone()); 2034ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl stp(src1, src0, MemOperand(StackPointer(), -2 * size, PreIndex)); 2035ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl break; 2036ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl case 3: 2037b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT(src3.IsNone()); 2038ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl stp(src2, src1, MemOperand(StackPointer(), -3 * size, PreIndex)); 2039ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl str(src0, MemOperand(StackPointer(), 2 * size)); 2040ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl break; 2041ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl case 4: 2042ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // Skip over 4 * size, then fill in the gap. This allows four W registers 2043ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // to be pushed using sp, whilst maintaining 16-byte alignment for sp at 2044ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // all times. 2045ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl stp(src3, src2, MemOperand(StackPointer(), -4 * size, PreIndex)); 2046ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl stp(src1, src0, MemOperand(StackPointer(), 2 * size)); 2047ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl break; 2048ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl default: 2049b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_UNREACHABLE(); 2050ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 2051ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl} 2052ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 2053ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 20540f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixlvoid MacroAssembler::PopHelper(int count, 20550f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl int size, 2056ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl const CPURegister& dst0, 2057ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl const CPURegister& dst1, 2058ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl const CPURegister& dst2, 2059ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl const CPURegister& dst3) { 2060ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // Ensure that we don't unintentionally modify scratch or debug registers. 2061c68cb64496485710cdb5b8480f8fee287058c93farmvixl // Worst case for size is 2 ldp. 206207d1aa5b941ace15deb01e5df2c79e677039c4aeAlexandre Rames ExactAssemblyScope scope(this, 206307d1aa5b941ace15deb01e5df2c79e677039c4aeAlexandre Rames 2 * kInstructionSize, 206407d1aa5b941ace15deb01e5df2c79e677039c4aeAlexandre Rames ExactAssemblyScope::kMaximumSize); 2065ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 2066b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT(AreSameSizeAndType(dst0, dst1, dst2, dst3)); 206788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_ASSERT(size == dst0.GetSizeInBytes()); 2068ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 2069ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // When popping multiple registers, the load order is chosen such that 2070ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // Pop(a, b) is equivalent to Pop(a) followed by Pop(b). 2071ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl switch (count) { 2072ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl case 1: 2073b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT(dst1.IsNone() && dst2.IsNone() && dst3.IsNone()); 2074ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl ldr(dst0, MemOperand(StackPointer(), 1 * size, PostIndex)); 2075ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl break; 2076ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl case 2: 2077b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT(dst2.IsNone() && dst3.IsNone()); 2078ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl ldp(dst0, dst1, MemOperand(StackPointer(), 2 * size, PostIndex)); 2079ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl break; 2080ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl case 3: 2081b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT(dst3.IsNone()); 2082ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl ldr(dst2, MemOperand(StackPointer(), 2 * size)); 2083ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl ldp(dst0, dst1, MemOperand(StackPointer(), 3 * size, PostIndex)); 2084ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl break; 2085ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl case 4: 2086ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // Load the higher addresses first, then load the lower addresses and skip 2087ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // the whole block in the second instruction. This allows four W registers 2088ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // to be popped using sp, whilst maintaining 16-byte alignment for sp at 2089ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // all times. 2090ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl ldp(dst2, dst3, MemOperand(StackPointer(), 2 * size)); 2091ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl ldp(dst0, dst1, MemOperand(StackPointer(), 4 * size, PostIndex)); 2092ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl break; 2093ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl default: 2094b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_UNREACHABLE(); 2095ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 2096ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl} 2097ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 2098ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 2099ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlvoid MacroAssembler::PrepareForPush(int count, int size) { 2100ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl if (sp.Is(StackPointer())) { 2101ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // If the current stack pointer is sp, then it must be aligned to 16 bytes 2102ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // on entry and the total size of the specified registers must also be a 2103ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // multiple of 16 bytes. 2104b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT((count * size) % 16 == 0); 2105ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } else { 2106ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // Even if the current stack pointer is not the system stack pointer (sp), 2107ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // the system stack pointer will still be modified in order to comply with 2108ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // ABI rules about accessing memory below the system stack pointer. 2109ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl BumpSystemStackPointer(count * size); 2110ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 2111ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl} 2112ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 2113ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 2114ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlvoid MacroAssembler::PrepareForPop(int count, int size) { 2115db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl USE(count, size); 2116ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl if (sp.Is(StackPointer())) { 2117ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // If the current stack pointer is sp, then it must be aligned to 16 bytes 2118ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // on entry and the total size of the specified registers must also be a 2119ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // multiple of 16 bytes. 2120b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT((count * size) % 16 == 0); 2121ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 2122ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl} 2123ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 2124ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlvoid MacroAssembler::Poke(const Register& src, const Operand& offset) { 2125b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT(allow_macro_instructions_); 2126ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl if (offset.IsImmediate()) { 212788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_ASSERT(offset.GetImmediate() >= 0); 2128ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 2129ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 2130ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl Str(src, MemOperand(StackPointer(), offset)); 2131ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl} 2132ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 2133ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 2134ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlvoid MacroAssembler::Peek(const Register& dst, const Operand& offset) { 2135b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT(allow_macro_instructions_); 2136ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl if (offset.IsImmediate()) { 213788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_ASSERT(offset.GetImmediate() >= 0); 2138ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 2139ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 2140ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl Ldr(dst, MemOperand(StackPointer(), offset)); 2141ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl} 2142ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 2143ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 2144ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlvoid MacroAssembler::Claim(const Operand& size) { 2145b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT(allow_macro_instructions_); 2146f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl 2147f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl if (size.IsZero()) { 2148f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl return; 2149f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl } 2150f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl 2151ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl if (size.IsImmediate()) { 215288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_ASSERT(size.GetImmediate() > 0); 2153ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl if (sp.Is(StackPointer())) { 215488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_ASSERT((size.GetImmediate() % 16) == 0); 2155ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 2156ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 2157ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 2158ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl if (!sp.Is(StackPointer())) { 2159ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl BumpSystemStackPointer(size); 2160ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 2161ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 2162ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl Sub(StackPointer(), StackPointer(), size); 2163ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl} 2164ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 2165ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 2166ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlvoid MacroAssembler::Drop(const Operand& size) { 2167b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT(allow_macro_instructions_); 2168f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl 2169f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl if (size.IsZero()) { 2170f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl return; 2171f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl } 2172f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl 2173ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl if (size.IsImmediate()) { 217488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_ASSERT(size.GetImmediate() > 0); 2175ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl if (sp.Is(StackPointer())) { 217688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_ASSERT((size.GetImmediate() % 16) == 0); 2177ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 2178ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 2179ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 2180ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl Add(StackPointer(), StackPointer(), size); 2181ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl} 2182ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 2183ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 2184ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlvoid MacroAssembler::PushCalleeSavedRegisters() { 2185ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // Ensure that the macro-assembler doesn't use any scratch registers. 2186c68cb64496485710cdb5b8480f8fee287058c93farmvixl // 10 stp will be emitted. 2187c68cb64496485710cdb5b8480f8fee287058c93farmvixl // TODO(all): Should we use GetCalleeSaved and SavedFP. 218807d1aa5b941ace15deb01e5df2c79e677039c4aeAlexandre Rames ExactAssemblyScope scope(this, 10 * kInstructionSize); 2189ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 2190ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // This method must not be called unless the current stack pointer is sp. 2191b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT(sp.Is(StackPointer())); 2192ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 2193db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl MemOperand tos(sp, -2 * static_cast<int>(kXRegSizeInBytes), PreIndex); 2194ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 2195ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl stp(x29, x30, tos); 2196ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl stp(x27, x28, tos); 2197ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl stp(x25, x26, tos); 2198ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl stp(x23, x24, tos); 2199ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl stp(x21, x22, tos); 2200ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl stp(x19, x20, tos); 22015799d6c5d10729eaade85ad608109c83ed1ae63barmvixl 22025799d6c5d10729eaade85ad608109c83ed1ae63barmvixl stp(d14, d15, tos); 22035799d6c5d10729eaade85ad608109c83ed1ae63barmvixl stp(d12, d13, tos); 22045799d6c5d10729eaade85ad608109c83ed1ae63barmvixl stp(d10, d11, tos); 22055799d6c5d10729eaade85ad608109c83ed1ae63barmvixl stp(d8, d9, tos); 2206ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl} 2207ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 2208ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 2209ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlvoid MacroAssembler::PopCalleeSavedRegisters() { 2210ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // Ensure that the macro-assembler doesn't use any scratch registers. 2211c68cb64496485710cdb5b8480f8fee287058c93farmvixl // 10 ldp will be emitted. 2212c68cb64496485710cdb5b8480f8fee287058c93farmvixl // TODO(all): Should we use GetCalleeSaved and SavedFP. 221307d1aa5b941ace15deb01e5df2c79e677039c4aeAlexandre Rames ExactAssemblyScope scope(this, 10 * kInstructionSize); 2214ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 2215ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // This method must not be called unless the current stack pointer is sp. 2216b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT(sp.Is(StackPointer())); 2217ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 2218ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl MemOperand tos(sp, 2 * kXRegSizeInBytes, PostIndex); 2219ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 22205799d6c5d10729eaade85ad608109c83ed1ae63barmvixl ldp(d8, d9, tos); 22215799d6c5d10729eaade85ad608109c83ed1ae63barmvixl ldp(d10, d11, tos); 22225799d6c5d10729eaade85ad608109c83ed1ae63barmvixl ldp(d12, d13, tos); 22235799d6c5d10729eaade85ad608109c83ed1ae63barmvixl ldp(d14, d15, tos); 22245799d6c5d10729eaade85ad608109c83ed1ae63barmvixl 2225ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl ldp(x19, x20, tos); 2226ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl ldp(x21, x22, tos); 2227ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl ldp(x23, x24, tos); 2228ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl ldp(x25, x26, tos); 2229ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl ldp(x27, x28, tos); 2230ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl ldp(x29, x30, tos); 2231ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl} 2232ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 22336e2c8275d5f34a531fe1eef7a7aa877601be8558armvixlvoid MacroAssembler::LoadCPURegList(CPURegList registers, 22346e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl const MemOperand& src) { 22356e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl LoadStoreCPURegListHelper(kLoad, registers, src); 22366e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl} 22376e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 22386e2c8275d5f34a531fe1eef7a7aa877601be8558armvixlvoid MacroAssembler::StoreCPURegList(CPURegList registers, 22396e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl const MemOperand& dst) { 22406e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl LoadStoreCPURegListHelper(kStore, registers, dst); 22416e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl} 22426e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 22436e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 22446e2c8275d5f34a531fe1eef7a7aa877601be8558armvixlvoid MacroAssembler::LoadStoreCPURegListHelper(LoadStoreCPURegListAction op, 22456e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl CPURegList registers, 22466e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl const MemOperand& mem) { 22476e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // We do not handle pre-indexing or post-indexing. 22486e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl VIXL_ASSERT(!(mem.IsPreIndex() || mem.IsPostIndex())); 22496e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl VIXL_ASSERT(!registers.Overlaps(tmp_list_)); 22506e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl VIXL_ASSERT(!registers.Overlaps(fptmp_list_)); 22516e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl VIXL_ASSERT(!registers.IncludesAliasOf(sp)); 22526e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 22536e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl UseScratchRegisterScope temps(this); 22546e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 22550f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl MemOperand loc = BaseMemOperandForLoadStoreCPURegList(registers, mem, &temps); 22566a46bf3b4e9ec6010133ee160dffa66f5dd4027aAnton Kirilov const int reg_size = registers.GetRegisterSizeInBytes(); 22576e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 22586a46bf3b4e9ec6010133ee160dffa66f5dd4027aAnton Kirilov VIXL_ASSERT(IsPowerOf2(reg_size)); 22596a46bf3b4e9ec6010133ee160dffa66f5dd4027aAnton Kirilov 22606a46bf3b4e9ec6010133ee160dffa66f5dd4027aAnton Kirilov // Since we are operating on register pairs, we would like to align on double 22616a46bf3b4e9ec6010133ee160dffa66f5dd4027aAnton Kirilov // the standard size; on the other hand, we don't want to insert an extra 22626a46bf3b4e9ec6010133ee160dffa66f5dd4027aAnton Kirilov // operation, which will happen if the number of registers is even. Note that 22636a46bf3b4e9ec6010133ee160dffa66f5dd4027aAnton Kirilov // the alignment of the base pointer is unknown here, but we assume that it 22646a46bf3b4e9ec6010133ee160dffa66f5dd4027aAnton Kirilov // is more likely to be aligned. 22656a46bf3b4e9ec6010133ee160dffa66f5dd4027aAnton Kirilov if (((loc.GetOffset() & (2 * reg_size - 1)) != 0) && 22666a46bf3b4e9ec6010133ee160dffa66f5dd4027aAnton Kirilov ((registers.GetCount() % 2) != 0)) { 22676a46bf3b4e9ec6010133ee160dffa66f5dd4027aAnton Kirilov if (op == kStore) { 22686a46bf3b4e9ec6010133ee160dffa66f5dd4027aAnton Kirilov Str(registers.PopLowestIndex(), loc); 22696a46bf3b4e9ec6010133ee160dffa66f5dd4027aAnton Kirilov } else { 22706a46bf3b4e9ec6010133ee160dffa66f5dd4027aAnton Kirilov VIXL_ASSERT(op == kLoad); 22716a46bf3b4e9ec6010133ee160dffa66f5dd4027aAnton Kirilov Ldr(registers.PopLowestIndex(), loc); 22726a46bf3b4e9ec6010133ee160dffa66f5dd4027aAnton Kirilov } 22736a46bf3b4e9ec6010133ee160dffa66f5dd4027aAnton Kirilov loc.AddOffset(reg_size); 22746a46bf3b4e9ec6010133ee160dffa66f5dd4027aAnton Kirilov } 227588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois while (registers.GetCount() >= 2) { 22766e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl const CPURegister& dst0 = registers.PopLowestIndex(); 22776e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl const CPURegister& dst1 = registers.PopLowestIndex(); 22786e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if (op == kStore) { 22796e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl Stp(dst0, dst1, loc); 22806e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } else { 22816e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl VIXL_ASSERT(op == kLoad); 22826e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl Ldp(dst0, dst1, loc); 22836e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 22846a46bf3b4e9ec6010133ee160dffa66f5dd4027aAnton Kirilov loc.AddOffset(2 * reg_size); 22856e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 22866e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if (!registers.IsEmpty()) { 22876e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if (op == kStore) { 22886e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl Str(registers.PopLowestIndex(), loc); 22896e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } else { 22906e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl VIXL_ASSERT(op == kLoad); 22916e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl Ldr(registers.PopLowestIndex(), loc); 22926e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 22936e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 22946e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl} 22956e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 22966e2c8275d5f34a531fe1eef7a7aa877601be8558armvixlMemOperand MacroAssembler::BaseMemOperandForLoadStoreCPURegList( 22976e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl const CPURegList& registers, 22986e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl const MemOperand& mem, 22996e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl UseScratchRegisterScope* scratch_scope) { 23006e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // If necessary, pre-compute the base address for the accesses. 23016e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if (mem.IsRegisterOffset()) { 23026e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl Register reg_base = scratch_scope->AcquireX(); 23036e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl ComputeAddress(reg_base, mem); 23046e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return MemOperand(reg_base); 23056e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 23066e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } else if (mem.IsImmediateOffset()) { 230788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int reg_size = registers.GetRegisterSizeInBytes(); 230888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int total_size = registers.GetTotalSizeInBytes(); 230988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int64_t min_offset = mem.GetOffset(); 231088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int64_t max_offset = 231188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois mem.GetOffset() + std::max(0, total_size - 2 * reg_size); 231288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois if ((registers.GetCount() >= 2) && 23136e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl (!Assembler::IsImmLSPair(min_offset, WhichPowerOf2(reg_size)) || 23146e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl !Assembler::IsImmLSPair(max_offset, WhichPowerOf2(reg_size)))) { 23156e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl Register reg_base = scratch_scope->AcquireX(); 23166e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl ComputeAddress(reg_base, mem); 23176e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return MemOperand(reg_base); 23186e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 23196e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 23206e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 23216e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return mem; 23226e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl} 23236e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 2324ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlvoid MacroAssembler::BumpSystemStackPointer(const Operand& space) { 2325b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT(!sp.Is(StackPointer())); 2326ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // TODO: Several callers rely on this not using scratch registers, so we use 2327ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // the assembler directly here. However, this means that large immediate 2328ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // values of 'space' cannot be handled. 232907d1aa5b941ace15deb01e5df2c79e677039c4aeAlexandre Rames ExactAssemblyScope scope(this, kInstructionSize); 2330ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl sub(sp, StackPointer(), space); 2331ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl} 2332ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 2333ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 23345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl// TODO(all): Fix printf for NEON registers, and resolve whether we should be 23355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl// using FPRegister or VRegister here. 23365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 2337ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// This is the main Printf implementation. All callee-saved registers are 2338ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// preserved, but NZCV and the caller-saved registers may be clobbered. 23390f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixlvoid MacroAssembler::PrintfNoPreserve(const char* format, 2340ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl const CPURegister& arg0, 2341ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl const CPURegister& arg1, 2342ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl const CPURegister& arg2, 2343ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl const CPURegister& arg3) { 2344ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // We cannot handle a caller-saved stack pointer. It doesn't make much sense 2345ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // in most cases anyway, so this restriction shouldn't be too serious. 2346b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT(!kCallerSaved.IncludesAliasOf(StackPointer())); 2347b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 23485799d6c5d10729eaade85ad608109c83ed1ae63barmvixl // The provided arguments, and their proper PCS registers. 23495799d6c5d10729eaade85ad608109c83ed1ae63barmvixl CPURegister args[kPrintfMaxArgCount] = {arg0, arg1, arg2, arg3}; 23505799d6c5d10729eaade85ad608109c83ed1ae63barmvixl CPURegister pcs[kPrintfMaxArgCount]; 23515799d6c5d10729eaade85ad608109c83ed1ae63barmvixl 23525799d6c5d10729eaade85ad608109c83ed1ae63barmvixl int arg_count = kPrintfMaxArgCount; 23535799d6c5d10729eaade85ad608109c83ed1ae63barmvixl 23545799d6c5d10729eaade85ad608109c83ed1ae63barmvixl // The PCS varargs registers for printf. Note that x0 is used for the printf 23555799d6c5d10729eaade85ad608109c83ed1ae63barmvixl // format string. 23565799d6c5d10729eaade85ad608109c83ed1ae63barmvixl static const CPURegList kPCSVarargs = 23575799d6c5d10729eaade85ad608109c83ed1ae63barmvixl CPURegList(CPURegister::kRegister, kXRegSize, 1, arg_count); 23585799d6c5d10729eaade85ad608109c83ed1ae63barmvixl static const CPURegList kPCSVarargsFP = 23595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl CPURegList(CPURegister::kVRegister, kDRegSize, 0, arg_count - 1); 23605799d6c5d10729eaade85ad608109c83ed1ae63barmvixl 23615799d6c5d10729eaade85ad608109c83ed1ae63barmvixl // We can use caller-saved registers as scratch values, except for the 23625799d6c5d10729eaade85ad608109c83ed1ae63barmvixl // arguments and the PCS registers where they might need to go. 2363b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl UseScratchRegisterScope temps(this); 23645799d6c5d10729eaade85ad608109c83ed1ae63barmvixl temps.Include(kCallerSaved); 23655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl temps.Include(kCallerSavedV); 23665799d6c5d10729eaade85ad608109c83ed1ae63barmvixl temps.Exclude(kPCSVarargs); 23675799d6c5d10729eaade85ad608109c83ed1ae63barmvixl temps.Exclude(kPCSVarargsFP); 2368b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl temps.Exclude(arg0, arg1, arg2, arg3); 2369ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 23705799d6c5d10729eaade85ad608109c83ed1ae63barmvixl // Copies of the arg lists that we can iterate through. 23715799d6c5d10729eaade85ad608109c83ed1ae63barmvixl CPURegList pcs_varargs = kPCSVarargs; 23725799d6c5d10729eaade85ad608109c83ed1ae63barmvixl CPURegList pcs_varargs_fp = kPCSVarargsFP; 23735799d6c5d10729eaade85ad608109c83ed1ae63barmvixl 23745799d6c5d10729eaade85ad608109c83ed1ae63barmvixl // Place the arguments. There are lots of clever tricks and optimizations we 23755799d6c5d10729eaade85ad608109c83ed1ae63barmvixl // could use here, but Printf is a debug tool so instead we just try to keep 23765799d6c5d10729eaade85ad608109c83ed1ae63barmvixl // it simple: Move each input that isn't already in the right place to a 23775799d6c5d10729eaade85ad608109c83ed1ae63barmvixl // scratch register, then move everything back. 23785799d6c5d10729eaade85ad608109c83ed1ae63barmvixl for (unsigned i = 0; i < kPrintfMaxArgCount; i++) { 23795799d6c5d10729eaade85ad608109c83ed1ae63barmvixl // Work out the proper PCS register for this argument. 2380ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl if (args[i].IsRegister()) { 23815799d6c5d10729eaade85ad608109c83ed1ae63barmvixl pcs[i] = pcs_varargs.PopLowestIndex().X(); 23825799d6c5d10729eaade85ad608109c83ed1ae63barmvixl // We might only need a W register here. We need to know the size of the 23835799d6c5d10729eaade85ad608109c83ed1ae63barmvixl // argument so we can properly encode it for the simulator call. 23845799d6c5d10729eaade85ad608109c83ed1ae63barmvixl if (args[i].Is32Bits()) pcs[i] = pcs[i].W(); 23855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else if (args[i].IsVRegister()) { 23865799d6c5d10729eaade85ad608109c83ed1ae63barmvixl // In C, floats are always cast to doubles for varargs calls. 23875799d6c5d10729eaade85ad608109c83ed1ae63barmvixl pcs[i] = pcs_varargs_fp.PopLowestIndex().D(); 2388ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } else { 23895799d6c5d10729eaade85ad608109c83ed1ae63barmvixl VIXL_ASSERT(args[i].IsNone()); 2390ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl arg_count = i; 2391ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl break; 2392ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 2393ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 23945799d6c5d10729eaade85ad608109c83ed1ae63barmvixl // If the argument is already in the right place, leave it where it is. 23955799d6c5d10729eaade85ad608109c83ed1ae63barmvixl if (args[i].Aliases(pcs[i])) continue; 23965799d6c5d10729eaade85ad608109c83ed1ae63barmvixl 23975799d6c5d10729eaade85ad608109c83ed1ae63barmvixl // Otherwise, if the argument is in a PCS argument register, allocate an 23985799d6c5d10729eaade85ad608109c83ed1ae63barmvixl // appropriate scratch register and then move it out of the way. 23995799d6c5d10729eaade85ad608109c83ed1ae63barmvixl if (kPCSVarargs.IncludesAliasOf(args[i]) || 24005799d6c5d10729eaade85ad608109c83ed1ae63barmvixl kPCSVarargsFP.IncludesAliasOf(args[i])) { 24015799d6c5d10729eaade85ad608109c83ed1ae63barmvixl if (args[i].IsRegister()) { 24025799d6c5d10729eaade85ad608109c83ed1ae63barmvixl Register old_arg = Register(args[i]); 24035799d6c5d10729eaade85ad608109c83ed1ae63barmvixl Register new_arg = temps.AcquireSameSizeAs(old_arg); 24045799d6c5d10729eaade85ad608109c83ed1ae63barmvixl Mov(new_arg, old_arg); 24055799d6c5d10729eaade85ad608109c83ed1ae63barmvixl args[i] = new_arg; 24065799d6c5d10729eaade85ad608109c83ed1ae63barmvixl } else { 24075799d6c5d10729eaade85ad608109c83ed1ae63barmvixl FPRegister old_arg = FPRegister(args[i]); 24085799d6c5d10729eaade85ad608109c83ed1ae63barmvixl FPRegister new_arg = temps.AcquireSameSizeAs(old_arg); 24095799d6c5d10729eaade85ad608109c83ed1ae63barmvixl Fmov(new_arg, old_arg); 24105799d6c5d10729eaade85ad608109c83ed1ae63barmvixl args[i] = new_arg; 24115799d6c5d10729eaade85ad608109c83ed1ae63barmvixl } 24125799d6c5d10729eaade85ad608109c83ed1ae63barmvixl } 2413ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 2414ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 24155799d6c5d10729eaade85ad608109c83ed1ae63barmvixl // Do a second pass to move values into their final positions and perform any 24165799d6c5d10729eaade85ad608109c83ed1ae63barmvixl // conversions that may be required. 24175799d6c5d10729eaade85ad608109c83ed1ae63barmvixl for (int i = 0; i < arg_count; i++) { 241888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_ASSERT(pcs[i].GetType() == args[i].GetType()); 24195799d6c5d10729eaade85ad608109c83ed1ae63barmvixl if (pcs[i].IsRegister()) { 24205799d6c5d10729eaade85ad608109c83ed1ae63barmvixl Mov(Register(pcs[i]), Register(args[i]), kDiscardForSameWReg); 2421ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } else { 24225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(pcs[i].IsVRegister()); 242388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois if (pcs[i].GetSizeInBits() == args[i].GetSizeInBits()) { 24245799d6c5d10729eaade85ad608109c83ed1ae63barmvixl Fmov(FPRegister(pcs[i]), FPRegister(args[i])); 24255799d6c5d10729eaade85ad608109c83ed1ae63barmvixl } else { 24265799d6c5d10729eaade85ad608109c83ed1ae63barmvixl Fcvt(FPRegister(pcs[i]), FPRegister(args[i])); 24275799d6c5d10729eaade85ad608109c83ed1ae63barmvixl } 2428ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 2429ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 2430ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 2431ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // Load the format string into x0, as per the procedure-call standard. 2432ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // 2433ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // To make the code as portable as possible, the format string is encoded 2434ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // directly in the instruction stream. It might be cleaner to encode it in a 2435ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // literal pool, but since Printf is usually used for debugging, it is 2436ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // beneficial for it to be minimally dependent on other features. 24375799d6c5d10729eaade85ad608109c83ed1ae63barmvixl temps.Exclude(x0); 2438ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl Label format_address; 2439ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl Adr(x0, &format_address); 2440ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 2441ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // Emit the format string directly in the instruction stream. 2442c68cb64496485710cdb5b8480f8fee287058c93farmvixl { 24435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl BlockPoolsScope scope(this); 2444c68cb64496485710cdb5b8480f8fee287058c93farmvixl // Data emitted: 2445c68cb64496485710cdb5b8480f8fee287058c93farmvixl // branch 2446c68cb64496485710cdb5b8480f8fee287058c93farmvixl // strlen(format) + 1 (includes null termination) 2447c68cb64496485710cdb5b8480f8fee287058c93farmvixl // padding to next instruction 2448c68cb64496485710cdb5b8480f8fee287058c93farmvixl // unreachable 24490f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl EmissionCheckScope guard(this, 24500f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl AlignUp(strlen(format) + 1, kInstructionSize) + 24510f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl 2 * kInstructionSize); 2452ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl Label after_data; 2453ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl B(&after_data); 2454ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl Bind(&format_address); 2455c68cb64496485710cdb5b8480f8fee287058c93farmvixl EmitString(format); 2456ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl Unreachable(); 2457ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl Bind(&after_data); 2458ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 2459ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 2460ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // We don't pass any arguments on the stack, but we still need to align the C 2461ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // stack pointer to a 16-byte boundary for PCS compliance. 2462ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl if (!sp.Is(StackPointer())) { 2463ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl Bic(sp, StackPointer(), 0xf); 2464ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 2465ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 2466ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // Actually call printf. This part needs special handling for the simulator, 2467ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // since the system printf function will use a different instruction set and 2468ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // the procedure-call standard will not be compatible. 2469703ff06a087f67fccde24a7ffbc8a2e74a406cb1Alexandre Rames if (generate_simulator_code_) { 247007d1aa5b941ace15deb01e5df2c79e677039c4aeAlexandre Rames ExactAssemblyScope scope(this, kPrintfLength); 2471ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl hlt(kPrintfOpcode); 24720f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl dc32(arg_count); // kPrintfArgCountOffset 24735799d6c5d10729eaade85ad608109c83ed1ae63barmvixl 24745799d6c5d10729eaade85ad608109c83ed1ae63barmvixl // Determine the argument pattern. 24755799d6c5d10729eaade85ad608109c83ed1ae63barmvixl uint32_t arg_pattern_list = 0; 24765799d6c5d10729eaade85ad608109c83ed1ae63barmvixl for (int i = 0; i < arg_count; i++) { 24775799d6c5d10729eaade85ad608109c83ed1ae63barmvixl uint32_t arg_pattern; 24785799d6c5d10729eaade85ad608109c83ed1ae63barmvixl if (pcs[i].IsRegister()) { 24795799d6c5d10729eaade85ad608109c83ed1ae63barmvixl arg_pattern = pcs[i].Is32Bits() ? kPrintfArgW : kPrintfArgX; 24805799d6c5d10729eaade85ad608109c83ed1ae63barmvixl } else { 24815799d6c5d10729eaade85ad608109c83ed1ae63barmvixl VIXL_ASSERT(pcs[i].Is64Bits()); 24825799d6c5d10729eaade85ad608109c83ed1ae63barmvixl arg_pattern = kPrintfArgD; 24835799d6c5d10729eaade85ad608109c83ed1ae63barmvixl } 24845799d6c5d10729eaade85ad608109c83ed1ae63barmvixl VIXL_ASSERT(arg_pattern < (1 << kPrintfArgPatternBits)); 24855799d6c5d10729eaade85ad608109c83ed1ae63barmvixl arg_pattern_list |= (arg_pattern << (kPrintfArgPatternBits * i)); 24865799d6c5d10729eaade85ad608109c83ed1ae63barmvixl } 24870f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl dc32(arg_pattern_list); // kPrintfArgPatternListOffset 2488684cd2a7f5845539b58d0da7e012e39df49ceff0armvixl } else { 2489684cd2a7f5845539b58d0da7e012e39df49ceff0armvixl Register tmp = temps.AcquireX(); 2490684cd2a7f5845539b58d0da7e012e39df49ceff0armvixl Mov(tmp, reinterpret_cast<uintptr_t>(printf)); 2491684cd2a7f5845539b58d0da7e012e39df49ceff0armvixl Blr(tmp); 2492ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 2493ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl} 2494ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 2495ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 24960f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixlvoid MacroAssembler::Printf(const char* format, 24975799d6c5d10729eaade85ad608109c83ed1ae63barmvixl CPURegister arg0, 24985799d6c5d10729eaade85ad608109c83ed1ae63barmvixl CPURegister arg1, 24995799d6c5d10729eaade85ad608109c83ed1ae63barmvixl CPURegister arg2, 25005799d6c5d10729eaade85ad608109c83ed1ae63barmvixl CPURegister arg3) { 25015799d6c5d10729eaade85ad608109c83ed1ae63barmvixl // We can only print sp if it is the current stack pointer. 25025799d6c5d10729eaade85ad608109c83ed1ae63barmvixl if (!sp.Is(StackPointer())) { 25035799d6c5d10729eaade85ad608109c83ed1ae63barmvixl VIXL_ASSERT(!sp.Aliases(arg0)); 25045799d6c5d10729eaade85ad608109c83ed1ae63barmvixl VIXL_ASSERT(!sp.Aliases(arg1)); 25055799d6c5d10729eaade85ad608109c83ed1ae63barmvixl VIXL_ASSERT(!sp.Aliases(arg2)); 25065799d6c5d10729eaade85ad608109c83ed1ae63barmvixl VIXL_ASSERT(!sp.Aliases(arg3)); 25075799d6c5d10729eaade85ad608109c83ed1ae63barmvixl } 25085799d6c5d10729eaade85ad608109c83ed1ae63barmvixl 2509b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl // Make sure that the macro assembler doesn't try to use any of our arguments 2510b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl // as scratch registers. 2511b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl UseScratchRegisterScope exclude_all(this); 2512b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl exclude_all.ExcludeAll(); 2513b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 2514ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // Preserve all caller-saved registers as well as NZCV. 2515ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // If sp is the stack pointer, PushCPURegList asserts that the size of each 2516ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // list is a multiple of 16 bytes. 2517ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl PushCPURegList(kCallerSaved); 25185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl PushCPURegList(kCallerSavedV); 2519ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 25200f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl { 25210f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl UseScratchRegisterScope temps(this); 2522b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl // We can use caller-saved registers as scratch values (except for argN). 25235799d6c5d10729eaade85ad608109c83ed1ae63barmvixl temps.Include(kCallerSaved); 25245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl temps.Include(kCallerSavedV); 2525b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl temps.Exclude(arg0, arg1, arg2, arg3); 2526b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 25275799d6c5d10729eaade85ad608109c83ed1ae63barmvixl // If any of the arguments are the current stack pointer, allocate a new 25285799d6c5d10729eaade85ad608109c83ed1ae63barmvixl // register for them, and adjust the value to compensate for pushing the 25295799d6c5d10729eaade85ad608109c83ed1ae63barmvixl // caller-saved registers. 25305799d6c5d10729eaade85ad608109c83ed1ae63barmvixl bool arg0_sp = StackPointer().Aliases(arg0); 25315799d6c5d10729eaade85ad608109c83ed1ae63barmvixl bool arg1_sp = StackPointer().Aliases(arg1); 25325799d6c5d10729eaade85ad608109c83ed1ae63barmvixl bool arg2_sp = StackPointer().Aliases(arg2); 25335799d6c5d10729eaade85ad608109c83ed1ae63barmvixl bool arg3_sp = StackPointer().Aliases(arg3); 25345799d6c5d10729eaade85ad608109c83ed1ae63barmvixl if (arg0_sp || arg1_sp || arg2_sp || arg3_sp) { 25355799d6c5d10729eaade85ad608109c83ed1ae63barmvixl // Allocate a register to hold the original stack pointer value, to pass 25365799d6c5d10729eaade85ad608109c83ed1ae63barmvixl // to PrintfNoPreserve as an argument. 25375799d6c5d10729eaade85ad608109c83ed1ae63barmvixl Register arg_sp = temps.AcquireX(); 25380f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl Add(arg_sp, 25390f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl StackPointer(), 254088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois kCallerSaved.GetTotalSizeInBytes() + 254188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois kCallerSavedV.GetTotalSizeInBytes()); 254288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois if (arg0_sp) arg0 = Register(arg_sp.GetCode(), arg0.GetSizeInBits()); 254388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois if (arg1_sp) arg1 = Register(arg_sp.GetCode(), arg1.GetSizeInBits()); 254488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois if (arg2_sp) arg2 = Register(arg_sp.GetCode(), arg2.GetSizeInBits()); 254588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois if (arg3_sp) arg3 = Register(arg_sp.GetCode(), arg3.GetSizeInBits()); 25465799d6c5d10729eaade85ad608109c83ed1ae63barmvixl } 25475799d6c5d10729eaade85ad608109c83ed1ae63barmvixl 2548b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl // Preserve NZCV. 2549b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl Register tmp = temps.AcquireX(); 2550b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl Mrs(tmp, NZCV); 2551b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl Push(tmp, xzr); 25525799d6c5d10729eaade85ad608109c83ed1ae63barmvixl temps.Release(tmp); 2553b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 2554b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl PrintfNoPreserve(format, arg0, arg1, arg2, arg3); 2555b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 25565799d6c5d10729eaade85ad608109c83ed1ae63barmvixl // Restore NZCV. 25575799d6c5d10729eaade85ad608109c83ed1ae63barmvixl tmp = temps.AcquireX(); 2558b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl Pop(xzr, tmp); 2559b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl Msr(NZCV, tmp); 25605799d6c5d10729eaade85ad608109c83ed1ae63barmvixl temps.Release(tmp); 2561b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl } 2562ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 25635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl PopCPURegList(kCallerSavedV); 2564ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl PopCPURegList(kCallerSaved); 2565ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl} 2566ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 2567ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlvoid MacroAssembler::Trace(TraceParameters parameters, TraceCommand command) { 2568b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT(allow_macro_instructions_); 2569ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 2570703ff06a087f67fccde24a7ffbc8a2e74a406cb1Alexandre Rames if (generate_simulator_code_) { 2571684cd2a7f5845539b58d0da7e012e39df49ceff0armvixl // The arguments to the trace pseudo instruction need to be contiguous in 2572684cd2a7f5845539b58d0da7e012e39df49ceff0armvixl // memory, so make sure we don't try to emit a literal pool. 257307d1aa5b941ace15deb01e5df2c79e677039c4aeAlexandre Rames ExactAssemblyScope scope(this, kTraceLength); 2574ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 2575684cd2a7f5845539b58d0da7e012e39df49ceff0armvixl Label start; 2576684cd2a7f5845539b58d0da7e012e39df49ceff0armvixl bind(&start); 2577ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 2578d3832965c62a8ad461b9ea9eb0994ca6b0a3da2cAlexandre Rames // Refer to simulator-aarch64.h for a description of the marker and its 2579684cd2a7f5845539b58d0da7e012e39df49ceff0armvixl // arguments. 2580684cd2a7f5845539b58d0da7e012e39df49ceff0armvixl hlt(kTraceOpcode); 2581ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 258288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_ASSERT(GetSizeOfCodeGeneratedSince(&start) == kTraceParamsOffset); 2583684cd2a7f5845539b58d0da7e012e39df49ceff0armvixl dc32(parameters); 2584ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 258588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_ASSERT(GetSizeOfCodeGeneratedSince(&start) == kTraceCommandOffset); 2586684cd2a7f5845539b58d0da7e012e39df49ceff0armvixl dc32(command); 2587684cd2a7f5845539b58d0da7e012e39df49ceff0armvixl } else { 2588684cd2a7f5845539b58d0da7e012e39df49ceff0armvixl // Emit nothing on real hardware. 2589684cd2a7f5845539b58d0da7e012e39df49ceff0armvixl USE(parameters, command); 2590684cd2a7f5845539b58d0da7e012e39df49ceff0armvixl } 2591ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl} 2592ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 2593ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 2594ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlvoid MacroAssembler::Log(TraceParameters parameters) { 2595b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT(allow_macro_instructions_); 2596ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 2597703ff06a087f67fccde24a7ffbc8a2e74a406cb1Alexandre Rames if (generate_simulator_code_) { 2598684cd2a7f5845539b58d0da7e012e39df49ceff0armvixl // The arguments to the log pseudo instruction need to be contiguous in 2599684cd2a7f5845539b58d0da7e012e39df49ceff0armvixl // memory, so make sure we don't try to emit a literal pool. 260007d1aa5b941ace15deb01e5df2c79e677039c4aeAlexandre Rames ExactAssemblyScope scope(this, kLogLength); 2601ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 2602684cd2a7f5845539b58d0da7e012e39df49ceff0armvixl Label start; 2603684cd2a7f5845539b58d0da7e012e39df49ceff0armvixl bind(&start); 2604ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 2605d3832965c62a8ad461b9ea9eb0994ca6b0a3da2cAlexandre Rames // Refer to simulator-aarch64.h for a description of the marker and its 2606684cd2a7f5845539b58d0da7e012e39df49ceff0armvixl // arguments. 2607684cd2a7f5845539b58d0da7e012e39df49ceff0armvixl hlt(kLogOpcode); 2608ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 260988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_ASSERT(GetSizeOfCodeGeneratedSince(&start) == kLogParamsOffset); 2610684cd2a7f5845539b58d0da7e012e39df49ceff0armvixl dc32(parameters); 2611684cd2a7f5845539b58d0da7e012e39df49ceff0armvixl } else { 2612684cd2a7f5845539b58d0da7e012e39df49ceff0armvixl // Emit nothing on real hardware. 2613684cd2a7f5845539b58d0da7e012e39df49ceff0armvixl USE(parameters); 2614684cd2a7f5845539b58d0da7e012e39df49ceff0armvixl } 2615ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl} 2616ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 2617578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 2618578645f14e122d2b87d907e298cda7e7d0babf1farmvixlvoid MacroAssembler::EnableInstrumentation() { 2619b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT(!isprint(InstrumentStateEnable)); 262007d1aa5b941ace15deb01e5df2c79e677039c4aeAlexandre Rames ExactAssemblyScope scope(this, kInstructionSize); 2621578645f14e122d2b87d907e298cda7e7d0babf1farmvixl movn(xzr, InstrumentStateEnable); 2622578645f14e122d2b87d907e298cda7e7d0babf1farmvixl} 2623578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 2624578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 2625578645f14e122d2b87d907e298cda7e7d0babf1farmvixlvoid MacroAssembler::DisableInstrumentation() { 2626b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT(!isprint(InstrumentStateDisable)); 262707d1aa5b941ace15deb01e5df2c79e677039c4aeAlexandre Rames ExactAssemblyScope scope(this, kInstructionSize); 2628578645f14e122d2b87d907e298cda7e7d0babf1farmvixl movn(xzr, InstrumentStateDisable); 2629578645f14e122d2b87d907e298cda7e7d0babf1farmvixl} 2630578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 2631578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 2632578645f14e122d2b87d907e298cda7e7d0babf1farmvixlvoid MacroAssembler::AnnotateInstrumentation(const char* marker_name) { 2633b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT(strlen(marker_name) == 2); 2634578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 2635578645f14e122d2b87d907e298cda7e7d0babf1farmvixl // We allow only printable characters in the marker names. Unprintable 2636578645f14e122d2b87d907e298cda7e7d0babf1farmvixl // characters are reserved for controlling features of the instrumentation. 2637b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT(isprint(marker_name[0]) && isprint(marker_name[1])); 2638578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 263907d1aa5b941ace15deb01e5df2c79e677039c4aeAlexandre Rames ExactAssemblyScope scope(this, kInstructionSize); 2640578645f14e122d2b87d907e298cda7e7d0babf1farmvixl movn(xzr, (marker_name[1] << 8) | marker_name[0]); 2641578645f14e122d2b87d907e298cda7e7d0babf1farmvixl} 2642578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 2643b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 2644330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixlvoid UseScratchRegisterScope::Open(MacroAssembler* masm) { 2645e8ce9f0ec7fe9484fca0c446ecc8a9d7929bea66Jacob Bramley VIXL_ASSERT(masm_ == NULL); 26460f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl VIXL_ASSERT(masm != NULL); 2647e8ce9f0ec7fe9484fca0c446ecc8a9d7929bea66Jacob Bramley masm_ = masm; 2648330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl 2649e8ce9f0ec7fe9484fca0c446ecc8a9d7929bea66Jacob Bramley CPURegList* available = masm->GetScratchRegisterList(); 2650e8ce9f0ec7fe9484fca0c446ecc8a9d7929bea66Jacob Bramley CPURegList* available_fp = masm->GetScratchFPRegisterList(); 2651e8ce9f0ec7fe9484fca0c446ecc8a9d7929bea66Jacob Bramley old_available_ = available->GetList(); 2652e8ce9f0ec7fe9484fca0c446ecc8a9d7929bea66Jacob Bramley old_availablefp_ = available_fp->GetList(); 2653e8ce9f0ec7fe9484fca0c446ecc8a9d7929bea66Jacob Bramley VIXL_ASSERT(available->GetType() == CPURegister::kRegister); 2654e8ce9f0ec7fe9484fca0c446ecc8a9d7929bea66Jacob Bramley VIXL_ASSERT(available_fp->GetType() == CPURegister::kVRegister); 2655330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl 2656e8ce9f0ec7fe9484fca0c446ecc8a9d7929bea66Jacob Bramley parent_ = masm->GetCurrentScratchRegisterScope(); 2657e8ce9f0ec7fe9484fca0c446ecc8a9d7929bea66Jacob Bramley masm->SetCurrentScratchRegisterScope(this); 2658330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl} 2659330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl 2660330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl 2661e8ce9f0ec7fe9484fca0c446ecc8a9d7929bea66Jacob Bramleyvoid UseScratchRegisterScope::Close() { 2662e8ce9f0ec7fe9484fca0c446ecc8a9d7929bea66Jacob Bramley if (masm_ != NULL) { 2663e8ce9f0ec7fe9484fca0c446ecc8a9d7929bea66Jacob Bramley // Ensure that scopes nest perfectly, and do not outlive their parents. 2664e8ce9f0ec7fe9484fca0c446ecc8a9d7929bea66Jacob Bramley // This is a run-time check because the order of destruction of objects in 2665e8ce9f0ec7fe9484fca0c446ecc8a9d7929bea66Jacob Bramley // the _same_ scope is implementation-defined, and is likely to change in 2666e8ce9f0ec7fe9484fca0c446ecc8a9d7929bea66Jacob Bramley // optimised builds. 2667e8ce9f0ec7fe9484fca0c446ecc8a9d7929bea66Jacob Bramley VIXL_CHECK(masm_->GetCurrentScratchRegisterScope() == this); 2668e8ce9f0ec7fe9484fca0c446ecc8a9d7929bea66Jacob Bramley masm_->SetCurrentScratchRegisterScope(parent_); 2669330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl 2670e8ce9f0ec7fe9484fca0c446ecc8a9d7929bea66Jacob Bramley masm_->GetScratchRegisterList()->SetList(old_available_); 2671e8ce9f0ec7fe9484fca0c446ecc8a9d7929bea66Jacob Bramley masm_->GetScratchFPRegisterList()->SetList(old_availablefp_); 2672330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl 2673e8ce9f0ec7fe9484fca0c446ecc8a9d7929bea66Jacob Bramley masm_ = NULL; 2674e8ce9f0ec7fe9484fca0c446ecc8a9d7929bea66Jacob Bramley } 2675e8ce9f0ec7fe9484fca0c446ecc8a9d7929bea66Jacob Bramley} 2676b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 2677b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 26785799d6c5d10729eaade85ad608109c83ed1ae63barmvixlbool UseScratchRegisterScope::IsAvailable(const CPURegister& reg) const { 2679e8ce9f0ec7fe9484fca0c446ecc8a9d7929bea66Jacob Bramley return masm_->GetScratchRegisterList()->IncludesAliasOf(reg) || 2680e8ce9f0ec7fe9484fca0c446ecc8a9d7929bea66Jacob Bramley masm_->GetScratchFPRegisterList()->IncludesAliasOf(reg); 26815799d6c5d10729eaade85ad608109c83ed1ae63barmvixl} 26825799d6c5d10729eaade85ad608109c83ed1ae63barmvixl 26835799d6c5d10729eaade85ad608109c83ed1ae63barmvixl 26844e7c93cc256c7719d69279d64e4f5d09044b8b2cAlexandre RamesRegister UseScratchRegisterScope::AcquireRegisterOfSize(int size_in_bits) { 2685e8ce9f0ec7fe9484fca0c446ecc8a9d7929bea66Jacob Bramley int code = AcquireNextAvailable(masm_->GetScratchRegisterList()).GetCode(); 26864e7c93cc256c7719d69279d64e4f5d09044b8b2cAlexandre Rames return Register(code, size_in_bits); 2687b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl} 2688b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 2689b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 26904e7c93cc256c7719d69279d64e4f5d09044b8b2cAlexandre RamesFPRegister UseScratchRegisterScope::AcquireVRegisterOfSize(int size_in_bits) { 2691e8ce9f0ec7fe9484fca0c446ecc8a9d7929bea66Jacob Bramley int code = AcquireNextAvailable(masm_->GetScratchFPRegisterList()).GetCode(); 26924e7c93cc256c7719d69279d64e4f5d09044b8b2cAlexandre Rames return FPRegister(code, size_in_bits); 2693b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl} 2694b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 2695b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 2696b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixlvoid UseScratchRegisterScope::Release(const CPURegister& reg) { 2697e8ce9f0ec7fe9484fca0c446ecc8a9d7929bea66Jacob Bramley VIXL_ASSERT(masm_ != NULL); 2698b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl if (reg.IsRegister()) { 2699e8ce9f0ec7fe9484fca0c446ecc8a9d7929bea66Jacob Bramley ReleaseByCode(masm_->GetScratchRegisterList(), reg.GetCode()); 2700b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl } else if (reg.IsFPRegister()) { 2701e8ce9f0ec7fe9484fca0c446ecc8a9d7929bea66Jacob Bramley ReleaseByCode(masm_->GetScratchFPRegisterList(), reg.GetCode()); 2702b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl } else { 2703b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT(reg.IsNone()); 2704b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl } 2705b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl} 2706b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 2707b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 27085799d6c5d10729eaade85ad608109c83ed1ae63barmvixlvoid UseScratchRegisterScope::Include(const CPURegList& list) { 2709e8ce9f0ec7fe9484fca0c446ecc8a9d7929bea66Jacob Bramley VIXL_ASSERT(masm_ != NULL); 271088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois if (list.GetType() == CPURegister::kRegister) { 27115799d6c5d10729eaade85ad608109c83ed1ae63barmvixl // Make sure that neither sp nor xzr are included the list. 2712e8ce9f0ec7fe9484fca0c446ecc8a9d7929bea66Jacob Bramley IncludeByRegList(masm_->GetScratchRegisterList(), 271388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois list.GetList() & ~(xzr.GetBit() | sp.GetBit())); 27145799d6c5d10729eaade85ad608109c83ed1ae63barmvixl } else { 271588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_ASSERT(list.GetType() == CPURegister::kVRegister); 2716e8ce9f0ec7fe9484fca0c446ecc8a9d7929bea66Jacob Bramley IncludeByRegList(masm_->GetScratchFPRegisterList(), list.GetList()); 27175799d6c5d10729eaade85ad608109c83ed1ae63barmvixl } 27185799d6c5d10729eaade85ad608109c83ed1ae63barmvixl} 27195799d6c5d10729eaade85ad608109c83ed1ae63barmvixl 27205799d6c5d10729eaade85ad608109c83ed1ae63barmvixl 2721b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixlvoid UseScratchRegisterScope::Include(const Register& reg1, 2722b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl const Register& reg2, 2723b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl const Register& reg3, 2724b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl const Register& reg4) { 2725e8ce9f0ec7fe9484fca0c446ecc8a9d7929bea66Jacob Bramley VIXL_ASSERT(masm_ != NULL); 272688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegList include = 272788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois reg1.GetBit() | reg2.GetBit() | reg3.GetBit() | reg4.GetBit(); 2728b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl // Make sure that neither sp nor xzr are included the list. 272988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois include &= ~(xzr.GetBit() | sp.GetBit()); 2730b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 2731e8ce9f0ec7fe9484fca0c446ecc8a9d7929bea66Jacob Bramley IncludeByRegList(masm_->GetScratchRegisterList(), include); 2732b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl} 2733b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 2734b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 2735b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixlvoid UseScratchRegisterScope::Include(const FPRegister& reg1, 2736b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl const FPRegister& reg2, 2737b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl const FPRegister& reg3, 2738b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl const FPRegister& reg4) { 273988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegList include = 274088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois reg1.GetBit() | reg2.GetBit() | reg3.GetBit() | reg4.GetBit(); 2741e8ce9f0ec7fe9484fca0c446ecc8a9d7929bea66Jacob Bramley IncludeByRegList(masm_->GetScratchFPRegisterList(), include); 2742b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl} 2743b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 2744b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 27455799d6c5d10729eaade85ad608109c83ed1ae63barmvixlvoid UseScratchRegisterScope::Exclude(const CPURegList& list) { 274688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois if (list.GetType() == CPURegister::kRegister) { 2747e8ce9f0ec7fe9484fca0c446ecc8a9d7929bea66Jacob Bramley ExcludeByRegList(masm_->GetScratchRegisterList(), list.GetList()); 27485799d6c5d10729eaade85ad608109c83ed1ae63barmvixl } else { 274988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_ASSERT(list.GetType() == CPURegister::kVRegister); 2750e8ce9f0ec7fe9484fca0c446ecc8a9d7929bea66Jacob Bramley ExcludeByRegList(masm_->GetScratchFPRegisterList(), list.GetList()); 27515799d6c5d10729eaade85ad608109c83ed1ae63barmvixl } 27525799d6c5d10729eaade85ad608109c83ed1ae63barmvixl} 27535799d6c5d10729eaade85ad608109c83ed1ae63barmvixl 27545799d6c5d10729eaade85ad608109c83ed1ae63barmvixl 2755b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixlvoid UseScratchRegisterScope::Exclude(const Register& reg1, 2756b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl const Register& reg2, 2757b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl const Register& reg3, 2758b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl const Register& reg4) { 275988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegList exclude = 276088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois reg1.GetBit() | reg2.GetBit() | reg3.GetBit() | reg4.GetBit(); 2761e8ce9f0ec7fe9484fca0c446ecc8a9d7929bea66Jacob Bramley ExcludeByRegList(masm_->GetScratchRegisterList(), exclude); 2762b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl} 2763b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 2764b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 2765b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixlvoid UseScratchRegisterScope::Exclude(const FPRegister& reg1, 2766b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl const FPRegister& reg2, 2767b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl const FPRegister& reg3, 2768b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl const FPRegister& reg4) { 276988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegList excludefp = 277088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois reg1.GetBit() | reg2.GetBit() | reg3.GetBit() | reg4.GetBit(); 2771e8ce9f0ec7fe9484fca0c446ecc8a9d7929bea66Jacob Bramley ExcludeByRegList(masm_->GetScratchFPRegisterList(), excludefp); 2772b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl} 2773b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 2774b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 2775b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixlvoid UseScratchRegisterScope::Exclude(const CPURegister& reg1, 2776b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl const CPURegister& reg2, 2777b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl const CPURegister& reg3, 2778b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl const CPURegister& reg4) { 2779b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl RegList exclude = 0; 2780b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl RegList excludefp = 0; 2781b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 2782b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl const CPURegister regs[] = {reg1, reg2, reg3, reg4}; 2783b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 2784b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl for (unsigned i = 0; i < (sizeof(regs) / sizeof(regs[0])); i++) { 2785b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl if (regs[i].IsRegister()) { 278688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois exclude |= regs[i].GetBit(); 2787b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl } else if (regs[i].IsFPRegister()) { 278888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois excludefp |= regs[i].GetBit(); 2789b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl } else { 2790b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT(regs[i].IsNone()); 2791b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl } 2792b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl } 2793b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 2794e8ce9f0ec7fe9484fca0c446ecc8a9d7929bea66Jacob Bramley ExcludeByRegList(masm_->GetScratchRegisterList(), exclude); 2795e8ce9f0ec7fe9484fca0c446ecc8a9d7929bea66Jacob Bramley ExcludeByRegList(masm_->GetScratchFPRegisterList(), excludefp); 2796b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl} 2797b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 2798b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 2799b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixlvoid UseScratchRegisterScope::ExcludeAll() { 2800e8ce9f0ec7fe9484fca0c446ecc8a9d7929bea66Jacob Bramley ExcludeByRegList(masm_->GetScratchRegisterList(), 2801e8ce9f0ec7fe9484fca0c446ecc8a9d7929bea66Jacob Bramley masm_->GetScratchRegisterList()->GetList()); 2802e8ce9f0ec7fe9484fca0c446ecc8a9d7929bea66Jacob Bramley ExcludeByRegList(masm_->GetScratchFPRegisterList(), 2803e8ce9f0ec7fe9484fca0c446ecc8a9d7929bea66Jacob Bramley masm_->GetScratchFPRegisterList()->GetList()); 2804b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl} 2805b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 2806b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 2807b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixlCPURegister UseScratchRegisterScope::AcquireNextAvailable( 2808b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl CPURegList* available) { 2809b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_CHECK(!available->IsEmpty()); 2810b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl CPURegister result = available->PopLowestIndex(); 2811b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT(!AreAliased(result, xzr, sp)); 2812b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl return result; 2813b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl} 2814b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 2815b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 2816b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixlvoid UseScratchRegisterScope::ReleaseByCode(CPURegList* available, int code) { 2817b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl ReleaseByRegList(available, static_cast<RegList>(1) << code); 2818b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl} 2819b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 2820b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 2821b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixlvoid UseScratchRegisterScope::ReleaseByRegList(CPURegList* available, 2822b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl RegList regs) { 282388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois available->SetList(available->GetList() | regs); 2824b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl} 2825b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 2826b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 2827b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixlvoid UseScratchRegisterScope::IncludeByRegList(CPURegList* available, 2828b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl RegList regs) { 282988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois available->SetList(available->GetList() | regs); 2830b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl} 2831b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 2832b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 2833b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixlvoid UseScratchRegisterScope::ExcludeByRegList(CPURegList* available, 2834b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl RegList exclude) { 283588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois available->SetList(available->GetList() & ~exclude); 2836b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl} 2837b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 283888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois} // namespace aarch64 2839ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl} // namespace vixl 2840