simulator-aarch64.h revision 482d4df29d1466ff87d94e74034f1a8659f1b354
1b78f13911bfe6eda303e91ef215c87a165aae8aeAlexandre Rames// Copyright 2015, VIXL authors 2ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// All rights reserved. 3ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// 4ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// Redistribution and use in source and binary forms, with or without 5ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// modification, are permitted provided that the following conditions are met: 6ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// 7ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// * Redistributions of source code must retain the above copyright notice, 8ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// this list of conditions and the following disclaimer. 9ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// * Redistributions in binary form must reproduce the above copyright notice, 10ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// this list of conditions and the following disclaimer in the documentation 11ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// and/or other materials provided with the distribution. 12ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// * Neither the name of ARM Limited nor the names of its contributors may be 13ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// used to endorse or promote products derived from this software without 14ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// specific prior written permission. 15ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// 16ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND 17ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 20ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 23ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 27d3832965c62a8ad461b9ea9eb0994ca6b0a3da2cAlexandre Rames#ifndef VIXL_AARCH64_SIMULATOR_AARCH64_H_ 28d3832965c62a8ad461b9ea9eb0994ca6b0a3da2cAlexandre Rames#define VIXL_AARCH64_SIMULATOR_AARCH64_H_ 29ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 301f9074de150536670464a85ef8e0ede60d26e3f9Alexandre Rames#include "globals-vixl.h" 311f9074de150536670464a85ef8e0ede60d26e3f9Alexandre Rames#include "utils-vixl.h" 32b68bacb75c1ab265fc539afa93964c7f51f35589Alexandre Rames 33064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames#include "aarch64/abi-aarch64.h" 34d3832965c62a8ad461b9ea9eb0994ca6b0a3da2cAlexandre Rames#include "aarch64/disasm-aarch64.h" 35d3832965c62a8ad461b9ea9eb0994ca6b0a3da2cAlexandre Rames#include "aarch64/instructions-aarch64.h" 36d3832965c62a8ad461b9ea9eb0994ca6b0a3da2cAlexandre Rames#include "aarch64/instrument-aarch64.h" 37d3832965c62a8ad461b9ea9eb0994ca6b0a3da2cAlexandre Rames#include "aarch64/simulator-constants-aarch64.h" 38ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 39064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames// These are only used for the ABI feature, and depend on checks performed for 40064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames// it. 41ca73ba046c11d65b6dce59cfd26847d14aba06abAlexandre Rames#ifdef VIXL_HAS_ABI_SUPPORT 42064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames#include <tuple> 43064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames#if __cplusplus >= 201402L 44064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames// Required for `std::index_sequence` 45064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames#include <utility> 46064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames#endif 47064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames#endif 48064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames 49ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlnamespace vixl { 5088c46b84df005638546de5e4e965bdcc31352f48Pierre Langloisnamespace aarch64 { 51ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 526e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl// Assemble the specified IEEE-754 components into the target type and apply 536e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl// appropriate rounding. 546e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl// sign: 0 = positive, 1 = negative 556e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl// exponent: Unbiased IEEE-754 exponent. 566e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl// mantissa: The mantissa of the input. The top bit (which is not encoded for 576e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl// normal IEEE-754 values) must not be omitted. This bit has the 586e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl// value 'pow(2, exponent)'. 596e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl// 606e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl// The input value is assumed to be a normalized value. That is, the input may 616e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl// not be infinity or NaN. If the source value is subnormal, it must be 626e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl// normalized before calling this function such that the highest set bit in the 636e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl// mantissa has the value 'pow(2, exponent)'. 646e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl// 656e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl// Callers should use FPRoundToFloat or FPRoundToDouble directly, rather than 666e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl// calling a templated FPRound. 676e2c8275d5f34a531fe1eef7a7aa877601be8558armvixltemplate <class T, int ebits, int mbits> 680f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixlT FPRound(int64_t sign, 690f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl int64_t exponent, 700f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl uint64_t mantissa, 710f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl FPRounding round_mode) { 726e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl VIXL_ASSERT((sign == 0) || (sign == 1)); 736e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 746e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // Only FPTieEven and FPRoundOdd rounding modes are implemented. 756e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl VIXL_ASSERT((round_mode == FPTieEven) || (round_mode == FPRoundOdd)); 766e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 776e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // Rounding can promote subnormals to normals, and normals to infinities. For 786e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // example, a double with exponent 127 (FLT_MAX_EXP) would appear to be 796e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // encodable as a float, but rounding based on the low-order mantissa bits 806e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // could make it overflow. With ties-to-even rounding, this value would become 816e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // an infinity. 826e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 836e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // ---- Rounding Method ---- 846e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // 856e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // The exponent is irrelevant in the rounding operation, so we treat the 866e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // lowest-order bit that will fit into the result ('onebit') as having 876e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // the value '1'. Similarly, the highest-order bit that won't fit into 886e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // the result ('halfbit') has the value '0.5'. The 'point' sits between 896e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // 'onebit' and 'halfbit': 906e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // 916e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // These bits fit into the result. 926e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // |---------------------| 936e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // mantissa = 0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 946e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // || 956e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // / | 966e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // / halfbit 976e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // onebit 986e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // 996e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // For subnormal outputs, the range of representable bits is smaller and 1006e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // the position of onebit and halfbit depends on the exponent of the 1016e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // input, but the method is otherwise similar. 1026e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // 1036e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // onebit(frac) 1046e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // | 1056e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // | halfbit(frac) halfbit(adjusted) 1066e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // | / / 1076e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // | | | 1086e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // 0b00.0 (exact) -> 0b00.0 (exact) -> 0b00 1096e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // 0b00.0... -> 0b00.0... -> 0b00 1106e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // 0b00.1 (exact) -> 0b00.0111..111 -> 0b00 1116e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // 0b00.1... -> 0b00.1... -> 0b01 1126e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // 0b01.0 (exact) -> 0b01.0 (exact) -> 0b01 1136e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // 0b01.0... -> 0b01.0... -> 0b01 1146e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // 0b01.1 (exact) -> 0b01.1 (exact) -> 0b10 1156e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // 0b01.1... -> 0b01.1... -> 0b10 1166e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // 0b10.0 (exact) -> 0b10.0 (exact) -> 0b10 1176e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // 0b10.0... -> 0b10.0... -> 0b10 1186e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // 0b10.1 (exact) -> 0b10.0111..111 -> 0b10 1196e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // 0b10.1... -> 0b10.1... -> 0b11 1206e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // 0b11.0 (exact) -> 0b11.0 (exact) -> 0b11 1216e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // ... / | / | 1226e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // / | / | 1236e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // / | 1246e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // adjusted = frac - (halfbit(mantissa) & ~onebit(frac)); / | 1256e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // 1266e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // mantissa = (mantissa >> shift) + halfbit(adjusted); 1276e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 1286e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl static const int mantissa_offset = 0; 1296e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl static const int exponent_offset = mantissa_offset + mbits; 1306e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl static const int sign_offset = exponent_offset + ebits; 1316e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl VIXL_ASSERT(sign_offset == (sizeof(T) * 8 - 1)); 1326e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 1336e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // Bail out early for zero inputs. 1346e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if (mantissa == 0) { 135db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl return static_cast<T>(sign << sign_offset); 1366e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 1376e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 1386e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // If all bits in the exponent are set, the value is infinite or NaN. 1396e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // This is true for all binary IEEE-754 formats. 1406e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl static const int infinite_exponent = (1 << ebits) - 1; 1416e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl static const int max_normal_exponent = infinite_exponent - 1; 1426e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 1436e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // Apply the exponent bias to encode it for the result. Doing this early makes 1446e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // it easy to detect values that will be infinite or subnormal. 1456e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl exponent += max_normal_exponent >> 1; 1466e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 1476e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if (exponent > max_normal_exponent) { 1486e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // Overflow: the input is too large for the result type to represent. 1496e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if (round_mode == FPTieEven) { 1506e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // FPTieEven rounding mode handles overflows using infinities. 1516e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl exponent = infinite_exponent; 1526e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl mantissa = 0; 1536e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } else { 1546e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl VIXL_ASSERT(round_mode == FPRoundOdd); 1556e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // FPRoundOdd rounding mode handles overflows using the largest magnitude 1566e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // normal number. 1576e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl exponent = max_normal_exponent; 1586e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl mantissa = (UINT64_C(1) << exponent_offset) - 1; 1596e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 160db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl return static_cast<T>((sign << sign_offset) | 161db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl (exponent << exponent_offset) | 162db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl (mantissa << mantissa_offset)); 1636e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 1646e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 1656e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // Calculate the shift required to move the top mantissa bit to the proper 1666e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // place in the destination type. 1676e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl const int highest_significant_bit = 63 - CountLeadingZeros(mantissa); 1686e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl int shift = highest_significant_bit - mbits; 1696e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 1706e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if (exponent <= 0) { 1716e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // The output will be subnormal (before rounding). 1726e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // For subnormal outputs, the shift must be adjusted by the exponent. The +1 1736e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // is necessary because the exponent of a subnormal value (encoded as 0) is 1746e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // the same as the exponent of the smallest normal value (encoded as 1). 1756e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl shift += -exponent + 1; 1766e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 1776e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // Handle inputs that would produce a zero output. 1786e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // 1796e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // Shifts higher than highest_significant_bit+1 will always produce a zero 1806e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // result. A shift of exactly highest_significant_bit+1 might produce a 1816e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // non-zero result after rounding. 1826e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if (shift > (highest_significant_bit + 1)) { 1836e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if (round_mode == FPTieEven) { 1846e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // The result will always be +/-0.0. 185db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl return static_cast<T>(sign << sign_offset); 1866e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } else { 1876e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl VIXL_ASSERT(round_mode == FPRoundOdd); 1886e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl VIXL_ASSERT(mantissa != 0); 1896e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // For FPRoundOdd, if the mantissa is too small to represent and 1906e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // non-zero return the next "odd" value. 191db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl return static_cast<T>((sign << sign_offset) | 1); 1926e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 1936e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 1946e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 1956e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // Properly encode the exponent for a subnormal output. 1966e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl exponent = 0; 1976e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } else { 1986e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // Clear the topmost mantissa bit, since this is not encoded in IEEE-754 1996e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // normal values. 2006e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl mantissa &= ~(UINT64_C(1) << highest_significant_bit); 2016e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 2026e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 2036e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if (shift > 0) { 2046e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if (round_mode == FPTieEven) { 2056e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // We have to shift the mantissa to the right. Some precision is lost, so 2066e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // we need to apply rounding. 2076e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl uint64_t onebit_mantissa = (mantissa >> (shift)) & 1; 2080f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl uint64_t halfbit_mantissa = (mantissa >> (shift - 1)) & 1; 2096e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl uint64_t adjustment = (halfbit_mantissa & ~onebit_mantissa); 2106e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl uint64_t adjusted = mantissa - adjustment; 2110f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl T halfbit_adjusted = (adjusted >> (shift - 1)) & 1; 2126e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 2130f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl T result = 2140f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl static_cast<T>((sign << sign_offset) | (exponent << exponent_offset) | 2150f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl ((mantissa >> shift) << mantissa_offset)); 2166e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 2176e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // A very large mantissa can overflow during rounding. If this happens, 2186e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // the exponent should be incremented and the mantissa set to 1.0 2196e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // (encoded as 0). Applying halfbit_adjusted after assembling the float 2206e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // has the nice side-effect that this case is handled for free. 2216e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // 2226e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // This also handles cases where a very large finite value overflows to 2236e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // infinity, or where a very large subnormal value overflows to become 2246e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // normal. 2256e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return result + halfbit_adjusted; 2266e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } else { 2276e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl VIXL_ASSERT(round_mode == FPRoundOdd); 2286e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // If any bits at position halfbit or below are set, onebit (ie. the 2296e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // bottom bit of the resulting mantissa) must be set. 2306e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl uint64_t fractional_bits = mantissa & ((UINT64_C(1) << shift) - 1); 2316e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if (fractional_bits != 0) { 2326e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl mantissa |= UINT64_C(1) << shift; 2336e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 2346e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 235db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl return static_cast<T>((sign << sign_offset) | 236db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl (exponent << exponent_offset) | 237db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl ((mantissa >> shift) << mantissa_offset)); 2386e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 2396e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } else { 2406e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // We have to shift the mantissa to the left (or not at all). The input 2416e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // mantissa is exactly representable in the output mantissa, so apply no 2426e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // rounding correction. 243db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl return static_cast<T>((sign << sign_offset) | 244db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl (exponent << exponent_offset) | 245db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl ((mantissa << -shift) << mantissa_offset)); 2466e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 2476e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl} 2486e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 2495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 2505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl// Representation of memory, with typed getters and setters for access. 2515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlclass Memory { 2525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl public: 2535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl template <typename T> 2545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl static T AddressUntag(T address) { 2555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Cast the address using a C-style cast. A reinterpret_cast would be 2565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // appropriate, but it can't cast one integral type to another. 2575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t bits = (uint64_t)address; 2585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return (T)(bits & ~kAddressTagMask); 2595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 2605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 2615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl template <typename T, typename A> 2625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl static T Read(A address) { 2635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl T value; 2645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl address = AddressUntag(address); 2655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT((sizeof(value) == 1) || (sizeof(value) == 2) || 2665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl (sizeof(value) == 4) || (sizeof(value) == 8) || 2675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl (sizeof(value) == 16)); 2680f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl memcpy(&value, reinterpret_cast<const char*>(address), sizeof(value)); 2695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return value; 2705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 2715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 2725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl template <typename T, typename A> 2735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl static void Write(A address, T value) { 2745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl address = AddressUntag(address); 2755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT((sizeof(value) == 1) || (sizeof(value) == 2) || 2765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl (sizeof(value) == 4) || (sizeof(value) == 8) || 2775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl (sizeof(value) == 16)); 2780f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl memcpy(reinterpret_cast<char*>(address), &value, sizeof(value)); 2795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 2805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl}; 2815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 2825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl// Represent a register (r0-r31, v0-v31). 2830f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixltemplate <int kSizeInBytes> 2845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlclass SimRegisterBase { 2855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl public: 2865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimRegisterBase() : written_since_last_log_(false) {} 2875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 2885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Write the specified value. The value is zero-extended if necessary. 2890f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl template <typename T> 29088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void Write(T new_value) { 2915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_STATIC_ASSERT(sizeof(new_value) <= kSizeInBytes); 2925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (sizeof(new_value) < kSizeInBytes) { 2935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // All AArch64 registers are zero-extending. 2945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl memset(value_ + sizeof(new_value), 0, kSizeInBytes - sizeof(new_value)); 2955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 2965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl memcpy(value_, &new_value, sizeof(new_value)); 2975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl NotifyRegisterWrite(); 2985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 29988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois template <typename T> 30088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("Write", void Set(T new_value)) { 30188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois Write(new_value); 30288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 3035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 3045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Insert a typed value into a register, leaving the rest of the register 3055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // unchanged. The lane parameter indicates where in the register the value 3065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // should be inserted, in the range [ 0, sizeof(value_) / sizeof(T) ), where 3075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // 0 represents the least significant bits. 3080f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl template <typename T> 3095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void Insert(int lane, T new_value) { 3105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(lane >= 0); 3110f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl VIXL_ASSERT((sizeof(new_value) + (lane * sizeof(new_value))) <= 3120f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl kSizeInBytes); 3135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl memcpy(&value_[lane * sizeof(new_value)], &new_value, sizeof(new_value)); 3145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl NotifyRegisterWrite(); 3155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 3165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 31788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois // Get the value as the specified type. The value is truncated if necessary. 31888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois template <typename T> 31988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois T Get() const { 32088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return GetLane<T>(0); 32188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 32288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois 32388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois // Get the lane value as the specified type. The value is truncated if 32488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois // necessary. 3250f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl template <typename T> 32688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois T GetLane(int lane) const { 3275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl T result; 3285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(lane >= 0); 3295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT((sizeof(result) + (lane * sizeof(result))) <= kSizeInBytes); 3305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl memcpy(&result, &value_[lane * sizeof(result)], sizeof(result)); 3315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return result; 3325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 33388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois template <typename T> 33488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("GetLane", T Get(int lane) const) { 33588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return GetLane(lane); 33688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 3375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 3385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // TODO: Make this return a map of updated bytes, so that we can highlight 3395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // updated lanes for load-and-insert. (That never happens for scalar code, but 3405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // NEON has some instructions that can update individual lanes.) 3410f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl bool WrittenSinceLastLog() const { return written_since_last_log_; } 3425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 3430f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl void NotifyRegisterLogged() { written_since_last_log_ = false; } 3445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 3455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl protected: 3465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint8_t value_[kSizeInBytes]; 3475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 3485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Helpers to aid with register tracing. 3495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl bool written_since_last_log_; 3505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 3510f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl void NotifyRegisterWrite() { written_since_last_log_ = true; } 3525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl}; 3530f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixltypedef SimRegisterBase<kXRegSizeInBytes> SimRegister; // r0-r31 3540f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixltypedef SimRegisterBase<kQRegSizeInBytes> SimVRegister; // v0-v31 3555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 3565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl// Representation of a vector register, with typed getters and setters for lanes 3575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl// and additional information to represent lane state. 3585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlclass LogicVRegister { 3595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl public: 3605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl inline LogicVRegister(SimVRegister& other) // NOLINT 3615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl : register_(other) { 3625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (unsigned i = 0; i < sizeof(saturated_) / sizeof(saturated_[0]); i++) { 3635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl saturated_[i] = kNotSaturated; 3645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 3655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (unsigned i = 0; i < sizeof(round_) / sizeof(round_[0]); i++) { 3665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl round_[i] = 0; 3675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 3685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 3695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 3705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int64_t Int(VectorFormat vform, int index) const { 3715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int64_t element; 3725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl switch (LaneSizeInBitsFromFormat(vform)) { 3730f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 8: 37488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois element = register_.GetLane<int8_t>(index); 3750f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 3760f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 16: 37788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois element = register_.GetLane<int16_t>(index); 3780f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 3790f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 32: 38088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois element = register_.GetLane<int32_t>(index); 3810f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 3820f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 64: 38388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois element = register_.GetLane<int64_t>(index); 3840f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 3850f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl default: 3860f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl VIXL_UNREACHABLE(); 3870f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl return 0; 3885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 3895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return element; 3905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 3915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 3925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t Uint(VectorFormat vform, int index) const { 3935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t element; 3945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl switch (LaneSizeInBitsFromFormat(vform)) { 3950f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 8: 39688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois element = register_.GetLane<uint8_t>(index); 3970f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 3980f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 16: 39988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois element = register_.GetLane<uint16_t>(index); 4000f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 4010f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 32: 40288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois element = register_.GetLane<uint32_t>(index); 4030f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 4040f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 64: 40588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois element = register_.GetLane<uint64_t>(index); 4060f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 4070f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl default: 4080f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl VIXL_UNREACHABLE(); 4090f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl return 0; 4105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 4115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return element; 4125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 4135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 4145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int64_t IntLeftJustified(VectorFormat vform, int index) const { 4155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return Int(vform, index) << (64 - LaneSizeInBitsFromFormat(vform)); 4165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 4175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 4185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t UintLeftJustified(VectorFormat vform, int index) const { 4195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return Uint(vform, index) << (64 - LaneSizeInBitsFromFormat(vform)); 4205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 4215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 4225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void SetInt(VectorFormat vform, int index, int64_t value) const { 4235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl switch (LaneSizeInBitsFromFormat(vform)) { 4240f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 8: 4250f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl register_.Insert(index, static_cast<int8_t>(value)); 4260f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 4270f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 16: 4280f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl register_.Insert(index, static_cast<int16_t>(value)); 4290f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 4300f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 32: 4310f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl register_.Insert(index, static_cast<int32_t>(value)); 4320f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 4330f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 64: 4340f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl register_.Insert(index, static_cast<int64_t>(value)); 4350f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 4360f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl default: 4370f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl VIXL_UNREACHABLE(); 4380f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl return; 4395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 4405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 4415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 4425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void SetUint(VectorFormat vform, int index, uint64_t value) const { 4435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl switch (LaneSizeInBitsFromFormat(vform)) { 4440f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 8: 4450f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl register_.Insert(index, static_cast<uint8_t>(value)); 4460f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 4470f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 16: 4480f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl register_.Insert(index, static_cast<uint16_t>(value)); 4490f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 4500f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 32: 4510f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl register_.Insert(index, static_cast<uint32_t>(value)); 4520f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 4530f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 64: 4540f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl register_.Insert(index, static_cast<uint64_t>(value)); 4550f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 4560f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl default: 4570f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl VIXL_UNREACHABLE(); 4580f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl return; 4595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 4605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 4615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 4625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void ReadUintFromMem(VectorFormat vform, int index, uint64_t addr) const { 4635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl switch (LaneSizeInBitsFromFormat(vform)) { 4640f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 8: 4650f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl register_.Insert(index, Memory::Read<uint8_t>(addr)); 4660f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 4670f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 16: 4680f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl register_.Insert(index, Memory::Read<uint16_t>(addr)); 4690f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 4700f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 32: 4710f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl register_.Insert(index, Memory::Read<uint32_t>(addr)); 4720f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 4730f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 64: 4740f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl register_.Insert(index, Memory::Read<uint64_t>(addr)); 4750f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 4760f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl default: 4770f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl VIXL_UNREACHABLE(); 4780f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl return; 4795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 4805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 4815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 4825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void WriteUintToMem(VectorFormat vform, int index, uint64_t addr) const { 483db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl uint64_t value = Uint(vform, index); 4845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl switch (LaneSizeInBitsFromFormat(vform)) { 4850f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 8: 4860f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl Memory::Write(addr, static_cast<uint8_t>(value)); 4870f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 4880f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 16: 4890f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl Memory::Write(addr, static_cast<uint16_t>(value)); 4900f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 4910f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 32: 4920f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl Memory::Write(addr, static_cast<uint32_t>(value)); 4930f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 4940f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 64: 4950f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl Memory::Write(addr, value); 4960f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 4975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 4985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 4995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 5005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl template <typename T> 5015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl T Float(int index) const { 50288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return register_.GetLane<T>(index); 5035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 5045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 5055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl template <typename T> 5065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void SetFloat(int index, T value) const { 5075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl register_.Insert(index, value); 5085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 5095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 5105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // When setting a result in a register of size less than Q, the top bits of 5115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // the Q register must be cleared. 5125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void ClearForWrite(VectorFormat vform) const { 5135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl unsigned size = RegisterSizeInBytesFromFormat(vform); 5145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (unsigned i = size; i < kQRegSizeInBytes; i++) { 5155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SetUint(kFormat16B, i, 0); 5165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 5175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 5185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 5195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Saturation state for each lane of a vector. 5205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl enum Saturation { 5215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kNotSaturated = 0, 5225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kSignedSatPositive = 1 << 0, 5235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kSignedSatNegative = 1 << 1, 5245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kSignedSatMask = kSignedSatPositive | kSignedSatNegative, 5255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kSignedSatUndefined = kSignedSatMask, 5265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kUnsignedSatPositive = 1 << 2, 5275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kUnsignedSatNegative = 1 << 3, 5285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kUnsignedSatMask = kUnsignedSatPositive | kUnsignedSatNegative, 5295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kUnsignedSatUndefined = kUnsignedSatMask 5305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl }; 5315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 5325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Getters for saturation state. 5335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Saturation GetSignedSaturation(int index) { 5345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return static_cast<Saturation>(saturated_[index] & kSignedSatMask); 5355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 5365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 5375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Saturation GetUnsignedSaturation(int index) { 5385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return static_cast<Saturation>(saturated_[index] & kUnsignedSatMask); 5395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 5405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 5415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Setters for saturation state. 5420f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl void ClearSat(int index) { saturated_[index] = kNotSaturated; } 5435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 5445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void SetSignedSat(int index, bool positive) { 5455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SetSatFlag(index, positive ? kSignedSatPositive : kSignedSatNegative); 5465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 5475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 5485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void SetUnsignedSat(int index, bool positive) { 5495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SetSatFlag(index, positive ? kUnsignedSatPositive : kUnsignedSatNegative); 5505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 5515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 5525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void SetSatFlag(int index, Saturation sat) { 5535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl saturated_[index] = static_cast<Saturation>(saturated_[index] | sat); 5545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT((sat & kUnsignedSatMask) != kUnsignedSatUndefined); 5555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT((sat & kSignedSatMask) != kSignedSatUndefined); 5565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 5575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 5585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Saturate lanes of a vector based on saturation state. 5595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister& SignedSaturate(VectorFormat vform) { 5605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 5615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Saturation sat = GetSignedSaturation(i); 5625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (sat == kSignedSatPositive) { 5635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SetInt(vform, i, MaxIntFromFormat(vform)); 5645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else if (sat == kSignedSatNegative) { 5655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SetInt(vform, i, MinIntFromFormat(vform)); 5665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 5675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 5685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return *this; 5695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 5705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 5715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister& UnsignedSaturate(VectorFormat vform) { 5725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 5735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Saturation sat = GetUnsignedSaturation(i); 5745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (sat == kUnsignedSatPositive) { 5755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SetUint(vform, i, MaxUintFromFormat(vform)); 5765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else if (sat == kUnsignedSatNegative) { 5775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SetUint(vform, i, 0); 5785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 5795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 5805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return *this; 5815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 5825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 5835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Getter for rounding state. 5840f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl bool GetRounding(int index) { return round_[index]; } 5855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 5865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Setter for rounding state. 5870f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl void SetRounding(int index, bool round) { round_[index] = round; } 5885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 5895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Round lanes of a vector based on rounding state. 5905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister& Round(VectorFormat vform) { 5915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 5925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SetInt(vform, i, Int(vform, i) + (GetRounding(i) ? 1 : 0)); 5935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 5945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return *this; 5955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 5965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 5975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Unsigned halve lanes of a vector, and use the saturation state to set the 5985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // top bit. 5995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister& Uhalve(VectorFormat vform) { 6005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 6015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t val = Uint(vform, i); 6025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SetRounding(i, (val & 1) == 1); 6035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl val >>= 1; 6045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (GetUnsignedSaturation(i) != kNotSaturated) { 6055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // If the operation causes unsigned saturation, the bit shifted into the 6065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // most significant bit must be set. 6075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl val |= (MaxUintFromFormat(vform) >> 1) + 1; 6085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 6095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SetInt(vform, i, val); 6105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 6115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return *this; 6125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 6135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 6145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Signed halve lanes of a vector, and use the carry state to set the top bit. 6155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister& Halve(VectorFormat vform) { 6165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 6175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int64_t val = Int(vform, i); 6185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SetRounding(i, (val & 1) == 1); 6195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl val >>= 1; 6205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (GetSignedSaturation(i) != kNotSaturated) { 6215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // If the operation causes signed saturation, the sign bit must be 6225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // inverted. 6235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl val ^= (MaxUintFromFormat(vform) >> 1) + 1; 6245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 6255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SetInt(vform, i, val); 6265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 6275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return *this; 6285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 6295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 6305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl private: 6315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister& register_; 6325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 6335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Allocate one saturation state entry per lane; largest register is type Q, 6345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // and lanes can be a minimum of one byte wide. 6355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Saturation saturated_[kQRegSizeInBytes]; 6365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 6375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Allocate one rounding state entry per lane. 6385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl bool round_[kQRegSizeInBytes]; 6395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl}; 6405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 641578645f14e122d2b87d907e298cda7e7d0babf1farmvixl// The proper way to initialize a simulated system register (such as NZCV) is as 642578645f14e122d2b87d907e298cda7e7d0babf1farmvixl// follows: 643578645f14e122d2b87d907e298cda7e7d0babf1farmvixl// SimSystemRegister nzcv = SimSystemRegister::DefaultValueFor(NZCV); 644578645f14e122d2b87d907e298cda7e7d0babf1farmvixlclass SimSystemRegister { 645578645f14e122d2b87d907e298cda7e7d0babf1farmvixl public: 646578645f14e122d2b87d907e298cda7e7d0babf1farmvixl // The default constructor represents a register which has no writable bits. 647578645f14e122d2b87d907e298cda7e7d0babf1farmvixl // It is not possible to set its value to anything other than 0. 6480f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl SimSystemRegister() : value_(0), write_ignore_mask_(0xffffffff) {} 649578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 65088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois uint32_t GetRawValue() const { return value_; } 65188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("GetRawValue", uint32_t RawValue() const) { 65288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return GetRawValue(); 65388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 654578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 655330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl void SetRawValue(uint32_t new_value) { 656578645f14e122d2b87d907e298cda7e7d0babf1farmvixl value_ = (value_ & write_ignore_mask_) | (new_value & ~write_ignore_mask_); 657578645f14e122d2b87d907e298cda7e7d0babf1farmvixl } 658578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 65988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois uint32_t ExtractBits(int msb, int lsb) const { 66088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ExtractUnsignedBitfield32(msb, lsb, value_); 66188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 66288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ExtractBits", uint32_t Bits(int msb, int lsb) const) { 66388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ExtractBits(msb, lsb); 664578645f14e122d2b87d907e298cda7e7d0babf1farmvixl } 665578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 66688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int32_t ExtractSignedBits(int msb, int lsb) const { 66788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ExtractSignedBitfield32(msb, lsb, value_); 66888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 66988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ExtractSignedBits", 67088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int32_t SignedBits(int msb, int lsb) const) { 67188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ExtractSignedBits(msb, lsb); 672578645f14e122d2b87d907e298cda7e7d0babf1farmvixl } 673578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 674578645f14e122d2b87d907e298cda7e7d0babf1farmvixl void SetBits(int msb, int lsb, uint32_t bits); 675578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 676578645f14e122d2b87d907e298cda7e7d0babf1farmvixl // Default system register values. 677578645f14e122d2b87d907e298cda7e7d0babf1farmvixl static SimSystemRegister DefaultValueFor(SystemRegister id); 678578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 67988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois#define DEFINE_GETTER(Name, HighBit, LowBit, Func) \ 68088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois uint32_t Get##Name() const { return this->Func(HighBit, LowBit); } \ 68188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("Get" #Name, uint32_t Name() const) { return Get##Name(); } \ 682330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl void Set##Name(uint32_t bits) { SetBits(HighBit, LowBit, bits); } 6830f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl#define DEFINE_WRITE_IGNORE_MASK(Name, Mask) \ 684578645f14e122d2b87d907e298cda7e7d0babf1farmvixl static const uint32_t Name##WriteIgnoreMask = ~static_cast<uint32_t>(Mask); 685578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 686578645f14e122d2b87d907e298cda7e7d0babf1farmvixl SYSTEM_REGISTER_FIELDS_LIST(DEFINE_GETTER, DEFINE_WRITE_IGNORE_MASK) 687578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 688578645f14e122d2b87d907e298cda7e7d0babf1farmvixl#undef DEFINE_ZERO_BITS 689578645f14e122d2b87d907e298cda7e7d0babf1farmvixl#undef DEFINE_GETTER 690578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 691578645f14e122d2b87d907e298cda7e7d0babf1farmvixl protected: 692578645f14e122d2b87d907e298cda7e7d0babf1farmvixl // Most system registers only implement a few of the bits in the word. Other 693578645f14e122d2b87d907e298cda7e7d0babf1farmvixl // bits are "read-as-zero, write-ignored". The write_ignore_mask argument 694578645f14e122d2b87d907e298cda7e7d0babf1farmvixl // describes the bits which are not modifiable. 695578645f14e122d2b87d907e298cda7e7d0babf1farmvixl SimSystemRegister(uint32_t value, uint32_t write_ignore_mask) 6960f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl : value_(value), write_ignore_mask_(write_ignore_mask) {} 697578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 698578645f14e122d2b87d907e298cda7e7d0babf1farmvixl uint32_t value_; 699578645f14e122d2b87d907e298cda7e7d0babf1farmvixl uint32_t write_ignore_mask_; 700578645f14e122d2b87d907e298cda7e7d0babf1farmvixl}; 701578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 702578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 7034a102baf640077d6794c0b33bb976f94b86c532barmvixlclass SimExclusiveLocalMonitor { 7044a102baf640077d6794c0b33bb976f94b86c532barmvixl public: 7054a102baf640077d6794c0b33bb976f94b86c532barmvixl SimExclusiveLocalMonitor() : kSkipClearProbability(8), seed_(0x87654321) { 7064a102baf640077d6794c0b33bb976f94b86c532barmvixl Clear(); 7074a102baf640077d6794c0b33bb976f94b86c532barmvixl } 7084a102baf640077d6794c0b33bb976f94b86c532barmvixl 7094a102baf640077d6794c0b33bb976f94b86c532barmvixl // Clear the exclusive monitor (like clrex). 7104a102baf640077d6794c0b33bb976f94b86c532barmvixl void Clear() { 7114a102baf640077d6794c0b33bb976f94b86c532barmvixl address_ = 0; 7124a102baf640077d6794c0b33bb976f94b86c532barmvixl size_ = 0; 7134a102baf640077d6794c0b33bb976f94b86c532barmvixl } 7144a102baf640077d6794c0b33bb976f94b86c532barmvixl 7154a102baf640077d6794c0b33bb976f94b86c532barmvixl // Clear the exclusive monitor most of the time. 7164a102baf640077d6794c0b33bb976f94b86c532barmvixl void MaybeClear() { 7174a102baf640077d6794c0b33bb976f94b86c532barmvixl if ((seed_ % kSkipClearProbability) != 0) { 7184a102baf640077d6794c0b33bb976f94b86c532barmvixl Clear(); 7194a102baf640077d6794c0b33bb976f94b86c532barmvixl } 7204a102baf640077d6794c0b33bb976f94b86c532barmvixl 7214a102baf640077d6794c0b33bb976f94b86c532barmvixl // Advance seed_ using a simple linear congruential generator. 7224a102baf640077d6794c0b33bb976f94b86c532barmvixl seed_ = (seed_ * 48271) % 2147483647; 7234a102baf640077d6794c0b33bb976f94b86c532barmvixl } 7244a102baf640077d6794c0b33bb976f94b86c532barmvixl 7254a102baf640077d6794c0b33bb976f94b86c532barmvixl // Mark the address range for exclusive access (like load-exclusive). 726330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl void MarkExclusive(uint64_t address, size_t size) { 727330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl address_ = address; 7284a102baf640077d6794c0b33bb976f94b86c532barmvixl size_ = size; 7294a102baf640077d6794c0b33bb976f94b86c532barmvixl } 7304a102baf640077d6794c0b33bb976f94b86c532barmvixl 7314a102baf640077d6794c0b33bb976f94b86c532barmvixl // Return true if the address range is marked (like store-exclusive). 7324a102baf640077d6794c0b33bb976f94b86c532barmvixl // This helper doesn't implicitly clear the monitor. 733330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl bool IsExclusive(uint64_t address, size_t size) { 7344a102baf640077d6794c0b33bb976f94b86c532barmvixl VIXL_ASSERT(size > 0); 7354a102baf640077d6794c0b33bb976f94b86c532barmvixl // Be pedantic: Require both the address and the size to match. 736330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl return (size == size_) && (address == address_); 7374a102baf640077d6794c0b33bb976f94b86c532barmvixl } 7384a102baf640077d6794c0b33bb976f94b86c532barmvixl 7394a102baf640077d6794c0b33bb976f94b86c532barmvixl private: 740330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl uint64_t address_; 7414a102baf640077d6794c0b33bb976f94b86c532barmvixl size_t size_; 7424a102baf640077d6794c0b33bb976f94b86c532barmvixl 7434a102baf640077d6794c0b33bb976f94b86c532barmvixl const int kSkipClearProbability; 7444a102baf640077d6794c0b33bb976f94b86c532barmvixl uint32_t seed_; 7454a102baf640077d6794c0b33bb976f94b86c532barmvixl}; 7464a102baf640077d6794c0b33bb976f94b86c532barmvixl 7474a102baf640077d6794c0b33bb976f94b86c532barmvixl 7484a102baf640077d6794c0b33bb976f94b86c532barmvixl// We can't accurate simulate the global monitor since it depends on external 7494a102baf640077d6794c0b33bb976f94b86c532barmvixl// influences. Instead, this implementation occasionally causes accesses to 7504a102baf640077d6794c0b33bb976f94b86c532barmvixl// fail, according to kPassProbability. 7514a102baf640077d6794c0b33bb976f94b86c532barmvixlclass SimExclusiveGlobalMonitor { 7524a102baf640077d6794c0b33bb976f94b86c532barmvixl public: 7534a102baf640077d6794c0b33bb976f94b86c532barmvixl SimExclusiveGlobalMonitor() : kPassProbability(8), seed_(0x87654321) {} 7544a102baf640077d6794c0b33bb976f94b86c532barmvixl 755330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl bool IsExclusive(uint64_t address, size_t size) { 756db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl USE(address, size); 7574a102baf640077d6794c0b33bb976f94b86c532barmvixl 7584a102baf640077d6794c0b33bb976f94b86c532barmvixl bool pass = (seed_ % kPassProbability) != 0; 7594a102baf640077d6794c0b33bb976f94b86c532barmvixl // Advance seed_ using a simple linear congruential generator. 7604a102baf640077d6794c0b33bb976f94b86c532barmvixl seed_ = (seed_ * 48271) % 2147483647; 7614a102baf640077d6794c0b33bb976f94b86c532barmvixl return pass; 7624a102baf640077d6794c0b33bb976f94b86c532barmvixl } 7634a102baf640077d6794c0b33bb976f94b86c532barmvixl 7644a102baf640077d6794c0b33bb976f94b86c532barmvixl private: 7654a102baf640077d6794c0b33bb976f94b86c532barmvixl const int kPassProbability; 7664a102baf640077d6794c0b33bb976f94b86c532barmvixl uint32_t seed_; 7674a102baf640077d6794c0b33bb976f94b86c532barmvixl}; 7684a102baf640077d6794c0b33bb976f94b86c532barmvixl 7694a102baf640077d6794c0b33bb976f94b86c532barmvixl 770ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlclass Simulator : public DecoderVisitor { 771ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl public: 772ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl explicit Simulator(Decoder* decoder, FILE* stream = stdout); 773ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl ~Simulator(); 774ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 775ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl void ResetState(); 776ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 777ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // Run the simulator. 778ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl virtual void Run(); 779c68cb64496485710cdb5b8480f8fee287058c93farmvixl void RunFrom(const Instruction* first); 780ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 7810f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl // Execution ends when the PC hits this address. 7820f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl static const Instruction* kEndOfSimAddress; 7830f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl 784ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // Simulation helpers. 78588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois const Instruction* ReadPc() const { return pc_; } 78688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadPc", const Instruction* pc() const) { return ReadPc(); } 78788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois 78888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void WritePc(const Instruction* new_pc) { 7895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl pc_ = Memory::AddressUntag(new_pc); 790ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl pc_modified_ = true; 791ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 79288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("WritePc", void set_pc(const Instruction* new_pc)) { 79388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return WritePc(new_pc); 79488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 795ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 79688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void IncrementPc() { 797ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl if (!pc_modified_) { 79888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois pc_ = pc_->GetNextInstruction(); 799ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 800ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 80188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("IncrementPc", void increment_pc()) { IncrementPc(); } 802ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 803330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl void ExecuteInstruction() { 804ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // The program counter should always be aligned. 805b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT(IsWordAligned(pc_)); 8060f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl pc_modified_ = false; 807ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl decoder_->Decode(pc_); 80888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois IncrementPc(); 8090f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogAllWrittenRegisters(); 810ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 811ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 8120f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl// Declare all Visitor functions. 8130f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl#define DECLARE(A) virtual void Visit##A(const Instruction* instr); 814684cd2a7f5845539b58d0da7e012e39df49ceff0armvixl VISITOR_LIST_THAT_RETURN(DECLARE) 8150f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl#undef DECLARE 816ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 8170f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl#define DECLARE(A) \ 8180f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl VIXL_DEBUG_NO_RETURN virtual void Visit##A(const Instruction* instr); 819684cd2a7f5845539b58d0da7e012e39df49ceff0armvixl VISITOR_LIST_THAT_DONT_RETURN(DECLARE) 8200f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl#undef DECLARE 821684cd2a7f5845539b58d0da7e012e39df49ceff0armvixl 822684cd2a7f5845539b58d0da7e012e39df49ceff0armvixl 8234a102baf640077d6794c0b33bb976f94b86c532barmvixl // Integer register accessors. 824f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl 8254a102baf640077d6794c0b33bb976f94b86c532barmvixl // Basic accessor: Read the register as the specified type. 8260f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl template <typename T> 82788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois T ReadRegister(unsigned code, Reg31Mode r31mode = Reg31IsZeroRegister) const { 828868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames VIXL_ASSERT( 829868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames code < kNumberOfRegisters || 830868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames ((r31mode == Reg31IsZeroRegister) && (code == kSPRegInternalCode))); 831ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl if ((code == 31) && (r31mode == Reg31IsZeroRegister)) { 832f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl T result; 833f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl memset(&result, 0, sizeof(result)); 834f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl return result; 835ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 836868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames if ((r31mode == Reg31IsZeroRegister) && (code == kSPRegInternalCode)) { 837868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames code = 31; 838868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames } 8394a102baf640077d6794c0b33bb976f94b86c532barmvixl return registers_[code].Get<T>(); 840f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl } 84188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois template <typename T> 84288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadRegister", 84388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois T reg(unsigned code, Reg31Mode r31mode = Reg31IsZeroRegister) 84488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois const) { 84588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadRegister<T>(code, r31mode); 84688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 847f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl 84888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois // Common specialized accessors for the ReadRegister() template. 84988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int32_t ReadWRegister(unsigned code, 85088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois Reg31Mode r31mode = Reg31IsZeroRegister) const { 85188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadRegister<int32_t>(code, r31mode); 85288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 85388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadWRegister", 85488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int32_t wreg(unsigned code, 85588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois Reg31Mode r31mode = Reg31IsZeroRegister) const) { 85688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadWRegister(code, r31mode); 857ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 858ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 85988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int64_t ReadXRegister(unsigned code, 86088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois Reg31Mode r31mode = Reg31IsZeroRegister) const { 86188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadRegister<int64_t>(code, r31mode); 86288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 86388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadXRegister", 86488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int64_t xreg(unsigned code, 86588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois Reg31Mode r31mode = Reg31IsZeroRegister) const) { 86688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadXRegister(code, r31mode); 867f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl } 868f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl 8694a102baf640077d6794c0b33bb976f94b86c532barmvixl // As above, with parameterized size and return type. The value is 8704a102baf640077d6794c0b33bb976f94b86c532barmvixl // either zero-extended or truncated to fit, as required. 8710f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl template <typename T> 87288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois T ReadRegister(unsigned size, 87388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois unsigned code, 87488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois Reg31Mode r31mode = Reg31IsZeroRegister) const { 8754a102baf640077d6794c0b33bb976f94b86c532barmvixl uint64_t raw; 8764a102baf640077d6794c0b33bb976f94b86c532barmvixl switch (size) { 8770f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case kWRegSize: 87888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois raw = ReadRegister<uint32_t>(code, r31mode); 8790f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 8800f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case kXRegSize: 88188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois raw = ReadRegister<uint64_t>(code, r31mode); 8820f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 8834a102baf640077d6794c0b33bb976f94b86c532barmvixl default: 8844a102baf640077d6794c0b33bb976f94b86c532barmvixl VIXL_UNREACHABLE(); 8854a102baf640077d6794c0b33bb976f94b86c532barmvixl return 0; 8864a102baf640077d6794c0b33bb976f94b86c532barmvixl } 8874a102baf640077d6794c0b33bb976f94b86c532barmvixl 8884a102baf640077d6794c0b33bb976f94b86c532barmvixl T result; 8894a102baf640077d6794c0b33bb976f94b86c532barmvixl VIXL_STATIC_ASSERT(sizeof(result) <= sizeof(raw)); 8904a102baf640077d6794c0b33bb976f94b86c532barmvixl // Copy the result and truncate to fit. This assumes a little-endian host. 8914a102baf640077d6794c0b33bb976f94b86c532barmvixl memcpy(&result, &raw, sizeof(result)); 8924a102baf640077d6794c0b33bb976f94b86c532barmvixl return result; 8934a102baf640077d6794c0b33bb976f94b86c532barmvixl } 89488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois template <typename T> 89588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadRegister", 89688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois T reg(unsigned size, 89788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois unsigned code, 89888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois Reg31Mode r31mode = Reg31IsZeroRegister) const) { 89988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadRegister<T>(size, code, r31mode); 90088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 9014a102baf640077d6794c0b33bb976f94b86c532barmvixl 9024a102baf640077d6794c0b33bb976f94b86c532barmvixl // Use int64_t by default if T is not specified. 90388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int64_t ReadRegister(unsigned size, 90488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois unsigned code, 90588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois Reg31Mode r31mode = Reg31IsZeroRegister) const { 90688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadRegister<int64_t>(size, code, r31mode); 90788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 90888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadRegister", 90988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int64_t reg(unsigned size, 91088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois unsigned code, 91188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois Reg31Mode r31mode = Reg31IsZeroRegister) const) { 91288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadRegister(size, code, r31mode); 913f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl } 914f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl 9150f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl enum RegLogMode { LogRegWrites, NoRegLog }; 916330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl 917330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl // Write 'value' into an integer register. The value is zero-extended. This 918330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl // behaviour matches AArch64 register writes. 9190f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl template <typename T> 92088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void WriteRegister(unsigned code, 92188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois T value, 92288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites, 92388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois Reg31Mode r31mode = Reg31IsZeroRegister) { 9244a102baf640077d6794c0b33bb976f94b86c532barmvixl VIXL_STATIC_ASSERT((sizeof(T) == kWRegSizeInBytes) || 9254a102baf640077d6794c0b33bb976f94b86c532barmvixl (sizeof(T) == kXRegSizeInBytes)); 926868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames VIXL_ASSERT( 927868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames code < kNumberOfRegisters || 928868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames ((r31mode == Reg31IsZeroRegister) && (code == kSPRegInternalCode))); 929f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl 930ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl if ((code == 31) && (r31mode == Reg31IsZeroRegister)) { 931f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl return; 932ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 933ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 934868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames if ((r31mode == Reg31IsZeroRegister) && (code == kSPRegInternalCode)) { 935868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames code = 31; 936868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames } 937868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames 93888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois registers_[code].Write(value); 939330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl 940330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl if (log_mode == LogRegWrites) LogRegister(code, r31mode); 941ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 94288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois template <typename T> 94388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("WriteRegister", 94488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void set_reg(unsigned code, 94588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois T value, 94688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites, 94788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois Reg31Mode r31mode = Reg31IsZeroRegister)) { 94888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteRegister<T>(code, value, log_mode, r31mode); 94988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 950ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 951f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl // Common specialized accessors for the set_reg() template. 95288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void WriteWRegister(unsigned code, 95388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int32_t value, 95488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites, 95588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois Reg31Mode r31mode = Reg31IsZeroRegister) { 95688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteRegister(code, value, log_mode, r31mode); 95788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 95888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("WriteWRegister", 95988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void set_wreg(unsigned code, 96088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int32_t value, 96188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites, 96288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois Reg31Mode r31mode = Reg31IsZeroRegister)) { 96388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteWRegister(code, value, log_mode, r31mode); 964ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 965ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 96688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void WriteXRegister(unsigned code, 96788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int64_t value, 96888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites, 96988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois Reg31Mode r31mode = Reg31IsZeroRegister) { 97088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteRegister(code, value, log_mode, r31mode); 97188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 97288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("WriteXRegister", 97388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void set_xreg(unsigned code, 97488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int64_t value, 97588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites, 97688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois Reg31Mode r31mode = Reg31IsZeroRegister)) { 97788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteXRegister(code, value, log_mode, r31mode); 9784a102baf640077d6794c0b33bb976f94b86c532barmvixl } 9794a102baf640077d6794c0b33bb976f94b86c532barmvixl 9804a102baf640077d6794c0b33bb976f94b86c532barmvixl // As above, with parameterized size and type. The value is either 9814a102baf640077d6794c0b33bb976f94b86c532barmvixl // zero-extended or truncated to fit, as required. 9820f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl template <typename T> 98388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void WriteRegister(unsigned size, 98488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois unsigned code, 98588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois T value, 98688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites, 98788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois Reg31Mode r31mode = Reg31IsZeroRegister) { 9884a102baf640077d6794c0b33bb976f94b86c532barmvixl // Zero-extend the input. 9894a102baf640077d6794c0b33bb976f94b86c532barmvixl uint64_t raw = 0; 9904a102baf640077d6794c0b33bb976f94b86c532barmvixl VIXL_STATIC_ASSERT(sizeof(value) <= sizeof(raw)); 9914a102baf640077d6794c0b33bb976f94b86c532barmvixl memcpy(&raw, &value, sizeof(value)); 9924a102baf640077d6794c0b33bb976f94b86c532barmvixl 9934a102baf640077d6794c0b33bb976f94b86c532barmvixl // Write (and possibly truncate) the value. 9944a102baf640077d6794c0b33bb976f94b86c532barmvixl switch (size) { 995db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl case kWRegSize: 99688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteRegister(code, static_cast<uint32_t>(raw), log_mode, r31mode); 997db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl break; 998db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl case kXRegSize: 99988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteRegister(code, raw, log_mode, r31mode); 1000db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl break; 10014a102baf640077d6794c0b33bb976f94b86c532barmvixl default: 10024a102baf640077d6794c0b33bb976f94b86c532barmvixl VIXL_UNREACHABLE(); 10034a102baf640077d6794c0b33bb976f94b86c532barmvixl return; 10044a102baf640077d6794c0b33bb976f94b86c532barmvixl } 1005ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 100688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois template <typename T> 100788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("WriteRegister", 100888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void set_reg(unsigned size, 100988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois unsigned code, 101088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois T value, 101188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites, 101288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois Reg31Mode r31mode = Reg31IsZeroRegister)) { 101388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteRegister(size, code, value, log_mode, r31mode); 101488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 1015ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 10164a102baf640077d6794c0b33bb976f94b86c532barmvixl // Common specialized accessors for the set_reg() template. 10174a102baf640077d6794c0b33bb976f94b86c532barmvixl 1018f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl // Commonly-used special cases. 10190f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl template <typename T> 102088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void WriteLr(T value) { 102188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteRegister(kLinkRegCode, value); 102288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 102388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois template <typename T> 102488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("WriteLr", void set_lr(T value)) { 102588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteLr(value); 1026ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 1027ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 10280f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl template <typename T> 102988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void WriteSp(T value) { 103088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteRegister(31, value, LogRegWrites, Reg31IsStackPointer); 103188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 103288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois template <typename T> 103388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("WriteSp", void set_sp(T value)) { 103488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteSp(value); 1035f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl } 1036ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 10375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Vector register accessors. 10385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // These are equivalent to the integer register accessors, but for vector 10394a102baf640077d6794c0b33bb976f94b86c532barmvixl // registers. 1040f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl 10415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // A structure for representing a 128-bit Q register. 10420f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl struct qreg_t { 10430f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl uint8_t val[kQRegSizeInBytes]; 10440f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl }; 10455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 10465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Basic accessor: read the register as the specified type. 10470f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl template <typename T> 104888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois T ReadVRegister(unsigned code) const { 10490f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl VIXL_STATIC_ASSERT( 10500f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl (sizeof(T) == kBRegSizeInBytes) || (sizeof(T) == kHRegSizeInBytes) || 10510f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl (sizeof(T) == kSRegSizeInBytes) || (sizeof(T) == kDRegSizeInBytes) || 10520f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl (sizeof(T) == kQRegSizeInBytes)); 10535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(code < kNumberOfVRegisters); 10545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 10555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return vregisters_[code].Get<T>(); 10565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 105788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois template <typename T> 105888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadVRegister", T vreg(unsigned code) const) { 105988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadVRegister<T>(code); 106088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 10615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 10625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Common specialized accessors for the vreg() template. 106388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int8_t ReadBRegister(unsigned code) const { 106488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadVRegister<int8_t>(code); 106588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 106688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadBRegister", int8_t breg(unsigned code) const) { 106788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadBRegister(code); 106888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 10694a102baf640077d6794c0b33bb976f94b86c532barmvixl 107088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int16_t ReadHRegister(unsigned code) const { 107188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadVRegister<int16_t>(code); 107288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 107388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadHRegister", int16_t hreg(unsigned code) const) { 107488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadHRegister(code); 107588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 1076ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 107788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois float ReadSRegister(unsigned code) const { 107888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadVRegister<float>(code); 107988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 108088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadSRegister", float sreg(unsigned code) const) { 108188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadSRegister(code); 108288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 1083ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 108488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois uint32_t ReadSRegisterBits(unsigned code) const { 108588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadVRegister<uint32_t>(code); 108688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 108788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadSRegisterBits", 108888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois uint32_t sreg_bits(unsigned code) const) { 108988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadSRegisterBits(code); 109088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 1091ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 109288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois double ReadDRegister(unsigned code) const { 109388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadVRegister<double>(code); 109488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 109588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadDRegister", double dreg(unsigned code) const) { 109688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadDRegister(code); 109788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 1098ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 109988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois uint64_t ReadDRegisterBits(unsigned code) const { 110088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadVRegister<uint64_t>(code); 110188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 110288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadDRegisterBits", 110388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois uint64_t dreg_bits(unsigned code) const) { 110488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadDRegisterBits(code); 110588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 11065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 110788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois qreg_t ReadQRegister(unsigned code) const { 110888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadVRegister<qreg_t>(code); 110988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 111088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadQRegister", qreg_t qreg(unsigned code) const) { 111188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadQRegister(code); 111288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 1113ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 11144a102baf640077d6794c0b33bb976f94b86c532barmvixl // As above, with parameterized size and return type. The value is 11154a102baf640077d6794c0b33bb976f94b86c532barmvixl // either zero-extended or truncated to fit, as required. 11160f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl template <typename T> 111788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois T ReadVRegister(unsigned size, unsigned code) const { 11185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t raw = 0; 11195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl T result; 11205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 1121ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl switch (size) { 11220f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case kSRegSize: 112388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois raw = ReadVRegister<uint32_t>(code); 11240f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 11250f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case kDRegSize: 112688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois raw = ReadVRegister<uint64_t>(code); 11270f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 1128f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl default: 1129b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_UNREACHABLE(); 11304a102baf640077d6794c0b33bb976f94b86c532barmvixl break; 1131ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 11324a102baf640077d6794c0b33bb976f94b86c532barmvixl 11334a102baf640077d6794c0b33bb976f94b86c532barmvixl VIXL_STATIC_ASSERT(sizeof(result) <= sizeof(raw)); 11344a102baf640077d6794c0b33bb976f94b86c532barmvixl // Copy the result and truncate to fit. This assumes a little-endian host. 11354a102baf640077d6794c0b33bb976f94b86c532barmvixl memcpy(&result, &raw, sizeof(result)); 11364a102baf640077d6794c0b33bb976f94b86c532barmvixl return result; 1137ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 113888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois template <typename T> 113988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadVRegister", T vreg(unsigned size, unsigned code) const) { 114088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadVRegister<T>(size, code); 114188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 1142ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 114388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois SimVRegister& ReadVRegister(unsigned code) { return vregisters_[code]; } 114488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadVRegister", SimVRegister& vreg(unsigned code)) { 114588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadVRegister(code); 114688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 11475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 11484a102baf640077d6794c0b33bb976f94b86c532barmvixl // Basic accessor: Write the specified value. 11490f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl template <typename T> 115088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void WriteVRegister(unsigned code, 115188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois T value, 115288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites) { 11535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_STATIC_ASSERT((sizeof(value) == kBRegSizeInBytes) || 11545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl (sizeof(value) == kHRegSizeInBytes) || 11555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl (sizeof(value) == kSRegSizeInBytes) || 11565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl (sizeof(value) == kDRegSizeInBytes) || 11575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl (sizeof(value) == kQRegSizeInBytes)); 11585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(code < kNumberOfVRegisters); 115988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois vregisters_[code].Write(value); 1160330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl 1161330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl if (log_mode == LogRegWrites) { 11625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogVRegister(code, GetPrintRegisterFormat(value)); 1163330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl } 1164ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 116588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois template <typename T> 116688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("WriteVRegister", 116788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void set_vreg(unsigned code, 116888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois T value, 116988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites)) { 117088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteVRegister(code, value, log_mode); 117188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 1172ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 117388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois // Common specialized accessors for the WriteVRegister() template. 117488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void WriteBRegister(unsigned code, 117588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int8_t value, 117688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites) { 117788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteVRegister(code, value, log_mode); 117888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 117988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("WriteBRegister", 118088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void set_breg(unsigned code, 118188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int8_t value, 118288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites)) { 118388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return WriteBRegister(code, value, log_mode); 11845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 11855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 118688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void WriteHRegister(unsigned code, 118788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int16_t value, 118888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites) { 118988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteVRegister(code, value, log_mode); 119088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 119188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("WriteHRegister", 119288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void set_hreg(unsigned code, 119388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int16_t value, 119488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites)) { 119588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return WriteHRegister(code, value, log_mode); 11965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 11975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 119888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void WriteSRegister(unsigned code, 119988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois float value, 120088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites) { 120188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteVRegister(code, value, log_mode); 120288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 120388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("WriteSRegister", 120488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void set_sreg(unsigned code, 120588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois float value, 120688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites)) { 120788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteSRegister(code, value, log_mode); 1208ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 1209ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 121088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void WriteSRegisterBits(unsigned code, 121188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois uint32_t value, 121288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites) { 121388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteVRegister(code, value, log_mode); 121488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 121588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("WriteSRegisterBits", 121688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void set_sreg_bits(unsigned code, 121788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois uint32_t value, 121888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites)) { 121988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteSRegisterBits(code, value, log_mode); 1220ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 1221ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 122288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void WriteDRegister(unsigned code, 122388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois double value, 122488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites) { 122588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteVRegister(code, value, log_mode); 122688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 122788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("WriteDRegister", 122888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void set_dreg(unsigned code, 122988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois double value, 123088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites)) { 123188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteDRegister(code, value, log_mode); 1232ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 1233ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 123488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void WriteDRegisterBits(unsigned code, 123588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois uint64_t value, 123688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites) { 123788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteVRegister(code, value, log_mode); 123888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 123988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("WriteDRegisterBits", 124088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void set_dreg_bits(unsigned code, 124188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois uint64_t value, 124288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites)) { 124388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteDRegisterBits(code, value, log_mode); 12445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 12455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 124688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void WriteQRegister(unsigned code, 124788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois qreg_t value, 124888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites) { 124988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteVRegister(code, value, log_mode); 1250ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 125188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("WriteQRegister", 125288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void set_qreg(unsigned code, 125388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois qreg_t value, 125488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites)) { 125588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteQRegister(code, value, log_mode); 125688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 125788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois 1258868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames template <typename T> 1259868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames T ReadRegister(Register reg) const { 1260868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames return ReadRegister<T>(reg.GetCode(), Reg31IsZeroRegister); 1261868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames } 1262868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames 1263868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames template <typename T> 1264868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames void WriteRegister(Register reg, 1265868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames T value, 1266868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames RegLogMode log_mode = LogRegWrites) { 1267868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames WriteRegister<T>(reg.GetCode(), value, log_mode, Reg31IsZeroRegister); 1268868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames } 1269868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames 1270868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames template <typename T> 1271868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames T ReadVRegister(VRegister vreg) const { 1272868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames return ReadVRegister<T>(vreg.GetCode()); 1273868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames } 1274868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames 1275868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames template <typename T> 1276868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames void WriteVRegister(VRegister vreg, 1277868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames T value, 1278868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames RegLogMode log_mode = LogRegWrites) { 1279868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames WriteVRegister<T>(vreg.GetCode(), value, log_mode); 1280868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames } 1281868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames 1282868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames template <typename T> 1283868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames T ReadCPURegister(CPURegister reg) const { 1284868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames if (reg.IsVRegister()) { 1285868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames return ReadVRegister<T>(VRegister(reg)); 1286868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames } else { 1287868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames return ReadRegister<T>(Register(reg)); 1288868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames } 1289868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames } 1290868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames 1291868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames template <typename T> 1292868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames void WriteCPURegister(CPURegister reg, 1293868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames T value, 1294868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames RegLogMode log_mode = LogRegWrites) { 1295868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames if (reg.IsVRegister()) { 1296868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames WriteVRegister<T>(VRegister(reg), value, log_mode); 1297868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames } else { 1298868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames WriteRegister<T>(Register(reg), value, log_mode); 1299868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames } 1300868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames } 1301868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames 1302868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames uint64_t ComputeMemOperandAddress(const MemOperand& mem_op) const; 1303868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames 1304868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames template <typename T> 1305868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames T ReadGenericOperand(GenericOperand operand) const { 1306868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames if (operand.IsCPURegister()) { 1307868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames return ReadCPURegister<T>(operand.GetCPURegister()); 1308868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames } else { 1309868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames VIXL_ASSERT(operand.IsMemOperand()); 1310868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames return Memory::Read<T>(ComputeMemOperandAddress(operand.GetMemOperand())); 1311868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames } 1312868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames } 1313868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames 1314868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames template <typename T> 1315868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames void WriteGenericOperand(GenericOperand operand, 1316868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames T value, 1317868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames RegLogMode log_mode = LogRegWrites) { 1318868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames if (operand.IsCPURegister()) { 1319868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames WriteCPURegister<T>(operand.GetCPURegister(), value, log_mode); 1320868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames } else { 1321868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames VIXL_ASSERT(operand.IsMemOperand()); 1322868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames Memory::Write(ComputeMemOperandAddress(operand.GetMemOperand()), value); 1323868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames } 1324868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames } 1325868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames 132688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois bool ReadN() const { return nzcv_.GetN() != 0; } 132788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadN", bool N() const) { return ReadN(); } 1328ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 132988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois bool ReadZ() const { return nzcv_.GetZ() != 0; } 133088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadZ", bool Z() const) { return ReadZ(); } 133188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois 133288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois bool ReadC() const { return nzcv_.GetC() != 0; } 133388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadC", bool C() const) { return ReadC(); } 133488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois 133588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois bool ReadV() const { return nzcv_.GetV() != 0; } 133688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadV", bool V() const) { return ReadV(); } 133788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois 133888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois SimSystemRegister& ReadNzcv() { return nzcv_; } 133988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadNzcv", SimSystemRegister& nzcv()) { return ReadNzcv(); } 1340578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 13415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // TODO: Find a way to make the fpcr_ members return the proper types, so 13425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // these accessors are not necessary. 134388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois FPRounding ReadRMode() const { 134488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return static_cast<FPRounding>(fpcr_.GetRMode()); 134588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 134688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadRMode", FPRounding RMode()) { return ReadRMode(); } 134788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois 134888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois bool ReadDN() const { return fpcr_.GetDN() != 0; } 134988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadDN", bool DN()) { return ReadDN(); } 135088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois 135188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois SimSystemRegister& ReadFpcr() { return fpcr_; } 135288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadFpcr", SimSystemRegister& fpcr()) { return ReadFpcr(); } 1353ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 13545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Specify relevant register formats for Print(V)Register and related helpers. 13555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl enum PrintRegisterFormat { 13565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // The lane size. 13575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintRegLaneSizeB = 0 << 0, 13585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintRegLaneSizeH = 1 << 0, 13595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintRegLaneSizeS = 2 << 0, 13605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintRegLaneSizeW = kPrintRegLaneSizeS, 13615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintRegLaneSizeD = 3 << 0, 13625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintRegLaneSizeX = kPrintRegLaneSizeD, 13635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintRegLaneSizeQ = 4 << 0, 13645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 13655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintRegLaneSizeOffset = 0, 13665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintRegLaneSizeMask = 7 << 0, 13675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 13685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // The lane count. 13695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintRegAsScalar = 0, 13705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintRegAsDVector = 1 << 3, 13715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintRegAsQVector = 2 << 3, 13725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 13735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintRegAsVectorMask = 3 << 3, 13745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 13755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Indicate floating-point format lanes. (This flag is only supported for S- 13765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // and D-sized lanes.) 13775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintRegAsFP = 1 << 5, 13785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 13795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Supported combinations. 13805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 13815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintXReg = kPrintRegLaneSizeX | kPrintRegAsScalar, 13825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintWReg = kPrintRegLaneSizeW | kPrintRegAsScalar, 13835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintSReg = kPrintRegLaneSizeS | kPrintRegAsScalar | kPrintRegAsFP, 13845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintDReg = kPrintRegLaneSizeD | kPrintRegAsScalar | kPrintRegAsFP, 13855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 13865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintReg1B = kPrintRegLaneSizeB | kPrintRegAsScalar, 13875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintReg8B = kPrintRegLaneSizeB | kPrintRegAsDVector, 13885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintReg16B = kPrintRegLaneSizeB | kPrintRegAsQVector, 13895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintReg1H = kPrintRegLaneSizeH | kPrintRegAsScalar, 13905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintReg4H = kPrintRegLaneSizeH | kPrintRegAsDVector, 13915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintReg8H = kPrintRegLaneSizeH | kPrintRegAsQVector, 13925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintReg1S = kPrintRegLaneSizeS | kPrintRegAsScalar, 13935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintReg2S = kPrintRegLaneSizeS | kPrintRegAsDVector, 13945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintReg4S = kPrintRegLaneSizeS | kPrintRegAsQVector, 13955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintReg1SFP = kPrintRegLaneSizeS | kPrintRegAsScalar | kPrintRegAsFP, 13965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintReg2SFP = kPrintRegLaneSizeS | kPrintRegAsDVector | kPrintRegAsFP, 13975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintReg4SFP = kPrintRegLaneSizeS | kPrintRegAsQVector | kPrintRegAsFP, 13985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintReg1D = kPrintRegLaneSizeD | kPrintRegAsScalar, 13995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintReg2D = kPrintRegLaneSizeD | kPrintRegAsQVector, 14005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintReg1DFP = kPrintRegLaneSizeD | kPrintRegAsScalar | kPrintRegAsFP, 14015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintReg2DFP = kPrintRegLaneSizeD | kPrintRegAsQVector | kPrintRegAsFP, 14025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintReg1Q = kPrintRegLaneSizeQ | kPrintRegAsScalar 14035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl }; 14045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 14055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl unsigned GetPrintRegLaneSizeInBytesLog2(PrintRegisterFormat format) { 14065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return (format & kPrintRegLaneSizeMask) >> kPrintRegLaneSizeOffset; 14075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 14085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 14095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl unsigned GetPrintRegLaneSizeInBytes(PrintRegisterFormat format) { 14105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return 1 << GetPrintRegLaneSizeInBytesLog2(format); 14115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 14125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 14135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl unsigned GetPrintRegSizeInBytesLog2(PrintRegisterFormat format) { 14145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (format & kPrintRegAsDVector) return kDRegSizeInBytesLog2; 14155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (format & kPrintRegAsQVector) return kQRegSizeInBytesLog2; 14165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 14175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Scalar types. 14185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return GetPrintRegLaneSizeInBytesLog2(format); 14195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 14205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 14215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl unsigned GetPrintRegSizeInBytes(PrintRegisterFormat format) { 14225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return 1 << GetPrintRegSizeInBytesLog2(format); 14235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 14245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 14255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl unsigned GetPrintRegLaneCount(PrintRegisterFormat format) { 14265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl unsigned reg_size_log2 = GetPrintRegSizeInBytesLog2(format); 14275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl unsigned lane_size_log2 = GetPrintRegLaneSizeInBytesLog2(format); 14285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(reg_size_log2 >= lane_size_log2); 14295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return 1 << (reg_size_log2 - lane_size_log2); 14305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 14315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 14325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl PrintRegisterFormat GetPrintRegisterFormatForSize(unsigned reg_size, 14335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl unsigned lane_size); 14345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 14355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl PrintRegisterFormat GetPrintRegisterFormatForSize(unsigned size) { 14365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return GetPrintRegisterFormatForSize(size, size); 14375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 14385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 14395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl PrintRegisterFormat GetPrintRegisterFormatForSizeFP(unsigned size) { 14405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl switch (size) { 14410f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl default: 14420f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl VIXL_UNREACHABLE(); 14430f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl return kPrintDReg; 14440f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case kDRegSizeInBytes: 14450f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl return kPrintDReg; 14460f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case kSRegSizeInBytes: 14470f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl return kPrintSReg; 14485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 14495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 14505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 14515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl PrintRegisterFormat GetPrintRegisterFormatTryFP(PrintRegisterFormat format) { 14525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if ((GetPrintRegLaneSizeInBytes(format) == kSRegSizeInBytes) || 14535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl (GetPrintRegLaneSizeInBytes(format) == kDRegSizeInBytes)) { 14545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return static_cast<PrintRegisterFormat>(format | kPrintRegAsFP); 14555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 14565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return format; 14575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 14585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 14590f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl template <typename T> 14605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl PrintRegisterFormat GetPrintRegisterFormat(T value) { 14615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return GetPrintRegisterFormatForSize(sizeof(value)); 14625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 14635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 14645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl PrintRegisterFormat GetPrintRegisterFormat(double value) { 14655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_STATIC_ASSERT(sizeof(value) == kDRegSizeInBytes); 14665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return GetPrintRegisterFormatForSizeFP(sizeof(value)); 14675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 14685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 14695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl PrintRegisterFormat GetPrintRegisterFormat(float value) { 14705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_STATIC_ASSERT(sizeof(value) == kSRegSizeInBytes); 14715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return GetPrintRegisterFormatForSizeFP(sizeof(value)); 14725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 14735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 14745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl PrintRegisterFormat GetPrintRegisterFormat(VectorFormat vform); 14750f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl PrintRegisterFormat GetPrintRegisterFormatFP(VectorFormat vform); 14765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 1477330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl // Print all registers of the specified types. 1478330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl void PrintRegisters(); 14795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void PrintVRegisters(); 1480330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl void PrintSystemRegisters(); 1481330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl 14825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // As above, but only print the registers that have been updated. 14835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void PrintWrittenRegisters(); 14845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void PrintWrittenVRegisters(); 14855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 14865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // As above, but respect LOG_REG and LOG_VREG. 14875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void LogWrittenRegisters() { 148888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois if (GetTraceParameters() & LOG_REGS) PrintWrittenRegisters(); 1489330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl } 14905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void LogWrittenVRegisters() { 149188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois if (GetTraceParameters() & LOG_VREGS) PrintWrittenVRegisters(); 1492330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl } 14935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void LogAllWrittenRegisters() { 14945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogWrittenRegisters(); 14955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogWrittenVRegisters(); 1496330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl } 1497330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl 1498330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl // Print individual register values (after update). 1499330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl void PrintRegister(unsigned code, Reg31Mode r31mode = Reg31IsStackPointer); 15005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void PrintVRegister(unsigned code, PrintRegisterFormat format); 1501330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl void PrintSystemRegister(SystemRegister id); 1502330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl 150388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois // Like Print* (above), but respect GetTraceParameters(). 1504330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl void LogRegister(unsigned code, Reg31Mode r31mode = Reg31IsStackPointer) { 150588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois if (GetTraceParameters() & LOG_REGS) PrintRegister(code, r31mode); 1506330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl } 15075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void LogVRegister(unsigned code, PrintRegisterFormat format) { 150888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois if (GetTraceParameters() & LOG_VREGS) PrintVRegister(code, format); 1509330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl } 1510330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl void LogSystemRegister(SystemRegister id) { 151188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois if (GetTraceParameters() & LOG_SYSREGS) PrintSystemRegister(id); 1512330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl } 1513330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl 1514330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl // Print memory accesses. 15150f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl void PrintRead(uintptr_t address, 15160f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl unsigned reg_code, 15175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl PrintRegisterFormat format); 15180f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl void PrintWrite(uintptr_t address, 15190f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl unsigned reg_code, 15200f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl PrintRegisterFormat format); 15210f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl void PrintVRead(uintptr_t address, 15220f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl unsigned reg_code, 15230f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl PrintRegisterFormat format, 15240f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl unsigned lane); 15250f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl void PrintVWrite(uintptr_t address, 15260f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl unsigned reg_code, 15270f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl PrintRegisterFormat format, 15280f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl unsigned lane); 1529330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl 153088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois // Like Print* (above), but respect GetTraceParameters(). 15310f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl void LogRead(uintptr_t address, 15320f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl unsigned reg_code, 15335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl PrintRegisterFormat format) { 153488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois if (GetTraceParameters() & LOG_REGS) PrintRead(address, reg_code, format); 1535330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl } 15360f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl void LogWrite(uintptr_t address, 15370f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl unsigned reg_code, 15385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl PrintRegisterFormat format) { 153988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois if (GetTraceParameters() & LOG_WRITE) PrintWrite(address, reg_code, format); 1540330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl } 15410f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl void LogVRead(uintptr_t address, 15420f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl unsigned reg_code, 15430f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl PrintRegisterFormat format, 15440f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl unsigned lane = 0) { 154588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois if (GetTraceParameters() & LOG_VREGS) { 15465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl PrintVRead(address, reg_code, format, lane); 15475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 1548330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl } 15490f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl void LogVWrite(uintptr_t address, 15500f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl unsigned reg_code, 15510f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl PrintRegisterFormat format, 15520f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl unsigned lane = 0) { 155388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois if (GetTraceParameters() & LOG_WRITE) { 15545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl PrintVWrite(address, reg_code, format, lane); 15555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 1556330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl } 1557330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl 15585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Helper functions for register tracing. 15590f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl void PrintRegisterRawHelper(unsigned code, 15600f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl Reg31Mode r31mode, 15615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int size_in_bytes = kXRegSizeInBytes); 15620f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl void PrintVRegisterRawHelper(unsigned code, 15630f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl int bytes = kQRegSizeInBytes, 15645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int lsb = 0); 15650f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl void PrintVRegisterFPHelper(unsigned code, 15660f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl unsigned lane_size_in_bytes, 15670f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl int lane_count = 1, 15680f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl int rightmost_lane = 0); 15695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 1570684cd2a7f5845539b58d0da7e012e39df49ceff0armvixl VIXL_NO_RETURN void DoUnreachable(const Instruction* instr); 1571330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl void DoTrace(const Instruction* instr); 1572330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl void DoLog(const Instruction* instr); 1573ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 1574ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl static const char* WRegNameForCode(unsigned code, 1575ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl Reg31Mode mode = Reg31IsZeroRegister); 1576ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl static const char* XRegNameForCode(unsigned code, 1577ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl Reg31Mode mode = Reg31IsZeroRegister); 1578ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl static const char* SRegNameForCode(unsigned code); 1579ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl static const char* DRegNameForCode(unsigned code); 1580ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl static const char* VRegNameForCode(unsigned code); 1581ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 158288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois bool IsColouredTrace() const { return coloured_trace_; } 158388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("IsColouredTrace", bool coloured_trace() const) { 158488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return IsColouredTrace(); 158588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 1586ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 158788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void SetColouredTrace(bool value); 158888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("SetColouredTrace", void set_coloured_trace(bool value)) { 158988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois SetColouredTrace(value); 159088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 1591330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl 1592d3832965c62a8ad461b9ea9eb0994ca6b0a3da2cAlexandre Rames // Values for traces parameters defined in simulator-constants-aarch64.h in 159388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois // enum TraceParameters. 159488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int GetTraceParameters() const { return trace_parameters_; } 159588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("GetTraceParameters", int trace_parameters() const) { 159688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return GetTraceParameters(); 159788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 159888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois 159988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void SetTraceParameters(int parameters); 160088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("SetTraceParameters", 160188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void set_trace_parameters(int parameters)) { 160288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois SetTraceParameters(parameters); 160388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 160488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois 160588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void SetInstructionStats(bool value); 160688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("SetInstructionStats", 160788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void set_instruction_stats(bool value)) { 160888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois SetInstructionStats(value); 160988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 1610ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 16114a102baf640077d6794c0b33bb976f94b86c532barmvixl // Clear the simulated local monitor to force the next store-exclusive 16124a102baf640077d6794c0b33bb976f94b86c532barmvixl // instruction to fail. 16130f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl void ClearLocalMonitor() { local_monitor_.Clear(); } 16144a102baf640077d6794c0b33bb976f94b86c532barmvixl 1615330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl void SilenceExclusiveAccessWarning() { 16164a102baf640077d6794c0b33bb976f94b86c532barmvixl print_exclusive_access_warning_ = false; 16174a102baf640077d6794c0b33bb976f94b86c532barmvixl } 16184a102baf640077d6794c0b33bb976f94b86c532barmvixl 1619064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames// Runtime call emulation support. 1620064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames// It requires VIXL's ABI features, and C++11 or greater. 1621482d4df29d1466ff87d94e74034f1a8659f1b354Jacob Bramley// Also, the initialisation of the tuples in RuntimeCall(Non)Void is incorrect 1622482d4df29d1466ff87d94e74034f1a8659f1b354Jacob Bramley// in GCC before 4.9.1: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=51253 1623482d4df29d1466ff87d94e74034f1a8659f1b354Jacob Bramley#if defined(VIXL_HAS_ABI_SUPPORT) && __cplusplus >= 201103L && \ 1624482d4df29d1466ff87d94e74034f1a8659f1b354Jacob Bramley (defined(__clang__) || GCC_VERSION_OR_NEWER(4, 9, 1)) 1625064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames 1626ca73ba046c11d65b6dce59cfd26847d14aba06abAlexandre Rames#define VIXL_HAS_SIMULATED_RUNTIME_CALL_SUPPORT 1627064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames 1628064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames// The implementation of the runtime call helpers require the functionality 1629064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames// provided by `std::index_sequence`. It is only available from C++14, but 1630064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames// we want runtime call simulation to work from C++11, so we emulate if 1631064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames// necessary. 1632064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames#if __cplusplus >= 201402L 1633064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames template <std::size_t... I> 1634064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames using local_index_sequence = std::index_sequence<I...>; 1635064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames template <typename... P> 1636064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames using __local_index_sequence_for = std::index_sequence_for<P...>; 1637064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames#else 1638064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames // Emulate the behaviour of `std::index_sequence` and 1639064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames // `std::index_sequence_for`. 1640064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames // Naming follow the `std` names, prefixed with `emulated_`. 1641064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames template <size_t... I> 1642064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames struct emulated_index_sequence {}; 1643064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames 1644064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames // A recursive template to create a sequence of indexes. 1645064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames // The base case (for `N == 0`) is declared outside of the class scope, as 1646064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames // required by C++. 1647064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames template <std::size_t N, size_t... I> 1648064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames struct emulated_make_index_sequence_helper 1649064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames : emulated_make_index_sequence_helper<N - 1, N - 1, I...> {}; 1650064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames 1651064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames template <std::size_t N> 1652064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames struct emulated_make_index_sequence : emulated_make_index_sequence_helper<N> { 1653064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames }; 1654064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames 1655064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames template <typename... P> 1656064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames struct emulated_index_sequence_for 1657064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames : emulated_make_index_sequence<sizeof...(P)> {}; 1658064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames 1659064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames template <std::size_t... I> 1660064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames using local_index_sequence = emulated_index_sequence<I...>; 1661064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames template <typename... P> 1662064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames using __local_index_sequence_for = emulated_index_sequence_for<P...>; 1663064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames#endif 1664064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames 1665064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames // Expand the argument tuple and perform the call. 1666064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames template <typename R, typename... P, std::size_t... I> 1667064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames R DoRuntimeCall(R (*function)(P...), 1668064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames std::tuple<P...> arguments, 1669064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames local_index_sequence<I...>) { 1670064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames return function(std::get<I>(arguments)...); 1671064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames } 1672064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames 1673064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames template <typename R, typename... P> 1674064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames void RuntimeCallNonVoid(R (*function)(P...)) { 1675064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames ABI abi; 1676064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames std::tuple<P...> argument_operands{ 1677064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames ReadGenericOperand<P>(abi.GetNextParameterGenericOperand<P>())...}; 1678064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames R return_value = DoRuntimeCall(function, 1679064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames argument_operands, 1680064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames __local_index_sequence_for<P...>{}); 1681064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames WriteGenericOperand(abi.GetReturnGenericOperand<R>(), return_value); 1682064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames } 1683064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames 1684064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames template <typename R, typename... P> 1685064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames void RuntimeCallVoid(R (*function)(P...)) { 1686064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames ABI abi; 1687064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames std::tuple<P...> argument_operands{ 1688064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames ReadGenericOperand<P>(abi.GetNextParameterGenericOperand<P>())...}; 1689064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames DoRuntimeCall(function, 1690064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames argument_operands, 1691064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames __local_index_sequence_for<P...>{}); 1692064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames } 1693064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames 1694064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames // We use `struct` for `void` return type specialisation. 1695064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames template <typename R, typename... P> 1696064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames struct RuntimeCallStructHelper { 1697482d4df29d1466ff87d94e74034f1a8659f1b354Jacob Bramley static void Wrapper(Simulator* simulator, uintptr_t function_pointer) { 1698064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames R (*function)(P...) = reinterpret_cast<R (*)(P...)>(function_pointer); 1699064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames simulator->RuntimeCallNonVoid(function); 1700064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames } 1701064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames }; 1702064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames 1703064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames // Partial specialization when the return type is `void`. 1704064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames template <typename... P> 1705064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames struct RuntimeCallStructHelper<void, P...> { 1706482d4df29d1466ff87d94e74034f1a8659f1b354Jacob Bramley static void Wrapper(Simulator* simulator, uintptr_t function_pointer) { 1707064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames void (*function)(P...) = 1708064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames reinterpret_cast<void (*)(P...)>(function_pointer); 1709064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames simulator->RuntimeCallVoid(function); 1710064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames } 1711064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames }; 1712064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames#endif 1713064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames 1714ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl protected: 1715b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl const char* clr_normal; 1716b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl const char* clr_flag_name; 1717b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl const char* clr_flag_value; 1718b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl const char* clr_reg_name; 1719b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl const char* clr_reg_value; 17205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const char* clr_vreg_name; 17215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const char* clr_vreg_value; 1722b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl const char* clr_memory_address; 17234a102baf640077d6794c0b33bb976f94b86c532barmvixl const char* clr_warning; 17244a102baf640077d6794c0b33bb976f94b86c532barmvixl const char* clr_warning_message; 1725b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl const char* clr_printf; 1726b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 1727ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // Simulation helpers ------------------------------------ 1728ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl bool ConditionPassed(Condition cond) { 1729ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl switch (cond) { 1730ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl case eq: 173188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadZ(); 1732ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl case ne: 173388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return !ReadZ(); 1734ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl case hs: 173588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadC(); 1736ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl case lo: 173788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return !ReadC(); 1738ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl case mi: 173988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadN(); 1740ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl case pl: 174188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return !ReadN(); 1742ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl case vs: 174388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadV(); 1744ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl case vc: 174588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return !ReadV(); 1746ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl case hi: 174788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadC() && !ReadZ(); 1748ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl case ls: 174988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return !(ReadC() && !ReadZ()); 1750ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl case ge: 175188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadN() == ReadV(); 1752ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl case lt: 175388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadN() != ReadV(); 1754ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl case gt: 175588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return !ReadZ() && (ReadN() == ReadV()); 1756ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl case le: 175788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return !(!ReadZ() && (ReadN() == ReadV())); 17586e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl case nv: 17596e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl VIXL_FALLTHROUGH(); 1760ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl case al: 1761ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl return true; 1762ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl default: 1763b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_UNREACHABLE(); 1764ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl return false; 1765ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 1766ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 1767ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 17684a102baf640077d6794c0b33bb976f94b86c532barmvixl bool ConditionPassed(Instr cond) { 17694a102baf640077d6794c0b33bb976f94b86c532barmvixl return ConditionPassed(static_cast<Condition>(cond)); 17704a102baf640077d6794c0b33bb976f94b86c532barmvixl } 17714a102baf640077d6794c0b33bb976f94b86c532barmvixl 17720f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl bool ConditionFailed(Condition cond) { return !ConditionPassed(cond); } 1773ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 1774c68cb64496485710cdb5b8480f8fee287058c93farmvixl void AddSubHelper(const Instruction* instr, int64_t op2); 1775684cd2a7f5845539b58d0da7e012e39df49ceff0armvixl uint64_t AddWithCarry(unsigned reg_size, 1776684cd2a7f5845539b58d0da7e012e39df49ceff0armvixl bool set_flags, 1777684cd2a7f5845539b58d0da7e012e39df49ceff0armvixl uint64_t left, 1778684cd2a7f5845539b58d0da7e012e39df49ceff0armvixl uint64_t right, 1779684cd2a7f5845539b58d0da7e012e39df49ceff0armvixl int carry_in = 0); 1780c68cb64496485710cdb5b8480f8fee287058c93farmvixl void LogicalHelper(const Instruction* instr, int64_t op2); 1781c68cb64496485710cdb5b8480f8fee287058c93farmvixl void ConditionalCompareHelper(const Instruction* instr, int64_t op2); 1782c68cb64496485710cdb5b8480f8fee287058c93farmvixl void LoadStoreHelper(const Instruction* instr, 1783ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl int64_t offset, 1784ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl AddrMode addrmode); 1785c68cb64496485710cdb5b8480f8fee287058c93farmvixl void LoadStorePairHelper(const Instruction* instr, AddrMode addrmode); 1786330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl uintptr_t AddressModeHelper(unsigned addr_reg, 1787330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl int64_t offset, 1788330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl AddrMode addrmode); 17895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void NEONLoadStoreMultiStructHelper(const Instruction* instr, 17905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl AddrMode addr_mode); 17915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void NEONLoadStoreSingleStructHelper(const Instruction* instr, 17925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl AddrMode addr_mode); 1793330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl 17940f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl uint64_t AddressUntag(uint64_t address) { return address & ~kAddressTagMask; } 1795ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 17964a102baf640077d6794c0b33bb976f94b86c532barmvixl template <typename T> 1797330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl T* AddressUntag(T* address) { 1798330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl uintptr_t address_raw = reinterpret_cast<uintptr_t>(address); 1799330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl return reinterpret_cast<T*>(AddressUntag(address_raw)); 18004a102baf640077d6794c0b33bb976f94b86c532barmvixl } 1801ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 1802ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl int64_t ShiftOperand(unsigned reg_size, 1803ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl int64_t value, 1804ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl Shift shift_type, 1805868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames unsigned amount) const; 1806ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl int64_t ExtendValue(unsigned reg_width, 1807ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl int64_t value, 1808ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl Extend extend_type, 1809868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames unsigned left_shift = 0) const; 1810868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames uint16_t PolynomialMult(uint8_t op1, uint8_t op2) const; 18115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 18120f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl void ld1(VectorFormat vform, LogicVRegister dst, uint64_t addr); 18130f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl void ld1(VectorFormat vform, LogicVRegister dst, int index, uint64_t addr); 18140f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl void ld1r(VectorFormat vform, LogicVRegister dst, uint64_t addr); 18155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void ld2(VectorFormat vform, 18165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst1, 18175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst2, 18185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr); 18195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void ld2(VectorFormat vform, 18205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst1, 18215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst2, 18225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index, 18235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr); 18245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void ld2r(VectorFormat vform, 18250f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst1, 18260f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst2, 18270f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl uint64_t addr); 18285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void ld3(VectorFormat vform, 18295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst1, 18305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst2, 18315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst3, 18325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr); 18335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void ld3(VectorFormat vform, 18345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst1, 18355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst2, 18365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst3, 18375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index, 18385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr); 18395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void ld3r(VectorFormat vform, 18400f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst1, 18410f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst2, 18420f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst3, 18430f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl uint64_t addr); 18445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void ld4(VectorFormat vform, 18455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst1, 18465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst2, 18475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst3, 18485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst4, 18495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr); 18505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void ld4(VectorFormat vform, 18515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst1, 18525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst2, 18535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst3, 18545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst4, 18555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index, 18565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr); 18575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void ld4r(VectorFormat vform, 18580f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst1, 18590f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst2, 18600f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst3, 18610f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst4, 18620f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl uint64_t addr); 18630f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl void st1(VectorFormat vform, LogicVRegister src, uint64_t addr); 18640f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl void st1(VectorFormat vform, LogicVRegister src, int index, uint64_t addr); 18655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void st2(VectorFormat vform, 18665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister src, 18675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister src2, 18685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr); 18695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void st2(VectorFormat vform, 18705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister src, 18715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister src2, 18725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index, 18735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr); 18745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void st3(VectorFormat vform, 18755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister src, 18765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister src2, 18775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister src3, 18785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr); 18795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void st3(VectorFormat vform, 18805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister src, 18815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister src2, 18825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister src3, 18835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index, 18845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr); 18855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void st4(VectorFormat vform, 18865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister src, 18875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister src2, 18885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister src3, 18895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister src4, 18905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr); 18915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void st4(VectorFormat vform, 18925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister src, 18935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister src2, 18945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister src3, 18955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister src4, 18965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index, 18975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr); 18985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister cmp(VectorFormat vform, 18995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 19005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 19015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 19025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Condition cond); 19035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister cmp(VectorFormat vform, 19045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 19055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 19065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int imm, 19075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Condition cond); 19085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister cmptst(VectorFormat vform, 19095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 19105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 19115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 19125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister add(VectorFormat vform, 19135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 19145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 19155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 19165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister addp(VectorFormat vform, 19175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 19185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 19195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 19205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister mla(VectorFormat vform, 19215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 19225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 19235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 19245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister mls(VectorFormat vform, 19255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 19265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 19275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 19285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister mul(VectorFormat vform, 19295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 19305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 19315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 19325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister mul(VectorFormat vform, 19335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 19345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 19355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 19365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 19375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister mla(VectorFormat vform, 19385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 19395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 19405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 19415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 19425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister mls(VectorFormat vform, 19435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 19445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 19455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 19465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 19475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister pmul(VectorFormat vform, 19485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 19495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 19505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 19515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 19525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl typedef LogicVRegister (Simulator::*ByElementOp)(VectorFormat vform, 19535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 19545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 19555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 19565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 19575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fmul(VectorFormat vform, 19585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 19595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 19605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 19615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 19625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fmla(VectorFormat vform, 19635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 19645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 19655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 19665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 19675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fmls(VectorFormat vform, 19685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 19695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 19705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 19715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 19725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fmulx(VectorFormat vform, 19735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 19745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 19755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 19765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 19775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister smull(VectorFormat vform, 19785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 19795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 19805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 19815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 19825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister smull2(VectorFormat vform, 19835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 19845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 19855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 19865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 19875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister umull(VectorFormat vform, 19885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 19895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 19905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 19915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 19925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister umull2(VectorFormat vform, 19935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 19945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 19955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 19965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 19975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister smlal(VectorFormat vform, 19985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 19995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 20005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 20015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 20025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister smlal2(VectorFormat vform, 20035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 20045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 20055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 20065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 20075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister umlal(VectorFormat vform, 20085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 20095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 20105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 20115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 20125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister umlal2(VectorFormat vform, 20135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 20145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 20155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 20165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 20175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister smlsl(VectorFormat vform, 20185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 20195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 20205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 20215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 20225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister smlsl2(VectorFormat vform, 20235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 20245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 20255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 20265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 20275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister umlsl(VectorFormat vform, 20285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 20295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 20305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 20315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 20325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister umlsl2(VectorFormat vform, 20335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 20345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 20355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 20365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 20375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sqdmull(VectorFormat vform, 20385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 20395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 20405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 20415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 20425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sqdmull2(VectorFormat vform, 20435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 20445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 20455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 20465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 20475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sqdmlal(VectorFormat vform, 20485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 20495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 20505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 20515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 20525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sqdmlal2(VectorFormat vform, 20535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 20545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 20555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 20565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 20575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sqdmlsl(VectorFormat vform, 20585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 20595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 20605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 20615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 20625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sqdmlsl2(VectorFormat vform, 20635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 20645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 20655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 20665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 20675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sqdmulh(VectorFormat vform, 20685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 20695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 20705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 20715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 20725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sqrdmulh(VectorFormat vform, 20735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 20745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 20755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 20765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 20775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sub(VectorFormat vform, 20785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 20795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 20805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 20815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister and_(VectorFormat vform, 20825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 20835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 20845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 20855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister orr(VectorFormat vform, 20865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 20875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 20885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 20895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister orn(VectorFormat vform, 20905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 20915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 20925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 20935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister eor(VectorFormat vform, 20945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 20955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 20965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 20975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister bic(VectorFormat vform, 20985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 20995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 21005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 21015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister bic(VectorFormat vform, 21025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 21045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t imm); 21055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister bif(VectorFormat vform, 21065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 21085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 21095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister bit(VectorFormat vform, 21105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 21125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 21135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister bsl(VectorFormat vform, 21145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 21165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 21175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister cls(VectorFormat vform, 21185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 21205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister clz(VectorFormat vform, 21215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 21235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister cnt(VectorFormat vform, 21245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 21265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister not_(VectorFormat vform, 21275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 21295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister rbit(VectorFormat vform, 21305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 21325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister rev(VectorFormat vform, 21335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 21355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int revSize); 21365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister rev16(VectorFormat vform, 21375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 21395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister rev32(VectorFormat vform, 21405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 21425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister rev64(VectorFormat vform, 21435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 21455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister addlp(VectorFormat vform, 21465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 21485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl bool is_signed, 21495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl bool do_accumulate); 21505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister saddlp(VectorFormat vform, 21515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 21535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister uaddlp(VectorFormat vform, 21545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 21565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sadalp(VectorFormat vform, 21575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 21595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister uadalp(VectorFormat vform, 21605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 21625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister ext(VectorFormat vform, 21635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 21655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 21665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 21675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister ins_element(VectorFormat vform, 21685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int dst_index, 21705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 21715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int src_index); 21725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister ins_immediate(VectorFormat vform, 21735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int dst_index, 21755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t imm); 21765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dup_element(VectorFormat vform, 21775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 21795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int src_index); 21805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dup_immediate(VectorFormat vform, 21815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t imm); 21830f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister movi(VectorFormat vform, LogicVRegister dst, uint64_t imm); 21840f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister mvni(VectorFormat vform, LogicVRegister dst, uint64_t imm); 21855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister orr(VectorFormat vform, 21865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 21885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t imm); 21895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sshl(VectorFormat vform, 21905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 21925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 21935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister ushl(VectorFormat vform, 21945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 21965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 21975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sminmax(VectorFormat vform, 21985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 22005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 22015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl bool max); 22025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister smax(VectorFormat vform, 22030f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst, 22040f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src1, 22050f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src2); 22065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister smin(VectorFormat vform, 22070f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst, 22080f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src1, 22090f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src2); 22105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sminmaxp(VectorFormat vform, 22115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int dst_index, 22135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 22145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl bool max); 22155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister smaxp(VectorFormat vform, 22165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 22185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 22195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sminp(VectorFormat vform, 22205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 22225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 22235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister addp(VectorFormat vform, 22245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 22265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister addv(VectorFormat vform, 22275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 22295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister uaddlv(VectorFormat vform, 22305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 22325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister saddlv(VectorFormat vform, 22335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 22355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sminmaxv(VectorFormat vform, 22365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 22385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl bool max); 22395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister smaxv(VectorFormat vform, 22405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 22425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sminv(VectorFormat vform, 22435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 22455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister uxtl(VectorFormat vform, 22465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 22485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister uxtl2(VectorFormat vform, 22495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 22515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sxtl(VectorFormat vform, 22525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 22545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sxtl2(VectorFormat vform, 22555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 22575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister tbl(VectorFormat vform, 22585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab, 22605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& ind); 22615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister tbl(VectorFormat vform, 22625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab, 22645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab2, 22655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& ind); 22665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister tbl(VectorFormat vform, 22675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab, 22695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab2, 22705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab3, 22715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& ind); 22725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister tbl(VectorFormat vform, 22735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab, 22755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab2, 22765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab3, 22775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab4, 22785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& ind); 22795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister tbx(VectorFormat vform, 22805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab, 22825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& ind); 22835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister tbx(VectorFormat vform, 22845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab, 22865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab2, 22875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& ind); 22885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister tbx(VectorFormat vform, 22895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab, 22915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab2, 22925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab3, 22935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& ind); 22945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister tbx(VectorFormat vform, 22955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab, 22975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab2, 22985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab3, 22995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab4, 23005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& ind); 23015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister uaddl(VectorFormat vform, 23025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 23035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 23045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 23055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister uaddl2(VectorFormat vform, 23065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 23075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 23085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 23095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister uaddw(VectorFormat vform, 23105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 23115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 23125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 23135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister uaddw2(VectorFormat vform, 23145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 23155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 23165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 23175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister saddl(VectorFormat vform, 23185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 23195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 23205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 23215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister saddl2(VectorFormat vform, 23225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 23235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 23245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 23255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister saddw(VectorFormat vform, 23265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 23275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 23285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 23295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister saddw2(VectorFormat vform, 23305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 23315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 23325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 23335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister usubl(VectorFormat vform, 23340f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst, 23350f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src1, 23360f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src2); 23375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister usubl2(VectorFormat vform, 23385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 23395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 23405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 23415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister usubw(VectorFormat vform, 23425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 23435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 23445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 23455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister usubw2(VectorFormat vform, 23465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 23475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 23485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 23495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister ssubl(VectorFormat vform, 23505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 23515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 23525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 23535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister ssubl2(VectorFormat vform, 23545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 23555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 23565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 23575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister ssubw(VectorFormat vform, 23585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 23595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 23605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 23615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister ssubw2(VectorFormat vform, 23625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 23635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 23645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 23655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister uminmax(VectorFormat vform, 23665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 23675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 23685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 23695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl bool max); 23705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister umax(VectorFormat vform, 23710f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst, 23720f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src1, 23730f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src2); 23745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister umin(VectorFormat vform, 23750f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst, 23760f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src1, 23770f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src2); 23785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister uminmaxp(VectorFormat vform, 23795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 23805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int dst_index, 23815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 23825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl bool max); 23835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister umaxp(VectorFormat vform, 23845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 23855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 23865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 23875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister uminp(VectorFormat vform, 23885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 23895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 23905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 23915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister uminmaxv(VectorFormat vform, 23925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 23935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 23945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl bool max); 23955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister umaxv(VectorFormat vform, 23965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 23975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 23985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister uminv(VectorFormat vform, 23995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 24015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister trn1(VectorFormat vform, 24025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 24045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 24055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister trn2(VectorFormat vform, 24065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 24085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 24095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister zip1(VectorFormat vform, 24105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 24125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 24135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister zip2(VectorFormat vform, 24145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 24165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 24175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister uzp1(VectorFormat vform, 24185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 24205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 24215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister uzp2(VectorFormat vform, 24225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 24245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 24255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister shl(VectorFormat vform, 24265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 24285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 24295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister scvtf(VectorFormat vform, 24305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 24325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int fbits, 24335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl FPRounding rounding_mode); 24345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister ucvtf(VectorFormat vform, 24355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 24375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int fbits, 24385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl FPRounding rounding_mode); 24395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sshll(VectorFormat vform, 24405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 24425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 24435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sshll2(VectorFormat vform, 24445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 24465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 24475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister shll(VectorFormat vform, 24485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 24505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister shll2(VectorFormat vform, 24515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 24535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister ushll(VectorFormat vform, 24545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 24565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 24575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister ushll2(VectorFormat vform, 24585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 24605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 24615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sli(VectorFormat vform, 24625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 24645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 24655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sri(VectorFormat vform, 24665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 24685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 24695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sshr(VectorFormat vform, 24705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 24725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 24735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister ushr(VectorFormat vform, 24745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 24765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 24775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister ssra(VectorFormat vform, 24785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 24805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 24815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister usra(VectorFormat vform, 24825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 24845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 24855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister srsra(VectorFormat vform, 24865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 24885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 24895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister ursra(VectorFormat vform, 24905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 24925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 24935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister suqadd(VectorFormat vform, 24940f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst, 24950f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src); 24965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister usqadd(VectorFormat vform, 24970f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst, 24980f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src); 24995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sqshl(VectorFormat vform, 25005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 25025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 25035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister uqshl(VectorFormat vform, 25045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 25065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 25075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sqshlu(VectorFormat vform, 25085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 25105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 25115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister abs(VectorFormat vform, 25125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 25145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister neg(VectorFormat vform, 25155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 25175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister extractnarrow(VectorFormat vform, 25185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl bool dstIsSigned, 25205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 25215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl bool srcIsSigned); 25225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister xtn(VectorFormat vform, 25235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 25255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sqxtn(VectorFormat vform, 25265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 25285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister uqxtn(VectorFormat vform, 25295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 25315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sqxtun(VectorFormat vform, 25325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 25345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister absdiff(VectorFormat vform, 25355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 25375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 25385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl bool issigned); 25395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister saba(VectorFormat vform, 25405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 25425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 25435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister uaba(VectorFormat vform, 25445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 25465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 25475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister shrn(VectorFormat vform, 25485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 25505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 25515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister shrn2(VectorFormat vform, 25520f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst, 25530f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src, 25540f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl int shift); 25555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister rshrn(VectorFormat vform, 25565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 25585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 25595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister rshrn2(VectorFormat vform, 25605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 25625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 25635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister uqshrn(VectorFormat vform, 25645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 25665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 25675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister uqshrn2(VectorFormat vform, 25685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 25705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 25715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister uqrshrn(VectorFormat vform, 25725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 25745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 25755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister uqrshrn2(VectorFormat vform, 25765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 25785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 25795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sqshrn(VectorFormat vform, 25805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 25825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 25835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sqshrn2(VectorFormat vform, 25845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 25865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 25875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sqrshrn(VectorFormat vform, 25885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 25905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 25915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sqrshrn2(VectorFormat vform, 25925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 25945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 25955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sqshrun(VectorFormat vform, 25965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 25985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 25995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sqshrun2(VectorFormat vform, 26005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 26015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 26025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 26035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sqrshrun(VectorFormat vform, 26045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 26055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 26065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 26075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sqrshrun2(VectorFormat vform, 26085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 26095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 26105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 26115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sqrdmulh(VectorFormat vform, 26125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 26135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 26145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 26155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl bool round = true); 26165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sqdmulh(VectorFormat vform, 26175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 26185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 26195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 26200f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl#define NEON_3VREG_LOGIC_LIST(V) \ 26210f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(addhn) \ 26220f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(addhn2) \ 26230f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(raddhn) \ 26240f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(raddhn2) \ 26250f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(subhn) \ 26260f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(subhn2) \ 26270f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(rsubhn) \ 26280f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(rsubhn2) \ 26290f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(pmull) \ 26300f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(pmull2) \ 26310f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(sabal) \ 26320f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(sabal2) \ 26330f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(uabal) \ 26340f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(uabal2) \ 26350f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(sabdl) \ 26360f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(sabdl2) \ 26370f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(uabdl) \ 26380f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(uabdl2) \ 26390f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(smull) \ 26400f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(smull2) \ 26410f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(umull) \ 26420f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(umull2) \ 26430f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(smlal) \ 26440f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(smlal2) \ 26450f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(umlal) \ 26460f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(umlal2) \ 26470f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(smlsl) \ 26480f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(smlsl2) \ 26490f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(umlsl) \ 26500f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(umlsl2) \ 26510f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(sqdmlal) \ 26520f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(sqdmlal2) \ 26530f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(sqdmlsl) \ 26540f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(sqdmlsl2) \ 26550f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(sqdmull) \ 26560f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(sqdmull2) 26570f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl 26580f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl#define DEFINE_LOGIC_FUNC(FXN) \ 26590f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister FXN(VectorFormat vform, \ 26600f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst, \ 26610f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src1, \ 26620f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src2); 26635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl NEON_3VREG_LOGIC_LIST(DEFINE_LOGIC_FUNC) 26640f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl#undef DEFINE_LOGIC_FUNC 26650f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl 26660f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl#define NEON_FP3SAME_LIST(V) \ 26670f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(fadd, FPAdd, false) \ 26680f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(fsub, FPSub, true) \ 26690f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(fmul, FPMul, true) \ 26700f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(fmulx, FPMulx, true) \ 26710f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(fdiv, FPDiv, true) \ 26720f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(fmax, FPMax, false) \ 26730f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(fmin, FPMin, false) \ 26740f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(fmaxnm, FPMaxNM, false) \ 26750f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(fminnm, FPMinNM, false) 26760f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl 26770f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl#define DECLARE_NEON_FP_VECTOR_OP(FN, OP, PROCNAN) \ 26780f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl template <typename T> \ 26790f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister FN(VectorFormat vform, \ 26800f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst, \ 26810f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src1, \ 26820f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src2); \ 26830f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister FN(VectorFormat vform, \ 26840f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst, \ 26850f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src1, \ 26860f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src2); 26875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl NEON_FP3SAME_LIST(DECLARE_NEON_FP_VECTOR_OP) 26880f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl#undef DECLARE_NEON_FP_VECTOR_OP 26890f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl 26900f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl#define NEON_FPPAIRWISE_LIST(V) \ 26910f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(faddp, fadd, FPAdd) \ 26920f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(fmaxp, fmax, FPMax) \ 26930f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(fmaxnmp, fmaxnm, FPMaxNM) \ 26940f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(fminp, fmin, FPMin) \ 26950f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(fminnmp, fminnm, FPMinNM) 26960f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl 26970f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl#define DECLARE_NEON_FP_PAIR_OP(FNP, FN, OP) \ 26980f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister FNP(VectorFormat vform, \ 26990f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst, \ 27000f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src1, \ 27010f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src2); \ 27020f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister FNP(VectorFormat vform, \ 27030f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst, \ 27040f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src); 27055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl NEON_FPPAIRWISE_LIST(DECLARE_NEON_FP_PAIR_OP) 27060f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl#undef DECLARE_NEON_FP_PAIR_OP 27075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 27085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl template <typename T> 27095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister frecps(VectorFormat vform, 27105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 27115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 27125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 27135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister frecps(VectorFormat vform, 27145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 27155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 27165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 27175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl template <typename T> 27185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister frsqrts(VectorFormat vform, 27195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 27205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 27215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 27225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister frsqrts(VectorFormat vform, 27235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 27245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 27255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 27265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl template <typename T> 27275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fmla(VectorFormat vform, 27285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 27295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 27305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 27315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fmla(VectorFormat vform, 27325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 27335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 27345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 27355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl template <typename T> 27365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fmls(VectorFormat vform, 27375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 27385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 27395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 27405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fmls(VectorFormat vform, 27415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 27425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 27435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 27445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fnmul(VectorFormat vform, 27455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 27465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 27475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 27485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 27495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl template <typename T> 27505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fcmp(VectorFormat vform, 27515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 27525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 27535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 27545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Condition cond); 27555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fcmp(VectorFormat vform, 27565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 27575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 27585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 27595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Condition cond); 27605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fabscmp(VectorFormat vform, 27615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 27625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 27635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 27645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Condition cond); 27655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fcmp_zero(VectorFormat vform, 27665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 27675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 27685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Condition cond); 27695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 27705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl template <typename T> 27715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fneg(VectorFormat vform, 27725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 27735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 27745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fneg(VectorFormat vform, 27755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 27765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 27775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl template <typename T> 27785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister frecpx(VectorFormat vform, 27795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 27805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 27815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister frecpx(VectorFormat vform, 27825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 27835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 27845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl template <typename T> 27855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fabs_(VectorFormat vform, 27865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 27875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 27885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fabs_(VectorFormat vform, 27895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 27905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 27915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fabd(VectorFormat vform, 27925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 27935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 27945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 27955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister frint(VectorFormat vform, 27965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 27975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 27985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl FPRounding rounding_mode, 27995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl bool inexact_exception = false); 28005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fcvts(VectorFormat vform, 28015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 28035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl FPRounding rounding_mode, 28045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int fbits = 0); 28055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fcvtu(VectorFormat vform, 28065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 28085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl FPRounding rounding_mode, 28095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int fbits = 0); 28105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fcvtl(VectorFormat vform, 28115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 28135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fcvtl2(VectorFormat vform, 28145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 28165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fcvtn(VectorFormat vform, 28175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 28195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fcvtn2(VectorFormat vform, 28205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 28225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fcvtxn(VectorFormat vform, 28235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 28255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fcvtxn2(VectorFormat vform, 28265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 28285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fsqrt(VectorFormat vform, 28295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 28315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister frsqrte(VectorFormat vform, 28325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 28345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister frecpe(VectorFormat vform, 28355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 28375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl FPRounding rounding); 28385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister ursqrte(VectorFormat vform, 28395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 28415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister urecpe(VectorFormat vform, 28425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 28445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 28455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl typedef float (Simulator::*FPMinMaxOp)(float a, float b); 28465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 28475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fminmaxv(VectorFormat vform, 28485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 28505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl FPMinMaxOp Op); 28515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 28525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fminv(VectorFormat vform, 28535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 28555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fmaxv(VectorFormat vform, 28565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 28585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fminnmv(VectorFormat vform, 28595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 28615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fmaxnmv(VectorFormat vform, 28625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 28645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 28650f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl static const uint32_t CRC32_POLY = 0x04C11DB7; 28665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl static const uint32_t CRC32C_POLY = 0x1EDC6F41; 28675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint32_t Poly32Mod2(unsigned n, uint64_t data, uint32_t poly); 28685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl template <typename T> 28695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint32_t Crc32Checksum(uint32_t acc, T val, uint32_t poly); 28705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint32_t Crc32Checksum(uint32_t acc, uint64_t val, uint32_t poly); 28715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 28725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void SysOp_W(int op, int64_t val); 2873ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 2874b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl template <typename T> 28755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl T FPRecipSqrtEstimate(T op); 28765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl template <typename T> 28775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl T FPRecipEstimate(T op, FPRounding rounding); 28785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl template <typename T, typename R> 28795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl R FPToFixed(T op, int fbits, bool is_signed, FPRounding rounding); 2880b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 28816e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl void FPCompare(double val0, double val1, FPTrapFlags trap); 2882ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl double FPRoundInt(double value, FPRounding round_mode); 2883578645f14e122d2b87d907e298cda7e7d0babf1farmvixl double FPToDouble(float value); 2884578645f14e122d2b87d907e298cda7e7d0babf1farmvixl float FPToFloat(double value, FPRounding round_mode); 28855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl float FPToFloat(float16 value); 28865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl float16 FPToFloat16(float value, FPRounding round_mode); 28875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl float16 FPToFloat16(double value, FPRounding round_mode); 28885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl double recip_sqrt_estimate(double a); 28895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl double recip_estimate(double a); 28905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl double FPRecipSqrtEstimate(double a); 28915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl double FPRecipEstimate(double a); 2892578645f14e122d2b87d907e298cda7e7d0babf1farmvixl double FixedToDouble(int64_t src, int fbits, FPRounding round_mode); 2893578645f14e122d2b87d907e298cda7e7d0babf1farmvixl double UFixedToDouble(uint64_t src, int fbits, FPRounding round_mode); 2894578645f14e122d2b87d907e298cda7e7d0babf1farmvixl float FixedToFloat(int64_t src, int fbits, FPRounding round_mode); 2895578645f14e122d2b87d907e298cda7e7d0babf1farmvixl float UFixedToFloat(uint64_t src, int fbits, FPRounding round_mode); 2896ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl int32_t FPToInt32(double value, FPRounding rmode); 2897ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl int64_t FPToInt64(double value, FPRounding rmode); 2898ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl uint32_t FPToUInt32(double value, FPRounding rmode); 2899ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl uint64_t FPToUInt64(double value, FPRounding rmode); 2900f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl 2901f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl template <typename T> 2902b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl T FPAdd(T op1, T op2); 2903f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl 2904f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl template <typename T> 2905b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl T FPDiv(T op1, T op2); 2906b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 2907b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl template <typename T> 2908b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl T FPMax(T a, T b); 2909f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl 2910f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl template <typename T> 2911f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl T FPMaxNM(T a, T b); 2912f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl 2913f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl template <typename T> 2914b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl T FPMin(T a, T b); 2915b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 2916b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl template <typename T> 2917f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl T FPMinNM(T a, T b); 2918ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 2919b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl template <typename T> 2920b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl T FPMul(T op1, T op2); 2921b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 2922b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl template <typename T> 29235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl T FPMulx(T op1, T op2); 29245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 29255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl template <typename T> 2926b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl T FPMulAdd(T a, T op1, T op2); 2927b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 2928b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl template <typename T> 2929b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl T FPSqrt(T op); 2930b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 2931b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl template <typename T> 2932b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl T FPSub(T op1, T op2); 2933b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 29345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl template <typename T> 29355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl T FPRecipStepFused(T op1, T op2); 29365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 29375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl template <typename T> 29385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl T FPRSqrtStepFused(T op1, T op2); 29395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 2940b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl // This doesn't do anything at the moment. We'll need it if we want support 2941b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl // for cumulative exception bits or floating-point exceptions. 29420f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl void FPProcessException() {} 2943b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 2944c68cb64496485710cdb5b8480f8fee287058c93farmvixl bool FPProcessNaNs(const Instruction* instr); 2945b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 2946ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // Pseudo Printf instruction 2947c68cb64496485710cdb5b8480f8fee287058c93farmvixl void DoPrintf(const Instruction* instr); 2948ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 2949064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames// Simulate a runtime call. 2950ca73ba046c11d65b6dce59cfd26847d14aba06abAlexandre Rames#ifndef VIXL_HAS_SIMULATED_RUNTIME_CALL_SUPPORT 2951064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames VIXL_NO_RETURN_IN_DEBUG_MODE 2952064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames#endif 2953064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames void DoRuntimeCall(const Instruction* instr); 2954064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames 2955ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // Processor state --------------------------------------- 2956ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 29574a102baf640077d6794c0b33bb976f94b86c532barmvixl // Simulated monitors for exclusive access instructions. 29584a102baf640077d6794c0b33bb976f94b86c532barmvixl SimExclusiveLocalMonitor local_monitor_; 29594a102baf640077d6794c0b33bb976f94b86c532barmvixl SimExclusiveGlobalMonitor global_monitor_; 29604a102baf640077d6794c0b33bb976f94b86c532barmvixl 2961ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // Output stream. 2962ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FILE* stream_; 2963ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl PrintDisassembler* print_disasm_; 2964ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 2965578645f14e122d2b87d907e298cda7e7d0babf1farmvixl // Instruction statistics instrumentation. 2966578645f14e122d2b87d907e298cda7e7d0babf1farmvixl Instrument* instrumentation_; 2967578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 2968ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // General purpose registers. Register 31 is the stack pointer. 2969ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl SimRegister registers_[kNumberOfRegisters]; 2970ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 29715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Vector registers 29725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister vregisters_[kNumberOfVRegisters]; 2973ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 2974ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // Program Status Register. 2975ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // bits[31, 27]: Condition flags N, Z, C, and V. 2976ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // (Negative, Zero, Carry, Overflow) 2977578645f14e122d2b87d907e298cda7e7d0babf1farmvixl SimSystemRegister nzcv_; 2978578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 2979578645f14e122d2b87d907e298cda7e7d0babf1farmvixl // Floating-Point Control Register 2980578645f14e122d2b87d907e298cda7e7d0babf1farmvixl SimSystemRegister fpcr_; 2981578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 2982578645f14e122d2b87d907e298cda7e7d0babf1farmvixl // Only a subset of FPCR features are supported by the simulator. This helper 2983578645f14e122d2b87d907e298cda7e7d0babf1farmvixl // checks that the FPCR settings are supported. 2984578645f14e122d2b87d907e298cda7e7d0babf1farmvixl // 2985578645f14e122d2b87d907e298cda7e7d0babf1farmvixl // This is checked when floating-point instructions are executed, not when 2986578645f14e122d2b87d907e298cda7e7d0babf1farmvixl // FPCR is set. This allows generated code to modify FPCR for external 2987578645f14e122d2b87d907e298cda7e7d0babf1farmvixl // functions, or to save and restore it when entering and leaving generated 2988578645f14e122d2b87d907e298cda7e7d0babf1farmvixl // code. 2989578645f14e122d2b87d907e298cda7e7d0babf1farmvixl void AssertSupportedFPCR() { 299088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois // No flush-to-zero support. 299188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_ASSERT(ReadFpcr().GetFZ() == 0); 299288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois // Ties-to-even rounding only. 299388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_ASSERT(ReadFpcr().GetRMode() == FPTieEven); 2994578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 299588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois // The simulator does not support half-precision operations so 299688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois // GetFpcr().AHP() is irrelevant, and is not checked here. 2997578645f14e122d2b87d907e298cda7e7d0babf1farmvixl } 2998ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 2999330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl static int CalcNFlag(uint64_t result, unsigned reg_size) { 3000578645f14e122d2b87d907e298cda7e7d0babf1farmvixl return (result >> (reg_size - 1)) & 1; 3001ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 3002ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 30030f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl static int CalcZFlag(uint64_t result) { return (result == 0) ? 1 : 0; } 3004ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 3005ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl static const uint32_t kConditionFlagsMask = 0xf0000000; 3006ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 3007ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // Stack 3008ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl byte* stack_; 3009ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl static const int stack_protection_size_ = 256; 3010ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // 2 KB stack. 3011ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl static const int stack_size_ = 2 * 1024 + 2 * stack_protection_size_; 3012ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl byte* stack_limit_; 3013ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 3014ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl Decoder* decoder_; 3015ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // Indicates if the pc has been modified by the instruction and should not be 3016ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // automatically incremented. 3017ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl bool pc_modified_; 3018c68cb64496485710cdb5b8480f8fee287058c93farmvixl const Instruction* pc_; 3019ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 3020ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl static const char* xreg_names[]; 3021ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl static const char* wreg_names[]; 3022ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl static const char* sreg_names[]; 3023ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl static const char* dreg_names[]; 3024ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl static const char* vreg_names[]; 3025ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 3026ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl private: 30276e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl template <typename T> 30286e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl static T FPDefaultNaN(); 30296e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 30306e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // Standard NaN processing. 30316e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl template <typename T> 30326e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl T FPProcessNaN(T op) { 30336e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl VIXL_ASSERT(std::isnan(op)); 30346e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if (IsSignallingNaN(op)) { 30356e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl FPProcessException(); 30366e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 303788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadDN() ? FPDefaultNaN<T>() : ToQuietNaN(op); 30386e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 30396e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 30406e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl template <typename T> 30416e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl T FPProcessNaNs(T op1, T op2) { 30426e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if (IsSignallingNaN(op1)) { 30436e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return FPProcessNaN(op1); 30446e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } else if (IsSignallingNaN(op2)) { 30456e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return FPProcessNaN(op2); 30466e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } else if (std::isnan(op1)) { 30476e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl VIXL_ASSERT(IsQuietNaN(op1)); 30486e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return FPProcessNaN(op1); 30496e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } else if (std::isnan(op2)) { 30506e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl VIXL_ASSERT(IsQuietNaN(op2)); 30516e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return FPProcessNaN(op2); 30526e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } else { 30536e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return 0.0; 30546e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 30556e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 30566e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 30576e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl template <typename T> 30586e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl T FPProcessNaNs3(T op1, T op2, T op3) { 30596e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if (IsSignallingNaN(op1)) { 30606e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return FPProcessNaN(op1); 30616e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } else if (IsSignallingNaN(op2)) { 30626e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return FPProcessNaN(op2); 30636e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } else if (IsSignallingNaN(op3)) { 30646e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return FPProcessNaN(op3); 30656e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } else if (std::isnan(op1)) { 30666e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl VIXL_ASSERT(IsQuietNaN(op1)); 30676e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return FPProcessNaN(op1); 30686e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } else if (std::isnan(op2)) { 30696e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl VIXL_ASSERT(IsQuietNaN(op2)); 30706e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return FPProcessNaN(op2); 30716e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } else if (std::isnan(op3)) { 30726e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl VIXL_ASSERT(IsQuietNaN(op3)); 30736e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return FPProcessNaN(op3); 30746e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } else { 30756e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return 0.0; 30766e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 30776e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 30786e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 3079ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl bool coloured_trace_; 3080578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 3081330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl // A set of TraceParameters flags. 3082330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl int trace_parameters_; 3083578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 3084578645f14e122d2b87d907e298cda7e7d0babf1farmvixl // Indicates whether the instruction instrumentation is active. 3085578645f14e122d2b87d907e298cda7e7d0babf1farmvixl bool instruction_stats_; 30864a102baf640077d6794c0b33bb976f94b86c532barmvixl 30874a102baf640077d6794c0b33bb976f94b86c532barmvixl // Indicates whether the exclusive-access warning has been printed. 30884a102baf640077d6794c0b33bb976f94b86c532barmvixl bool print_exclusive_access_warning_; 30894a102baf640077d6794c0b33bb976f94b86c532barmvixl void PrintExclusiveAccessWarning(); 3090ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl}; 3091064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames 3092482d4df29d1466ff87d94e74034f1a8659f1b354Jacob Bramley#if defined(VIXL_HAS_SIMULATED_RUNTIME_CALL_SUPPORT) && __cplusplus < 201402L 3093064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames// Base case of the recursive template used to emulate C++14 3094064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames// `std::index_sequence`. 3095064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Ramestemplate <size_t... I> 3096064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Ramesstruct Simulator::emulated_make_index_sequence_helper<0, I...> 3097064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames : Simulator::emulated_index_sequence<I...> {}; 3098064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames#endif 3099064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames 310088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois} // namespace aarch64 3101ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl} // namespace vixl 3102ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 3103d3832965c62a8ad461b9ea9eb0994ca6b0a3da2cAlexandre Rames#endif // VIXL_AARCH64_SIMULATOR_AARCH64_H_ 3104