simulator-aarch64.h revision f75ec85cb9c8690e42125aea3dac1e57d46c21da
1b78f13911bfe6eda303e91ef215c87a165aae8aeAlexandre Rames// Copyright 2015, VIXL authors 2ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// All rights reserved. 3ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// 4ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// Redistribution and use in source and binary forms, with or without 5ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// modification, are permitted provided that the following conditions are met: 6ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// 7ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// * Redistributions of source code must retain the above copyright notice, 8ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// this list of conditions and the following disclaimer. 9ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// * Redistributions in binary form must reproduce the above copyright notice, 10ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// this list of conditions and the following disclaimer in the documentation 11ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// and/or other materials provided with the distribution. 12ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// * Neither the name of ARM Limited nor the names of its contributors may be 13ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// used to endorse or promote products derived from this software without 14ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// specific prior written permission. 15ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// 16ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND 17ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 20ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 23ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 27d3832965c62a8ad461b9ea9eb0994ca6b0a3da2cAlexandre Rames#ifndef VIXL_AARCH64_SIMULATOR_AARCH64_H_ 28d3832965c62a8ad461b9ea9eb0994ca6b0a3da2cAlexandre Rames#define VIXL_AARCH64_SIMULATOR_AARCH64_H_ 29ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 30b49bdb7996e603555eba4c8b56c7325e3e737ab6Alexandre Rames#include "../globals-vixl.h" 31b49bdb7996e603555eba4c8b56c7325e3e737ab6Alexandre Rames#include "../utils-vixl.h" 32b68bacb75c1ab265fc539afa93964c7f51f35589Alexandre Rames 33b49bdb7996e603555eba4c8b56c7325e3e737ab6Alexandre Rames#include "abi-aarch64.h" 34b49bdb7996e603555eba4c8b56c7325e3e737ab6Alexandre Rames#include "disasm-aarch64.h" 35b49bdb7996e603555eba4c8b56c7325e3e737ab6Alexandre Rames#include "instructions-aarch64.h" 36b49bdb7996e603555eba4c8b56c7325e3e737ab6Alexandre Rames#include "instrument-aarch64.h" 37b49bdb7996e603555eba4c8b56c7325e3e737ab6Alexandre Rames#include "simulator-constants-aarch64.h" 38ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 39a4055d25c688d1397fc369a40abf57fa4f1ab805Pierre Langlois#ifdef VIXL_INCLUDE_SIMULATOR_AARCH64 40a4055d25c688d1397fc369a40abf57fa4f1ab805Pierre Langlois 41064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames// These are only used for the ABI feature, and depend on checks performed for 42064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames// it. 43ca73ba046c11d65b6dce59cfd26847d14aba06abAlexandre Rames#ifdef VIXL_HAS_ABI_SUPPORT 44064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames#include <tuple> 45064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames#if __cplusplus >= 201402L 46064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames// Required for `std::index_sequence` 47064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames#include <utility> 48064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames#endif 49064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames#endif 50064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames 51ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlnamespace vixl { 5288c46b84df005638546de5e4e965bdcc31352f48Pierre Langloisnamespace aarch64 { 53ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 546e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl// Assemble the specified IEEE-754 components into the target type and apply 556e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl// appropriate rounding. 566e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl// sign: 0 = positive, 1 = negative 576e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl// exponent: Unbiased IEEE-754 exponent. 586e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl// mantissa: The mantissa of the input. The top bit (which is not encoded for 596e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl// normal IEEE-754 values) must not be omitted. This bit has the 606e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl// value 'pow(2, exponent)'. 616e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl// 626e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl// The input value is assumed to be a normalized value. That is, the input may 636e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl// not be infinity or NaN. If the source value is subnormal, it must be 646e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl// normalized before calling this function such that the highest set bit in the 656e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl// mantissa has the value 'pow(2, exponent)'. 666e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl// 676e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl// Callers should use FPRoundToFloat or FPRoundToDouble directly, rather than 686e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl// calling a templated FPRound. 696e2c8275d5f34a531fe1eef7a7aa877601be8558armvixltemplate <class T, int ebits, int mbits> 700f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixlT FPRound(int64_t sign, 710f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl int64_t exponent, 720f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl uint64_t mantissa, 730f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl FPRounding round_mode) { 746e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl VIXL_ASSERT((sign == 0) || (sign == 1)); 756e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 766e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // Only FPTieEven and FPRoundOdd rounding modes are implemented. 776e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl VIXL_ASSERT((round_mode == FPTieEven) || (round_mode == FPRoundOdd)); 786e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 796e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // Rounding can promote subnormals to normals, and normals to infinities. For 806e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // example, a double with exponent 127 (FLT_MAX_EXP) would appear to be 816e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // encodable as a float, but rounding based on the low-order mantissa bits 826e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // could make it overflow. With ties-to-even rounding, this value would become 836e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // an infinity. 846e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 856e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // ---- Rounding Method ---- 866e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // 876e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // The exponent is irrelevant in the rounding operation, so we treat the 886e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // lowest-order bit that will fit into the result ('onebit') as having 896e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // the value '1'. Similarly, the highest-order bit that won't fit into 906e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // the result ('halfbit') has the value '0.5'. The 'point' sits between 916e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // 'onebit' and 'halfbit': 926e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // 936e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // These bits fit into the result. 946e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // |---------------------| 956e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // mantissa = 0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 966e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // || 976e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // / | 986e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // / halfbit 996e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // onebit 1006e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // 1016e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // For subnormal outputs, the range of representable bits is smaller and 1026e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // the position of onebit and halfbit depends on the exponent of the 1036e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // input, but the method is otherwise similar. 1046e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // 1056e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // onebit(frac) 1066e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // | 1076e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // | halfbit(frac) halfbit(adjusted) 1086e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // | / / 1096e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // | | | 1106e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // 0b00.0 (exact) -> 0b00.0 (exact) -> 0b00 1116e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // 0b00.0... -> 0b00.0... -> 0b00 1126e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // 0b00.1 (exact) -> 0b00.0111..111 -> 0b00 1136e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // 0b00.1... -> 0b00.1... -> 0b01 1146e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // 0b01.0 (exact) -> 0b01.0 (exact) -> 0b01 1156e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // 0b01.0... -> 0b01.0... -> 0b01 1166e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // 0b01.1 (exact) -> 0b01.1 (exact) -> 0b10 1176e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // 0b01.1... -> 0b01.1... -> 0b10 1186e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // 0b10.0 (exact) -> 0b10.0 (exact) -> 0b10 1196e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // 0b10.0... -> 0b10.0... -> 0b10 1206e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // 0b10.1 (exact) -> 0b10.0111..111 -> 0b10 1216e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // 0b10.1... -> 0b10.1... -> 0b11 1226e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // 0b11.0 (exact) -> 0b11.0 (exact) -> 0b11 1236e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // ... / | / | 1246e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // / | / | 1256e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // / | 1266e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // adjusted = frac - (halfbit(mantissa) & ~onebit(frac)); / | 1276e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // 1286e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // mantissa = (mantissa >> shift) + halfbit(adjusted); 1296e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 1306e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl static const int mantissa_offset = 0; 1316e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl static const int exponent_offset = mantissa_offset + mbits; 1326e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl static const int sign_offset = exponent_offset + ebits; 1336e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl VIXL_ASSERT(sign_offset == (sizeof(T) * 8 - 1)); 1346e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 1356e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // Bail out early for zero inputs. 1366e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if (mantissa == 0) { 137db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl return static_cast<T>(sign << sign_offset); 1386e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 1396e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 1406e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // If all bits in the exponent are set, the value is infinite or NaN. 1416e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // This is true for all binary IEEE-754 formats. 1426e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl static const int infinite_exponent = (1 << ebits) - 1; 1436e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl static const int max_normal_exponent = infinite_exponent - 1; 1446e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 1456e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // Apply the exponent bias to encode it for the result. Doing this early makes 1466e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // it easy to detect values that will be infinite or subnormal. 1476e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl exponent += max_normal_exponent >> 1; 1486e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 1496e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if (exponent > max_normal_exponent) { 1506e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // Overflow: the input is too large for the result type to represent. 1516e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if (round_mode == FPTieEven) { 1526e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // FPTieEven rounding mode handles overflows using infinities. 1536e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl exponent = infinite_exponent; 1546e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl mantissa = 0; 1556e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } else { 1566e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl VIXL_ASSERT(round_mode == FPRoundOdd); 1576e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // FPRoundOdd rounding mode handles overflows using the largest magnitude 1586e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // normal number. 1596e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl exponent = max_normal_exponent; 1606e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl mantissa = (UINT64_C(1) << exponent_offset) - 1; 1616e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 162db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl return static_cast<T>((sign << sign_offset) | 163db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl (exponent << exponent_offset) | 164db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl (mantissa << mantissa_offset)); 1656e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 1666e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 1676e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // Calculate the shift required to move the top mantissa bit to the proper 1686e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // place in the destination type. 1696e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl const int highest_significant_bit = 63 - CountLeadingZeros(mantissa); 1706e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl int shift = highest_significant_bit - mbits; 1716e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 1726e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if (exponent <= 0) { 1736e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // The output will be subnormal (before rounding). 1746e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // For subnormal outputs, the shift must be adjusted by the exponent. The +1 1756e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // is necessary because the exponent of a subnormal value (encoded as 0) is 1766e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // the same as the exponent of the smallest normal value (encoded as 1). 1776e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl shift += -exponent + 1; 1786e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 1796e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // Handle inputs that would produce a zero output. 1806e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // 1816e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // Shifts higher than highest_significant_bit+1 will always produce a zero 1826e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // result. A shift of exactly highest_significant_bit+1 might produce a 1836e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // non-zero result after rounding. 1846e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if (shift > (highest_significant_bit + 1)) { 1856e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if (round_mode == FPTieEven) { 1866e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // The result will always be +/-0.0. 187db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl return static_cast<T>(sign << sign_offset); 1886e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } else { 1896e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl VIXL_ASSERT(round_mode == FPRoundOdd); 1906e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl VIXL_ASSERT(mantissa != 0); 1916e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // For FPRoundOdd, if the mantissa is too small to represent and 1926e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // non-zero return the next "odd" value. 193db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl return static_cast<T>((sign << sign_offset) | 1); 1946e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 1956e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 1966e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 1976e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // Properly encode the exponent for a subnormal output. 1986e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl exponent = 0; 1996e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } else { 2006e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // Clear the topmost mantissa bit, since this is not encoded in IEEE-754 2016e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // normal values. 2026e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl mantissa &= ~(UINT64_C(1) << highest_significant_bit); 2036e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 2046e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 2056e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if (shift > 0) { 2066e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if (round_mode == FPTieEven) { 2076e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // We have to shift the mantissa to the right. Some precision is lost, so 2086e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // we need to apply rounding. 2096e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl uint64_t onebit_mantissa = (mantissa >> (shift)) & 1; 2100f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl uint64_t halfbit_mantissa = (mantissa >> (shift - 1)) & 1; 2116e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl uint64_t adjustment = (halfbit_mantissa & ~onebit_mantissa); 2126e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl uint64_t adjusted = mantissa - adjustment; 2130f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl T halfbit_adjusted = (adjusted >> (shift - 1)) & 1; 2146e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 2150f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl T result = 2160f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl static_cast<T>((sign << sign_offset) | (exponent << exponent_offset) | 2170f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl ((mantissa >> shift) << mantissa_offset)); 2186e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 2196e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // A very large mantissa can overflow during rounding. If this happens, 2206e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // the exponent should be incremented and the mantissa set to 1.0 2216e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // (encoded as 0). Applying halfbit_adjusted after assembling the float 2226e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // has the nice side-effect that this case is handled for free. 2236e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // 2246e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // This also handles cases where a very large finite value overflows to 2256e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // infinity, or where a very large subnormal value overflows to become 2266e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // normal. 2276e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return result + halfbit_adjusted; 2286e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } else { 2296e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl VIXL_ASSERT(round_mode == FPRoundOdd); 2306e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // If any bits at position halfbit or below are set, onebit (ie. the 2316e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // bottom bit of the resulting mantissa) must be set. 2326e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl uint64_t fractional_bits = mantissa & ((UINT64_C(1) << shift) - 1); 2336e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if (fractional_bits != 0) { 2346e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl mantissa |= UINT64_C(1) << shift; 2356e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 2366e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 237db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl return static_cast<T>((sign << sign_offset) | 238db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl (exponent << exponent_offset) | 239db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl ((mantissa >> shift) << mantissa_offset)); 2406e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 2416e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } else { 2426e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // We have to shift the mantissa to the left (or not at all). The input 2436e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // mantissa is exactly representable in the output mantissa, so apply no 2446e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // rounding correction. 245db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl return static_cast<T>((sign << sign_offset) | 246db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl (exponent << exponent_offset) | 247db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl ((mantissa << -shift) << mantissa_offset)); 2486e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 2496e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl} 2506e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 2515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 2525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl// Representation of memory, with typed getters and setters for access. 2535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlclass Memory { 2545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl public: 2555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl template <typename T> 2565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl static T AddressUntag(T address) { 2575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Cast the address using a C-style cast. A reinterpret_cast would be 2585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // appropriate, but it can't cast one integral type to another. 2595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t bits = (uint64_t)address; 2605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return (T)(bits & ~kAddressTagMask); 2615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 2625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 2635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl template <typename T, typename A> 2645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl static T Read(A address) { 2655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl T value; 2665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl address = AddressUntag(address); 2675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT((sizeof(value) == 1) || (sizeof(value) == 2) || 2685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl (sizeof(value) == 4) || (sizeof(value) == 8) || 2695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl (sizeof(value) == 16)); 2700f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl memcpy(&value, reinterpret_cast<const char*>(address), sizeof(value)); 2715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return value; 2725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 2735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 2745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl template <typename T, typename A> 2755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl static void Write(A address, T value) { 2765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl address = AddressUntag(address); 2775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT((sizeof(value) == 1) || (sizeof(value) == 2) || 2785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl (sizeof(value) == 4) || (sizeof(value) == 8) || 2795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl (sizeof(value) == 16)); 2800f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl memcpy(reinterpret_cast<char*>(address), &value, sizeof(value)); 2815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 2825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl}; 2835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 2845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl// Represent a register (r0-r31, v0-v31). 2850f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixltemplate <int kSizeInBytes> 2865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlclass SimRegisterBase { 2875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl public: 2885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimRegisterBase() : written_since_last_log_(false) {} 2895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 2905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Write the specified value. The value is zero-extended if necessary. 2910f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl template <typename T> 29288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void Write(T new_value) { 2935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_STATIC_ASSERT(sizeof(new_value) <= kSizeInBytes); 2945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (sizeof(new_value) < kSizeInBytes) { 2955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // All AArch64 registers are zero-extending. 2965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl memset(value_ + sizeof(new_value), 0, kSizeInBytes - sizeof(new_value)); 2975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 2985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl memcpy(value_, &new_value, sizeof(new_value)); 2995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl NotifyRegisterWrite(); 3005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 30188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois template <typename T> 30288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("Write", void Set(T new_value)) { 30388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois Write(new_value); 30488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 3055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 3065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Insert a typed value into a register, leaving the rest of the register 3075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // unchanged. The lane parameter indicates where in the register the value 3085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // should be inserted, in the range [ 0, sizeof(value_) / sizeof(T) ), where 3095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // 0 represents the least significant bits. 3100f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl template <typename T> 3115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void Insert(int lane, T new_value) { 3125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(lane >= 0); 3130f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl VIXL_ASSERT((sizeof(new_value) + (lane * sizeof(new_value))) <= 3140f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl kSizeInBytes); 3155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl memcpy(&value_[lane * sizeof(new_value)], &new_value, sizeof(new_value)); 3165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl NotifyRegisterWrite(); 3175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 3185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 31988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois // Get the value as the specified type. The value is truncated if necessary. 32088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois template <typename T> 32188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois T Get() const { 32288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return GetLane<T>(0); 32388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 32488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois 32588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois // Get the lane value as the specified type. The value is truncated if 32688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois // necessary. 3270f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl template <typename T> 32888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois T GetLane(int lane) const { 3295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl T result; 3305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(lane >= 0); 3315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT((sizeof(result) + (lane * sizeof(result))) <= kSizeInBytes); 3325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl memcpy(&result, &value_[lane * sizeof(result)], sizeof(result)); 3335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return result; 3345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 33588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois template <typename T> 33688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("GetLane", T Get(int lane) const) { 33788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return GetLane(lane); 33888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 3395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 3405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // TODO: Make this return a map of updated bytes, so that we can highlight 3415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // updated lanes for load-and-insert. (That never happens for scalar code, but 3425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // NEON has some instructions that can update individual lanes.) 3430f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl bool WrittenSinceLastLog() const { return written_since_last_log_; } 3445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 3450f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl void NotifyRegisterLogged() { written_since_last_log_ = false; } 3465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 3475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl protected: 3485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint8_t value_[kSizeInBytes]; 3495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 3505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Helpers to aid with register tracing. 3515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl bool written_since_last_log_; 3525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 3530f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl void NotifyRegisterWrite() { written_since_last_log_ = true; } 3545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl}; 3550f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixltypedef SimRegisterBase<kXRegSizeInBytes> SimRegister; // r0-r31 3560f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixltypedef SimRegisterBase<kQRegSizeInBytes> SimVRegister; // v0-v31 3575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 3585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl// Representation of a vector register, with typed getters and setters for lanes 3595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl// and additional information to represent lane state. 3605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlclass LogicVRegister { 3615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl public: 36260241a544be0ebf48347789bf0ec268414364627Vincent Belliard inline LogicVRegister( 36360241a544be0ebf48347789bf0ec268414364627Vincent Belliard SimVRegister& other) // NOLINT(runtime/references)(runtime/explicit) 3645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl : register_(other) { 3655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (unsigned i = 0; i < sizeof(saturated_) / sizeof(saturated_[0]); i++) { 3665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl saturated_[i] = kNotSaturated; 3675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 3685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (unsigned i = 0; i < sizeof(round_) / sizeof(round_[0]); i++) { 3695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl round_[i] = 0; 3705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 3715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 3725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 3735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int64_t Int(VectorFormat vform, int index) const { 3745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int64_t element; 3755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl switch (LaneSizeInBitsFromFormat(vform)) { 3760f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 8: 37788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois element = register_.GetLane<int8_t>(index); 3780f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 3790f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 16: 38088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois element = register_.GetLane<int16_t>(index); 3810f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 3820f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 32: 38388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois element = register_.GetLane<int32_t>(index); 3840f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 3850f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 64: 38688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois element = register_.GetLane<int64_t>(index); 3870f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 3880f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl default: 3890f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl VIXL_UNREACHABLE(); 3900f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl return 0; 3915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 3925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return element; 3935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 3945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 3955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t Uint(VectorFormat vform, int index) const { 3965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t element; 3975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl switch (LaneSizeInBitsFromFormat(vform)) { 3980f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 8: 39988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois element = register_.GetLane<uint8_t>(index); 4000f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 4010f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 16: 40288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois element = register_.GetLane<uint16_t>(index); 4030f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 4040f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 32: 40588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois element = register_.GetLane<uint32_t>(index); 4060f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 4070f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 64: 40888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois element = register_.GetLane<uint64_t>(index); 4090f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 4100f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl default: 4110f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl VIXL_UNREACHABLE(); 4120f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl return 0; 4135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 4145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return element; 4155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 4165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 4175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t UintLeftJustified(VectorFormat vform, int index) const { 4185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return Uint(vform, index) << (64 - LaneSizeInBitsFromFormat(vform)); 4195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 4205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 4215b24fb388927a1f1801a15d460d4c9448f7aa733Martyn Capewell int64_t IntLeftJustified(VectorFormat vform, int index) const { 4225b24fb388927a1f1801a15d460d4c9448f7aa733Martyn Capewell uint64_t value = UintLeftJustified(vform, index); 4235b24fb388927a1f1801a15d460d4c9448f7aa733Martyn Capewell int64_t result; 4245b24fb388927a1f1801a15d460d4c9448f7aa733Martyn Capewell memcpy(&result, &value, sizeof(result)); 4255b24fb388927a1f1801a15d460d4c9448f7aa733Martyn Capewell return result; 4265b24fb388927a1f1801a15d460d4c9448f7aa733Martyn Capewell } 4275b24fb388927a1f1801a15d460d4c9448f7aa733Martyn Capewell 4285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void SetInt(VectorFormat vform, int index, int64_t value) const { 4295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl switch (LaneSizeInBitsFromFormat(vform)) { 4300f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 8: 4310f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl register_.Insert(index, static_cast<int8_t>(value)); 4320f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 4330f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 16: 4340f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl register_.Insert(index, static_cast<int16_t>(value)); 4350f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 4360f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 32: 4370f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl register_.Insert(index, static_cast<int32_t>(value)); 4380f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 4390f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 64: 4400f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl register_.Insert(index, static_cast<int64_t>(value)); 4410f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 4420f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl default: 4430f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl VIXL_UNREACHABLE(); 4440f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl return; 4455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 4465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 4475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 448b953ea8255b36e27834f17941429cd17af12f6f2Martyn Capewell void SetIntArray(VectorFormat vform, const int64_t* src) const { 449b953ea8255b36e27834f17941429cd17af12f6f2Martyn Capewell ClearForWrite(vform); 450b953ea8255b36e27834f17941429cd17af12f6f2Martyn Capewell for (int i = 0; i < LaneCountFromFormat(vform); i++) { 451b953ea8255b36e27834f17941429cd17af12f6f2Martyn Capewell SetInt(vform, i, src[i]); 452b953ea8255b36e27834f17941429cd17af12f6f2Martyn Capewell } 453b953ea8255b36e27834f17941429cd17af12f6f2Martyn Capewell } 454b953ea8255b36e27834f17941429cd17af12f6f2Martyn Capewell 4555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void SetUint(VectorFormat vform, int index, uint64_t value) const { 4565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl switch (LaneSizeInBitsFromFormat(vform)) { 4570f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 8: 4580f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl register_.Insert(index, static_cast<uint8_t>(value)); 4590f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 4600f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 16: 4610f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl register_.Insert(index, static_cast<uint16_t>(value)); 4620f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 4630f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 32: 4640f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl register_.Insert(index, static_cast<uint32_t>(value)); 4650f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 4660f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 64: 4670f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl register_.Insert(index, static_cast<uint64_t>(value)); 4680f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 4690f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl default: 4700f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl VIXL_UNREACHABLE(); 4710f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl return; 4725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 4735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 4745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 475b953ea8255b36e27834f17941429cd17af12f6f2Martyn Capewell void SetUintArray(VectorFormat vform, const uint64_t* src) const { 476b953ea8255b36e27834f17941429cd17af12f6f2Martyn Capewell ClearForWrite(vform); 477b953ea8255b36e27834f17941429cd17af12f6f2Martyn Capewell for (int i = 0; i < LaneCountFromFormat(vform); i++) { 478b953ea8255b36e27834f17941429cd17af12f6f2Martyn Capewell SetUint(vform, i, src[i]); 479b953ea8255b36e27834f17941429cd17af12f6f2Martyn Capewell } 480b953ea8255b36e27834f17941429cd17af12f6f2Martyn Capewell } 481b953ea8255b36e27834f17941429cd17af12f6f2Martyn Capewell 4825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void ReadUintFromMem(VectorFormat vform, int index, uint64_t addr) const { 4835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl switch (LaneSizeInBitsFromFormat(vform)) { 4840f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 8: 4850f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl register_.Insert(index, Memory::Read<uint8_t>(addr)); 4860f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 4870f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 16: 4880f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl register_.Insert(index, Memory::Read<uint16_t>(addr)); 4890f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 4900f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 32: 4910f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl register_.Insert(index, Memory::Read<uint32_t>(addr)); 4920f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 4930f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 64: 4940f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl register_.Insert(index, Memory::Read<uint64_t>(addr)); 4950f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 4960f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl default: 4970f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl VIXL_UNREACHABLE(); 4980f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl return; 4995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 5005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 5015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 5025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void WriteUintToMem(VectorFormat vform, int index, uint64_t addr) const { 503db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl uint64_t value = Uint(vform, index); 5045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl switch (LaneSizeInBitsFromFormat(vform)) { 5050f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 8: 5060f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl Memory::Write(addr, static_cast<uint8_t>(value)); 5070f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 5080f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 16: 5090f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl Memory::Write(addr, static_cast<uint16_t>(value)); 5100f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 5110f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 32: 5120f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl Memory::Write(addr, static_cast<uint32_t>(value)); 5130f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 5140f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 64: 5150f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl Memory::Write(addr, value); 5160f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 5175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 5185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 5195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 5205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl template <typename T> 5215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl T Float(int index) const { 52288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return register_.GetLane<T>(index); 5235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 5245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 5255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl template <typename T> 5265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void SetFloat(int index, T value) const { 5275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl register_.Insert(index, value); 5285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 5295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 5305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // When setting a result in a register of size less than Q, the top bits of 5315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // the Q register must be cleared. 5325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void ClearForWrite(VectorFormat vform) const { 5335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl unsigned size = RegisterSizeInBytesFromFormat(vform); 5345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (unsigned i = size; i < kQRegSizeInBytes; i++) { 5355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SetUint(kFormat16B, i, 0); 5365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 5375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 5385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 5395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Saturation state for each lane of a vector. 5405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl enum Saturation { 5415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kNotSaturated = 0, 5425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kSignedSatPositive = 1 << 0, 5435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kSignedSatNegative = 1 << 1, 5445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kSignedSatMask = kSignedSatPositive | kSignedSatNegative, 5455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kSignedSatUndefined = kSignedSatMask, 5465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kUnsignedSatPositive = 1 << 2, 5475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kUnsignedSatNegative = 1 << 3, 5485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kUnsignedSatMask = kUnsignedSatPositive | kUnsignedSatNegative, 5495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kUnsignedSatUndefined = kUnsignedSatMask 5505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl }; 5515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 5525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Getters for saturation state. 5535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Saturation GetSignedSaturation(int index) { 5545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return static_cast<Saturation>(saturated_[index] & kSignedSatMask); 5555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 5565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 5575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Saturation GetUnsignedSaturation(int index) { 5585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return static_cast<Saturation>(saturated_[index] & kUnsignedSatMask); 5595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 5605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 5615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Setters for saturation state. 5620f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl void ClearSat(int index) { saturated_[index] = kNotSaturated; } 5635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 5645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void SetSignedSat(int index, bool positive) { 5655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SetSatFlag(index, positive ? kSignedSatPositive : kSignedSatNegative); 5665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 5675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 5685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void SetUnsignedSat(int index, bool positive) { 5695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SetSatFlag(index, positive ? kUnsignedSatPositive : kUnsignedSatNegative); 5705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 5715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 5725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void SetSatFlag(int index, Saturation sat) { 5735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl saturated_[index] = static_cast<Saturation>(saturated_[index] | sat); 5745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT((sat & kUnsignedSatMask) != kUnsignedSatUndefined); 5755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT((sat & kSignedSatMask) != kSignedSatUndefined); 5765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 5775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 5785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Saturate lanes of a vector based on saturation state. 5795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister& SignedSaturate(VectorFormat vform) { 5805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 5815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Saturation sat = GetSignedSaturation(i); 5825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (sat == kSignedSatPositive) { 5835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SetInt(vform, i, MaxIntFromFormat(vform)); 5845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else if (sat == kSignedSatNegative) { 5855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SetInt(vform, i, MinIntFromFormat(vform)); 5865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 5875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 5885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return *this; 5895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 5905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 5915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister& UnsignedSaturate(VectorFormat vform) { 5925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 5935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Saturation sat = GetUnsignedSaturation(i); 5945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (sat == kUnsignedSatPositive) { 5955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SetUint(vform, i, MaxUintFromFormat(vform)); 5965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else if (sat == kUnsignedSatNegative) { 5975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SetUint(vform, i, 0); 5985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 5995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 6005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return *this; 6015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 6025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 6035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Getter for rounding state. 6040f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl bool GetRounding(int index) { return round_[index]; } 6055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 6065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Setter for rounding state. 6070f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl void SetRounding(int index, bool round) { round_[index] = round; } 6085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 6095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Round lanes of a vector based on rounding state. 6105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister& Round(VectorFormat vform) { 6115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 6125b24fb388927a1f1801a15d460d4c9448f7aa733Martyn Capewell SetUint(vform, i, Uint(vform, i) + (GetRounding(i) ? 1 : 0)); 6135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 6145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return *this; 6155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 6165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 6175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Unsigned halve lanes of a vector, and use the saturation state to set the 6185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // top bit. 6195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister& Uhalve(VectorFormat vform) { 6205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 6215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t val = Uint(vform, i); 6225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SetRounding(i, (val & 1) == 1); 6235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl val >>= 1; 6245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (GetUnsignedSaturation(i) != kNotSaturated) { 6255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // If the operation causes unsigned saturation, the bit shifted into the 6265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // most significant bit must be set. 6275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl val |= (MaxUintFromFormat(vform) >> 1) + 1; 6285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 6295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SetInt(vform, i, val); 6305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 6315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return *this; 6325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 6335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 6345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Signed halve lanes of a vector, and use the carry state to set the top bit. 6355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister& Halve(VectorFormat vform) { 6365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 6375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int64_t val = Int(vform, i); 6385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SetRounding(i, (val & 1) == 1); 6395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl val >>= 1; 6405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (GetSignedSaturation(i) != kNotSaturated) { 6415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // If the operation causes signed saturation, the sign bit must be 6425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // inverted. 6435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl val ^= (MaxUintFromFormat(vform) >> 1) + 1; 6445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 6455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SetInt(vform, i, val); 6465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 6475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return *this; 6485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 6495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 6505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl private: 6515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister& register_; 6525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 6535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Allocate one saturation state entry per lane; largest register is type Q, 6545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // and lanes can be a minimum of one byte wide. 6555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Saturation saturated_[kQRegSizeInBytes]; 6565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 6575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Allocate one rounding state entry per lane. 6585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl bool round_[kQRegSizeInBytes]; 6595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl}; 6605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 661578645f14e122d2b87d907e298cda7e7d0babf1farmvixl// The proper way to initialize a simulated system register (such as NZCV) is as 662578645f14e122d2b87d907e298cda7e7d0babf1farmvixl// follows: 663578645f14e122d2b87d907e298cda7e7d0babf1farmvixl// SimSystemRegister nzcv = SimSystemRegister::DefaultValueFor(NZCV); 664578645f14e122d2b87d907e298cda7e7d0babf1farmvixlclass SimSystemRegister { 665578645f14e122d2b87d907e298cda7e7d0babf1farmvixl public: 666578645f14e122d2b87d907e298cda7e7d0babf1farmvixl // The default constructor represents a register which has no writable bits. 667578645f14e122d2b87d907e298cda7e7d0babf1farmvixl // It is not possible to set its value to anything other than 0. 6680f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl SimSystemRegister() : value_(0), write_ignore_mask_(0xffffffff) {} 669578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 67088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois uint32_t GetRawValue() const { return value_; } 67188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("GetRawValue", uint32_t RawValue() const) { 67288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return GetRawValue(); 67388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 674578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 675330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl void SetRawValue(uint32_t new_value) { 676578645f14e122d2b87d907e298cda7e7d0babf1farmvixl value_ = (value_ & write_ignore_mask_) | (new_value & ~write_ignore_mask_); 677578645f14e122d2b87d907e298cda7e7d0babf1farmvixl } 678578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 67988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois uint32_t ExtractBits(int msb, int lsb) const { 68088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ExtractUnsignedBitfield32(msb, lsb, value_); 68188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 68288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ExtractBits", uint32_t Bits(int msb, int lsb) const) { 68388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ExtractBits(msb, lsb); 684578645f14e122d2b87d907e298cda7e7d0babf1farmvixl } 685578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 68688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int32_t ExtractSignedBits(int msb, int lsb) const { 68788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ExtractSignedBitfield32(msb, lsb, value_); 68888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 68988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ExtractSignedBits", 69088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int32_t SignedBits(int msb, int lsb) const) { 69188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ExtractSignedBits(msb, lsb); 692578645f14e122d2b87d907e298cda7e7d0babf1farmvixl } 693578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 694578645f14e122d2b87d907e298cda7e7d0babf1farmvixl void SetBits(int msb, int lsb, uint32_t bits); 695578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 696578645f14e122d2b87d907e298cda7e7d0babf1farmvixl // Default system register values. 697578645f14e122d2b87d907e298cda7e7d0babf1farmvixl static SimSystemRegister DefaultValueFor(SystemRegister id); 698578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 69988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois#define DEFINE_GETTER(Name, HighBit, LowBit, Func) \ 70088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois uint32_t Get##Name() const { return this->Func(HighBit, LowBit); } \ 70188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("Get" #Name, uint32_t Name() const) { return Get##Name(); } \ 702330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl void Set##Name(uint32_t bits) { SetBits(HighBit, LowBit, bits); } 7030f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl#define DEFINE_WRITE_IGNORE_MASK(Name, Mask) \ 704578645f14e122d2b87d907e298cda7e7d0babf1farmvixl static const uint32_t Name##WriteIgnoreMask = ~static_cast<uint32_t>(Mask); 705578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 706578645f14e122d2b87d907e298cda7e7d0babf1farmvixl SYSTEM_REGISTER_FIELDS_LIST(DEFINE_GETTER, DEFINE_WRITE_IGNORE_MASK) 707578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 708578645f14e122d2b87d907e298cda7e7d0babf1farmvixl#undef DEFINE_ZERO_BITS 709578645f14e122d2b87d907e298cda7e7d0babf1farmvixl#undef DEFINE_GETTER 710578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 711578645f14e122d2b87d907e298cda7e7d0babf1farmvixl protected: 712578645f14e122d2b87d907e298cda7e7d0babf1farmvixl // Most system registers only implement a few of the bits in the word. Other 713578645f14e122d2b87d907e298cda7e7d0babf1farmvixl // bits are "read-as-zero, write-ignored". The write_ignore_mask argument 714578645f14e122d2b87d907e298cda7e7d0babf1farmvixl // describes the bits which are not modifiable. 715578645f14e122d2b87d907e298cda7e7d0babf1farmvixl SimSystemRegister(uint32_t value, uint32_t write_ignore_mask) 7160f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl : value_(value), write_ignore_mask_(write_ignore_mask) {} 717578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 718578645f14e122d2b87d907e298cda7e7d0babf1farmvixl uint32_t value_; 719578645f14e122d2b87d907e298cda7e7d0babf1farmvixl uint32_t write_ignore_mask_; 720578645f14e122d2b87d907e298cda7e7d0babf1farmvixl}; 721578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 722578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 7234a102baf640077d6794c0b33bb976f94b86c532barmvixlclass SimExclusiveLocalMonitor { 7244a102baf640077d6794c0b33bb976f94b86c532barmvixl public: 7254a102baf640077d6794c0b33bb976f94b86c532barmvixl SimExclusiveLocalMonitor() : kSkipClearProbability(8), seed_(0x87654321) { 7264a102baf640077d6794c0b33bb976f94b86c532barmvixl Clear(); 7274a102baf640077d6794c0b33bb976f94b86c532barmvixl } 7284a102baf640077d6794c0b33bb976f94b86c532barmvixl 7294a102baf640077d6794c0b33bb976f94b86c532barmvixl // Clear the exclusive monitor (like clrex). 7304a102baf640077d6794c0b33bb976f94b86c532barmvixl void Clear() { 7314a102baf640077d6794c0b33bb976f94b86c532barmvixl address_ = 0; 7324a102baf640077d6794c0b33bb976f94b86c532barmvixl size_ = 0; 7334a102baf640077d6794c0b33bb976f94b86c532barmvixl } 7344a102baf640077d6794c0b33bb976f94b86c532barmvixl 7354a102baf640077d6794c0b33bb976f94b86c532barmvixl // Clear the exclusive monitor most of the time. 7364a102baf640077d6794c0b33bb976f94b86c532barmvixl void MaybeClear() { 7374a102baf640077d6794c0b33bb976f94b86c532barmvixl if ((seed_ % kSkipClearProbability) != 0) { 7384a102baf640077d6794c0b33bb976f94b86c532barmvixl Clear(); 7394a102baf640077d6794c0b33bb976f94b86c532barmvixl } 7404a102baf640077d6794c0b33bb976f94b86c532barmvixl 7414a102baf640077d6794c0b33bb976f94b86c532barmvixl // Advance seed_ using a simple linear congruential generator. 7424a102baf640077d6794c0b33bb976f94b86c532barmvixl seed_ = (seed_ * 48271) % 2147483647; 7434a102baf640077d6794c0b33bb976f94b86c532barmvixl } 7444a102baf640077d6794c0b33bb976f94b86c532barmvixl 7454a102baf640077d6794c0b33bb976f94b86c532barmvixl // Mark the address range for exclusive access (like load-exclusive). 746330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl void MarkExclusive(uint64_t address, size_t size) { 747330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl address_ = address; 7484a102baf640077d6794c0b33bb976f94b86c532barmvixl size_ = size; 7494a102baf640077d6794c0b33bb976f94b86c532barmvixl } 7504a102baf640077d6794c0b33bb976f94b86c532barmvixl 7514a102baf640077d6794c0b33bb976f94b86c532barmvixl // Return true if the address range is marked (like store-exclusive). 7524a102baf640077d6794c0b33bb976f94b86c532barmvixl // This helper doesn't implicitly clear the monitor. 753330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl bool IsExclusive(uint64_t address, size_t size) { 7544a102baf640077d6794c0b33bb976f94b86c532barmvixl VIXL_ASSERT(size > 0); 7554a102baf640077d6794c0b33bb976f94b86c532barmvixl // Be pedantic: Require both the address and the size to match. 756330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl return (size == size_) && (address == address_); 7574a102baf640077d6794c0b33bb976f94b86c532barmvixl } 7584a102baf640077d6794c0b33bb976f94b86c532barmvixl 7594a102baf640077d6794c0b33bb976f94b86c532barmvixl private: 760330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl uint64_t address_; 7614a102baf640077d6794c0b33bb976f94b86c532barmvixl size_t size_; 7624a102baf640077d6794c0b33bb976f94b86c532barmvixl 7634a102baf640077d6794c0b33bb976f94b86c532barmvixl const int kSkipClearProbability; 7644a102baf640077d6794c0b33bb976f94b86c532barmvixl uint32_t seed_; 7654a102baf640077d6794c0b33bb976f94b86c532barmvixl}; 7664a102baf640077d6794c0b33bb976f94b86c532barmvixl 7674a102baf640077d6794c0b33bb976f94b86c532barmvixl 7684a102baf640077d6794c0b33bb976f94b86c532barmvixl// We can't accurate simulate the global monitor since it depends on external 7694a102baf640077d6794c0b33bb976f94b86c532barmvixl// influences. Instead, this implementation occasionally causes accesses to 7704a102baf640077d6794c0b33bb976f94b86c532barmvixl// fail, according to kPassProbability. 7714a102baf640077d6794c0b33bb976f94b86c532barmvixlclass SimExclusiveGlobalMonitor { 7724a102baf640077d6794c0b33bb976f94b86c532barmvixl public: 7734a102baf640077d6794c0b33bb976f94b86c532barmvixl SimExclusiveGlobalMonitor() : kPassProbability(8), seed_(0x87654321) {} 7744a102baf640077d6794c0b33bb976f94b86c532barmvixl 775330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl bool IsExclusive(uint64_t address, size_t size) { 776db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl USE(address, size); 7774a102baf640077d6794c0b33bb976f94b86c532barmvixl 7784a102baf640077d6794c0b33bb976f94b86c532barmvixl bool pass = (seed_ % kPassProbability) != 0; 7794a102baf640077d6794c0b33bb976f94b86c532barmvixl // Advance seed_ using a simple linear congruential generator. 7804a102baf640077d6794c0b33bb976f94b86c532barmvixl seed_ = (seed_ * 48271) % 2147483647; 7814a102baf640077d6794c0b33bb976f94b86c532barmvixl return pass; 7824a102baf640077d6794c0b33bb976f94b86c532barmvixl } 7834a102baf640077d6794c0b33bb976f94b86c532barmvixl 7844a102baf640077d6794c0b33bb976f94b86c532barmvixl private: 7854a102baf640077d6794c0b33bb976f94b86c532barmvixl const int kPassProbability; 7864a102baf640077d6794c0b33bb976f94b86c532barmvixl uint32_t seed_; 7874a102baf640077d6794c0b33bb976f94b86c532barmvixl}; 7884a102baf640077d6794c0b33bb976f94b86c532barmvixl 7894a102baf640077d6794c0b33bb976f94b86c532barmvixl 790ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlclass Simulator : public DecoderVisitor { 791ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl public: 792ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl explicit Simulator(Decoder* decoder, FILE* stream = stdout); 793ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl ~Simulator(); 794ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 795ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl void ResetState(); 796ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 797ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // Run the simulator. 798ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl virtual void Run(); 799c68cb64496485710cdb5b8480f8fee287058c93farmvixl void RunFrom(const Instruction* first); 800ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 801f75ec85cb9c8690e42125aea3dac1e57d46c21daAlexandre Rames 802f75ec85cb9c8690e42125aea3dac1e57d46c21daAlexandre Rames#if defined(VIXL_HAS_ABI_SUPPORT) && __cplusplus >= 201103L && \ 803f75ec85cb9c8690e42125aea3dac1e57d46c21daAlexandre Rames (defined(__clang__) || GCC_VERSION_OR_NEWER(4, 9, 1)) 804f75ec85cb9c8690e42125aea3dac1e57d46c21daAlexandre Rames // Templated `RunFrom` version taking care of passing arguments and returning 805f75ec85cb9c8690e42125aea3dac1e57d46c21daAlexandre Rames // the result value. 806f75ec85cb9c8690e42125aea3dac1e57d46c21daAlexandre Rames // This allows code like: 807f75ec85cb9c8690e42125aea3dac1e57d46c21daAlexandre Rames // int32_t res = simulator.RunFrom<int32_t, int32_t>(GenerateCode(), 808f75ec85cb9c8690e42125aea3dac1e57d46c21daAlexandre Rames // 0x123); 809f75ec85cb9c8690e42125aea3dac1e57d46c21daAlexandre Rames // It requires VIXL's ABI features, and C++11 or greater. 810f75ec85cb9c8690e42125aea3dac1e57d46c21daAlexandre Rames // Also, the initialisation of tuples is incorrect in GCC before 4.9.1: 811f75ec85cb9c8690e42125aea3dac1e57d46c21daAlexandre Rames // https://gcc.gnu.org/bugzilla/show_bug.cgi?id=51253 812f75ec85cb9c8690e42125aea3dac1e57d46c21daAlexandre Rames template <typename R, typename... P> 813f75ec85cb9c8690e42125aea3dac1e57d46c21daAlexandre Rames R RunFrom(const Instruction* code, P... arguments) { 814f75ec85cb9c8690e42125aea3dac1e57d46c21daAlexandre Rames return RunFromStructHelper<R, P...>::Wrapper(this, code, arguments...); 815f75ec85cb9c8690e42125aea3dac1e57d46c21daAlexandre Rames } 816f75ec85cb9c8690e42125aea3dac1e57d46c21daAlexandre Rames 817f75ec85cb9c8690e42125aea3dac1e57d46c21daAlexandre Rames template <typename R, typename... P> 818f75ec85cb9c8690e42125aea3dac1e57d46c21daAlexandre Rames struct RunFromStructHelper { 819f75ec85cb9c8690e42125aea3dac1e57d46c21daAlexandre Rames static R Wrapper(Simulator* simulator, 820f75ec85cb9c8690e42125aea3dac1e57d46c21daAlexandre Rames const Instruction* code, 821f75ec85cb9c8690e42125aea3dac1e57d46c21daAlexandre Rames P... arguments) { 822f75ec85cb9c8690e42125aea3dac1e57d46c21daAlexandre Rames ABI abi; 823f75ec85cb9c8690e42125aea3dac1e57d46c21daAlexandre Rames std::tuple<P...> unused_tuple{ 824f75ec85cb9c8690e42125aea3dac1e57d46c21daAlexandre Rames // TODO: We currently do not support arguments passed on the stack. We 825f75ec85cb9c8690e42125aea3dac1e57d46c21daAlexandre Rames // could do so by using `WriteGenericOperand()` here, but may need to 826f75ec85cb9c8690e42125aea3dac1e57d46c21daAlexandre Rames // add features to handle situations where the stack is or is not set 827f75ec85cb9c8690e42125aea3dac1e57d46c21daAlexandre Rames // up. 828f75ec85cb9c8690e42125aea3dac1e57d46c21daAlexandre Rames (simulator->WriteCPURegister(abi.GetNextParameterGenericOperand<P>() 829f75ec85cb9c8690e42125aea3dac1e57d46c21daAlexandre Rames .GetCPURegister(), 830f75ec85cb9c8690e42125aea3dac1e57d46c21daAlexandre Rames arguments), 831f75ec85cb9c8690e42125aea3dac1e57d46c21daAlexandre Rames arguments)...}; 832f75ec85cb9c8690e42125aea3dac1e57d46c21daAlexandre Rames simulator->RunFrom(code); 833f75ec85cb9c8690e42125aea3dac1e57d46c21daAlexandre Rames return simulator->ReadGenericOperand<R>(abi.GetReturnGenericOperand<R>()); 834f75ec85cb9c8690e42125aea3dac1e57d46c21daAlexandre Rames } 835f75ec85cb9c8690e42125aea3dac1e57d46c21daAlexandre Rames }; 836f75ec85cb9c8690e42125aea3dac1e57d46c21daAlexandre Rames 837f75ec85cb9c8690e42125aea3dac1e57d46c21daAlexandre Rames // Partial specialization when the return type is `void`. 838f75ec85cb9c8690e42125aea3dac1e57d46c21daAlexandre Rames template <typename... P> 839f75ec85cb9c8690e42125aea3dac1e57d46c21daAlexandre Rames struct RunFromStructHelper<void, P...> { 840f75ec85cb9c8690e42125aea3dac1e57d46c21daAlexandre Rames static void Wrapper(Simulator* simulator, 841f75ec85cb9c8690e42125aea3dac1e57d46c21daAlexandre Rames const Instruction* code, 842f75ec85cb9c8690e42125aea3dac1e57d46c21daAlexandre Rames P... arguments) { 843f75ec85cb9c8690e42125aea3dac1e57d46c21daAlexandre Rames ABI abi; 844f75ec85cb9c8690e42125aea3dac1e57d46c21daAlexandre Rames std::tuple<P...> unused_tuple{ 845f75ec85cb9c8690e42125aea3dac1e57d46c21daAlexandre Rames // TODO: We currently do not support arguments passed on the stack. We 846f75ec85cb9c8690e42125aea3dac1e57d46c21daAlexandre Rames // could do so by using `WriteGenericOperand()` here, but may need to 847f75ec85cb9c8690e42125aea3dac1e57d46c21daAlexandre Rames // add features to handle situations where the stack is or is not set 848f75ec85cb9c8690e42125aea3dac1e57d46c21daAlexandre Rames // up. 849f75ec85cb9c8690e42125aea3dac1e57d46c21daAlexandre Rames (simulator->WriteCPURegister(abi.GetNextParameterGenericOperand<P>() 850f75ec85cb9c8690e42125aea3dac1e57d46c21daAlexandre Rames .GetCPURegister(), 851f75ec85cb9c8690e42125aea3dac1e57d46c21daAlexandre Rames arguments), 852f75ec85cb9c8690e42125aea3dac1e57d46c21daAlexandre Rames arguments)...}; 853f75ec85cb9c8690e42125aea3dac1e57d46c21daAlexandre Rames simulator->RunFrom(code); 854f75ec85cb9c8690e42125aea3dac1e57d46c21daAlexandre Rames } 855f75ec85cb9c8690e42125aea3dac1e57d46c21daAlexandre Rames }; 856f75ec85cb9c8690e42125aea3dac1e57d46c21daAlexandre Rames#endif 857f75ec85cb9c8690e42125aea3dac1e57d46c21daAlexandre Rames 8580f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl // Execution ends when the PC hits this address. 8590f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl static const Instruction* kEndOfSimAddress; 8600f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl 861ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // Simulation helpers. 86288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois const Instruction* ReadPc() const { return pc_; } 86388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadPc", const Instruction* pc() const) { return ReadPc(); } 86488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois 865e79723a010a6f42fe78e2515c7b0eb9308b93093Jacob Bramley enum BranchLogMode { LogBranches, NoBranchLog }; 866e79723a010a6f42fe78e2515c7b0eb9308b93093Jacob Bramley 867e79723a010a6f42fe78e2515c7b0eb9308b93093Jacob Bramley void WritePc(const Instruction* new_pc, 868e79723a010a6f42fe78e2515c7b0eb9308b93093Jacob Bramley BranchLogMode log_mode = LogBranches) { 869e79723a010a6f42fe78e2515c7b0eb9308b93093Jacob Bramley if (log_mode == LogBranches) LogTakenBranch(new_pc); 8705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl pc_ = Memory::AddressUntag(new_pc); 871ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl pc_modified_ = true; 872ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 87388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("WritePc", void set_pc(const Instruction* new_pc)) { 87488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return WritePc(new_pc); 87588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 876ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 87788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void IncrementPc() { 878ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl if (!pc_modified_) { 87988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois pc_ = pc_->GetNextInstruction(); 880ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 881ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 88288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("IncrementPc", void increment_pc()) { IncrementPc(); } 883ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 884330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl void ExecuteInstruction() { 885ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // The program counter should always be aligned. 886b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT(IsWordAligned(pc_)); 8870f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl pc_modified_ = false; 888ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl decoder_->Decode(pc_); 88988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois IncrementPc(); 8900f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogAllWrittenRegisters(); 891ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 892ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 8930f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl// Declare all Visitor functions. 8943fac43c1a101f98f116e752b80abc122d32b83acPierre Langlois#define DECLARE(A) \ 8953fac43c1a101f98f116e752b80abc122d32b83acPierre Langlois virtual void Visit##A(const Instruction* instr) VIXL_OVERRIDE; 896684cd2a7f5845539b58d0da7e012e39df49ceff0armvixl VISITOR_LIST_THAT_RETURN(DECLARE) 8970f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl#undef DECLARE 898ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 8993fac43c1a101f98f116e752b80abc122d32b83acPierre Langlois#define DECLARE(A) \ 9003fac43c1a101f98f116e752b80abc122d32b83acPierre Langlois VIXL_DEBUG_NO_RETURN virtual void Visit##A(const Instruction* instr) \ 9013fac43c1a101f98f116e752b80abc122d32b83acPierre Langlois VIXL_OVERRIDE; 902684cd2a7f5845539b58d0da7e012e39df49ceff0armvixl VISITOR_LIST_THAT_DONT_RETURN(DECLARE) 9030f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl#undef DECLARE 904684cd2a7f5845539b58d0da7e012e39df49ceff0armvixl 905684cd2a7f5845539b58d0da7e012e39df49ceff0armvixl 9064a102baf640077d6794c0b33bb976f94b86c532barmvixl // Integer register accessors. 907f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl 9084a102baf640077d6794c0b33bb976f94b86c532barmvixl // Basic accessor: Read the register as the specified type. 9090f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl template <typename T> 91088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois T ReadRegister(unsigned code, Reg31Mode r31mode = Reg31IsZeroRegister) const { 911868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames VIXL_ASSERT( 912868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames code < kNumberOfRegisters || 913868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames ((r31mode == Reg31IsZeroRegister) && (code == kSPRegInternalCode))); 914ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl if ((code == 31) && (r31mode == Reg31IsZeroRegister)) { 915f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl T result; 916f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl memset(&result, 0, sizeof(result)); 917f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl return result; 918ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 919868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames if ((r31mode == Reg31IsZeroRegister) && (code == kSPRegInternalCode)) { 920868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames code = 31; 921868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames } 9224a102baf640077d6794c0b33bb976f94b86c532barmvixl return registers_[code].Get<T>(); 923f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl } 92488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois template <typename T> 92588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadRegister", 92688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois T reg(unsigned code, Reg31Mode r31mode = Reg31IsZeroRegister) 92788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois const) { 92888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadRegister<T>(code, r31mode); 92988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 930f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl 93188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois // Common specialized accessors for the ReadRegister() template. 93288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int32_t ReadWRegister(unsigned code, 93388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois Reg31Mode r31mode = Reg31IsZeroRegister) const { 93488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadRegister<int32_t>(code, r31mode); 93588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 93688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadWRegister", 93788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int32_t wreg(unsigned code, 93888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois Reg31Mode r31mode = Reg31IsZeroRegister) const) { 93988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadWRegister(code, r31mode); 940ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 941ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 94288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int64_t ReadXRegister(unsigned code, 94388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois Reg31Mode r31mode = Reg31IsZeroRegister) const { 94488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadRegister<int64_t>(code, r31mode); 94588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 94688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadXRegister", 94788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int64_t xreg(unsigned code, 94888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois Reg31Mode r31mode = Reg31IsZeroRegister) const) { 94988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadXRegister(code, r31mode); 950f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl } 951f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl 9524a102baf640077d6794c0b33bb976f94b86c532barmvixl // As above, with parameterized size and return type. The value is 9534a102baf640077d6794c0b33bb976f94b86c532barmvixl // either zero-extended or truncated to fit, as required. 9540f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl template <typename T> 95588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois T ReadRegister(unsigned size, 95688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois unsigned code, 95788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois Reg31Mode r31mode = Reg31IsZeroRegister) const { 9584a102baf640077d6794c0b33bb976f94b86c532barmvixl uint64_t raw; 9594a102baf640077d6794c0b33bb976f94b86c532barmvixl switch (size) { 9600f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case kWRegSize: 96188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois raw = ReadRegister<uint32_t>(code, r31mode); 9620f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 9630f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case kXRegSize: 96488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois raw = ReadRegister<uint64_t>(code, r31mode); 9650f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 9664a102baf640077d6794c0b33bb976f94b86c532barmvixl default: 9674a102baf640077d6794c0b33bb976f94b86c532barmvixl VIXL_UNREACHABLE(); 9684a102baf640077d6794c0b33bb976f94b86c532barmvixl return 0; 9694a102baf640077d6794c0b33bb976f94b86c532barmvixl } 9704a102baf640077d6794c0b33bb976f94b86c532barmvixl 9714a102baf640077d6794c0b33bb976f94b86c532barmvixl T result; 9724a102baf640077d6794c0b33bb976f94b86c532barmvixl VIXL_STATIC_ASSERT(sizeof(result) <= sizeof(raw)); 9734a102baf640077d6794c0b33bb976f94b86c532barmvixl // Copy the result and truncate to fit. This assumes a little-endian host. 9744a102baf640077d6794c0b33bb976f94b86c532barmvixl memcpy(&result, &raw, sizeof(result)); 9754a102baf640077d6794c0b33bb976f94b86c532barmvixl return result; 9764a102baf640077d6794c0b33bb976f94b86c532barmvixl } 97788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois template <typename T> 97888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadRegister", 97988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois T reg(unsigned size, 98088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois unsigned code, 98188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois Reg31Mode r31mode = Reg31IsZeroRegister) const) { 98288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadRegister<T>(size, code, r31mode); 98388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 9844a102baf640077d6794c0b33bb976f94b86c532barmvixl 9854a102baf640077d6794c0b33bb976f94b86c532barmvixl // Use int64_t by default if T is not specified. 98688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int64_t ReadRegister(unsigned size, 98788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois unsigned code, 98888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois Reg31Mode r31mode = Reg31IsZeroRegister) const { 98988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadRegister<int64_t>(size, code, r31mode); 99088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 99188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadRegister", 99288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int64_t reg(unsigned size, 99388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois unsigned code, 99488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois Reg31Mode r31mode = Reg31IsZeroRegister) const) { 99588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadRegister(size, code, r31mode); 996f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl } 997f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl 9980f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl enum RegLogMode { LogRegWrites, NoRegLog }; 999330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl 1000330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl // Write 'value' into an integer register. The value is zero-extended. This 1001330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl // behaviour matches AArch64 register writes. 10020f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl template <typename T> 100388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void WriteRegister(unsigned code, 100488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois T value, 100588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites, 100688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois Reg31Mode r31mode = Reg31IsZeroRegister) { 10074a102baf640077d6794c0b33bb976f94b86c532barmvixl VIXL_STATIC_ASSERT((sizeof(T) == kWRegSizeInBytes) || 10084a102baf640077d6794c0b33bb976f94b86c532barmvixl (sizeof(T) == kXRegSizeInBytes)); 1009868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames VIXL_ASSERT( 1010868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames code < kNumberOfRegisters || 1011868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames ((r31mode == Reg31IsZeroRegister) && (code == kSPRegInternalCode))); 1012f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl 1013ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl if ((code == 31) && (r31mode == Reg31IsZeroRegister)) { 1014f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl return; 1015ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 1016ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 1017868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames if ((r31mode == Reg31IsZeroRegister) && (code == kSPRegInternalCode)) { 1018868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames code = 31; 1019868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames } 1020868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames 102188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois registers_[code].Write(value); 1022330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl 1023330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl if (log_mode == LogRegWrites) LogRegister(code, r31mode); 1024ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 102588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois template <typename T> 102688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("WriteRegister", 102788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void set_reg(unsigned code, 102888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois T value, 102988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites, 103088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois Reg31Mode r31mode = Reg31IsZeroRegister)) { 103188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteRegister<T>(code, value, log_mode, r31mode); 103288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 1033ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 1034f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl // Common specialized accessors for the set_reg() template. 103588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void WriteWRegister(unsigned code, 103688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int32_t value, 103788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites, 103888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois Reg31Mode r31mode = Reg31IsZeroRegister) { 103988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteRegister(code, value, log_mode, r31mode); 104088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 104188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("WriteWRegister", 104288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void set_wreg(unsigned code, 104388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int32_t value, 104488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites, 104588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois Reg31Mode r31mode = Reg31IsZeroRegister)) { 104688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteWRegister(code, value, log_mode, r31mode); 1047ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 1048ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 104988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void WriteXRegister(unsigned code, 105088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int64_t value, 105188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites, 105288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois Reg31Mode r31mode = Reg31IsZeroRegister) { 105388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteRegister(code, value, log_mode, r31mode); 105488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 105588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("WriteXRegister", 105688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void set_xreg(unsigned code, 105788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int64_t value, 105888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites, 105988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois Reg31Mode r31mode = Reg31IsZeroRegister)) { 106088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteXRegister(code, value, log_mode, r31mode); 10614a102baf640077d6794c0b33bb976f94b86c532barmvixl } 10624a102baf640077d6794c0b33bb976f94b86c532barmvixl 10634a102baf640077d6794c0b33bb976f94b86c532barmvixl // As above, with parameterized size and type. The value is either 10644a102baf640077d6794c0b33bb976f94b86c532barmvixl // zero-extended or truncated to fit, as required. 10650f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl template <typename T> 106688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void WriteRegister(unsigned size, 106788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois unsigned code, 106888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois T value, 106988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites, 107088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois Reg31Mode r31mode = Reg31IsZeroRegister) { 10714a102baf640077d6794c0b33bb976f94b86c532barmvixl // Zero-extend the input. 10724a102baf640077d6794c0b33bb976f94b86c532barmvixl uint64_t raw = 0; 10734a102baf640077d6794c0b33bb976f94b86c532barmvixl VIXL_STATIC_ASSERT(sizeof(value) <= sizeof(raw)); 10744a102baf640077d6794c0b33bb976f94b86c532barmvixl memcpy(&raw, &value, sizeof(value)); 10754a102baf640077d6794c0b33bb976f94b86c532barmvixl 10764a102baf640077d6794c0b33bb976f94b86c532barmvixl // Write (and possibly truncate) the value. 10774a102baf640077d6794c0b33bb976f94b86c532barmvixl switch (size) { 1078db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl case kWRegSize: 107988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteRegister(code, static_cast<uint32_t>(raw), log_mode, r31mode); 1080db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl break; 1081db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl case kXRegSize: 108288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteRegister(code, raw, log_mode, r31mode); 1083db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl break; 10844a102baf640077d6794c0b33bb976f94b86c532barmvixl default: 10854a102baf640077d6794c0b33bb976f94b86c532barmvixl VIXL_UNREACHABLE(); 10864a102baf640077d6794c0b33bb976f94b86c532barmvixl return; 10874a102baf640077d6794c0b33bb976f94b86c532barmvixl } 1088ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 108988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois template <typename T> 109088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("WriteRegister", 109188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void set_reg(unsigned size, 109288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois unsigned code, 109388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois T value, 109488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites, 109588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois Reg31Mode r31mode = Reg31IsZeroRegister)) { 109688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteRegister(size, code, value, log_mode, r31mode); 109788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 1098ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 10994a102baf640077d6794c0b33bb976f94b86c532barmvixl // Common specialized accessors for the set_reg() template. 11004a102baf640077d6794c0b33bb976f94b86c532barmvixl 1101f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl // Commonly-used special cases. 11020f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl template <typename T> 110388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void WriteLr(T value) { 110488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteRegister(kLinkRegCode, value); 110588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 110688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois template <typename T> 110788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("WriteLr", void set_lr(T value)) { 110888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteLr(value); 1109ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 1110ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 11110f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl template <typename T> 111288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void WriteSp(T value) { 111388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteRegister(31, value, LogRegWrites, Reg31IsStackPointer); 111488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 111588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois template <typename T> 111688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("WriteSp", void set_sp(T value)) { 111788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteSp(value); 1118f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl } 1119ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 11205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Vector register accessors. 11215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // These are equivalent to the integer register accessors, but for vector 11224a102baf640077d6794c0b33bb976f94b86c532barmvixl // registers. 1123f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl 11245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // A structure for representing a 128-bit Q register. 11250f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl struct qreg_t { 11260f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl uint8_t val[kQRegSizeInBytes]; 11270f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl }; 11285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 11295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Basic accessor: read the register as the specified type. 11300f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl template <typename T> 113188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois T ReadVRegister(unsigned code) const { 11320f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl VIXL_STATIC_ASSERT( 11330f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl (sizeof(T) == kBRegSizeInBytes) || (sizeof(T) == kHRegSizeInBytes) || 11340f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl (sizeof(T) == kSRegSizeInBytes) || (sizeof(T) == kDRegSizeInBytes) || 11350f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl (sizeof(T) == kQRegSizeInBytes)); 11365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(code < kNumberOfVRegisters); 11375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 11385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return vregisters_[code].Get<T>(); 11395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 114088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois template <typename T> 114188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadVRegister", T vreg(unsigned code) const) { 114288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadVRegister<T>(code); 114388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 11445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 11455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Common specialized accessors for the vreg() template. 114688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int8_t ReadBRegister(unsigned code) const { 114788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadVRegister<int8_t>(code); 114888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 114988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadBRegister", int8_t breg(unsigned code) const) { 115088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadBRegister(code); 115188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 11524a102baf640077d6794c0b33bb976f94b86c532barmvixl 115388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int16_t ReadHRegister(unsigned code) const { 115488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadVRegister<int16_t>(code); 115588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 115688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadHRegister", int16_t hreg(unsigned code) const) { 115788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadHRegister(code); 115888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 1159ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 116088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois float ReadSRegister(unsigned code) const { 116188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadVRegister<float>(code); 116288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 116388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadSRegister", float sreg(unsigned code) const) { 116488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadSRegister(code); 116588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 1166ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 116788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois uint32_t ReadSRegisterBits(unsigned code) const { 116888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadVRegister<uint32_t>(code); 116988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 117088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadSRegisterBits", 117188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois uint32_t sreg_bits(unsigned code) const) { 117288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadSRegisterBits(code); 117388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 1174ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 117588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois double ReadDRegister(unsigned code) const { 117688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadVRegister<double>(code); 117788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 117888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadDRegister", double dreg(unsigned code) const) { 117988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadDRegister(code); 118088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 1181ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 118288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois uint64_t ReadDRegisterBits(unsigned code) const { 118388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadVRegister<uint64_t>(code); 118488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 118588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadDRegisterBits", 118688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois uint64_t dreg_bits(unsigned code) const) { 118788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadDRegisterBits(code); 118888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 11895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 119088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois qreg_t ReadQRegister(unsigned code) const { 119188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadVRegister<qreg_t>(code); 119288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 119388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadQRegister", qreg_t qreg(unsigned code) const) { 119488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadQRegister(code); 119588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 1196ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 11974a102baf640077d6794c0b33bb976f94b86c532barmvixl // As above, with parameterized size and return type. The value is 11984a102baf640077d6794c0b33bb976f94b86c532barmvixl // either zero-extended or truncated to fit, as required. 11990f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl template <typename T> 120088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois T ReadVRegister(unsigned size, unsigned code) const { 12015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t raw = 0; 12025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl T result; 12035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 1204ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl switch (size) { 12050f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case kSRegSize: 120688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois raw = ReadVRegister<uint32_t>(code); 12070f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 12080f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case kDRegSize: 120988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois raw = ReadVRegister<uint64_t>(code); 12100f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 1211f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl default: 1212b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_UNREACHABLE(); 12134a102baf640077d6794c0b33bb976f94b86c532barmvixl break; 1214ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 12154a102baf640077d6794c0b33bb976f94b86c532barmvixl 12164a102baf640077d6794c0b33bb976f94b86c532barmvixl VIXL_STATIC_ASSERT(sizeof(result) <= sizeof(raw)); 12174a102baf640077d6794c0b33bb976f94b86c532barmvixl // Copy the result and truncate to fit. This assumes a little-endian host. 12184a102baf640077d6794c0b33bb976f94b86c532barmvixl memcpy(&result, &raw, sizeof(result)); 12194a102baf640077d6794c0b33bb976f94b86c532barmvixl return result; 1220ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 122188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois template <typename T> 122288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadVRegister", T vreg(unsigned size, unsigned code) const) { 122388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadVRegister<T>(size, code); 122488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 1225ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 122688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois SimVRegister& ReadVRegister(unsigned code) { return vregisters_[code]; } 122788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadVRegister", SimVRegister& vreg(unsigned code)) { 122888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadVRegister(code); 122988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 12305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 12314a102baf640077d6794c0b33bb976f94b86c532barmvixl // Basic accessor: Write the specified value. 12320f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl template <typename T> 123388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void WriteVRegister(unsigned code, 123488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois T value, 123588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites) { 12365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_STATIC_ASSERT((sizeof(value) == kBRegSizeInBytes) || 12375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl (sizeof(value) == kHRegSizeInBytes) || 12385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl (sizeof(value) == kSRegSizeInBytes) || 12395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl (sizeof(value) == kDRegSizeInBytes) || 12405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl (sizeof(value) == kQRegSizeInBytes)); 12415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(code < kNumberOfVRegisters); 124288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois vregisters_[code].Write(value); 1243330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl 1244330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl if (log_mode == LogRegWrites) { 12455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogVRegister(code, GetPrintRegisterFormat(value)); 1246330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl } 1247ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 124888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois template <typename T> 124988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("WriteVRegister", 125088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void set_vreg(unsigned code, 125188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois T value, 125288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites)) { 125388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteVRegister(code, value, log_mode); 125488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 1255ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 125688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois // Common specialized accessors for the WriteVRegister() template. 125788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void WriteBRegister(unsigned code, 125888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int8_t value, 125988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites) { 126088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteVRegister(code, value, log_mode); 126188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 126288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("WriteBRegister", 126388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void set_breg(unsigned code, 126488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int8_t value, 126588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites)) { 126688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return WriteBRegister(code, value, log_mode); 12675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 12685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 126988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void WriteHRegister(unsigned code, 127088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int16_t value, 127188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites) { 127288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteVRegister(code, value, log_mode); 127388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 127488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("WriteHRegister", 127588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void set_hreg(unsigned code, 127688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int16_t value, 127788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites)) { 127888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return WriteHRegister(code, value, log_mode); 12795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 12805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 128188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void WriteSRegister(unsigned code, 128288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois float value, 128388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites) { 128488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteVRegister(code, value, log_mode); 128588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 128688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("WriteSRegister", 128788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void set_sreg(unsigned code, 128888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois float value, 128988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites)) { 129088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteSRegister(code, value, log_mode); 1291ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 1292ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 129388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void WriteSRegisterBits(unsigned code, 129488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois uint32_t value, 129588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites) { 129688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteVRegister(code, value, log_mode); 129788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 129888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("WriteSRegisterBits", 129988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void set_sreg_bits(unsigned code, 130088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois uint32_t value, 130188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites)) { 130288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteSRegisterBits(code, value, log_mode); 1303ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 1304ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 130588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void WriteDRegister(unsigned code, 130688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois double value, 130788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites) { 130888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteVRegister(code, value, log_mode); 130988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 131088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("WriteDRegister", 131188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void set_dreg(unsigned code, 131288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois double value, 131388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites)) { 131488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteDRegister(code, value, log_mode); 1315ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 1316ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 131788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void WriteDRegisterBits(unsigned code, 131888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois uint64_t value, 131988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites) { 132088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteVRegister(code, value, log_mode); 132188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 132288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("WriteDRegisterBits", 132388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void set_dreg_bits(unsigned code, 132488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois uint64_t value, 132588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites)) { 132688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteDRegisterBits(code, value, log_mode); 13275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 13285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 132988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void WriteQRegister(unsigned code, 133088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois qreg_t value, 133188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites) { 133288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteVRegister(code, value, log_mode); 1333ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 133488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("WriteQRegister", 133588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void set_qreg(unsigned code, 133688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois qreg_t value, 133788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites)) { 133888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteQRegister(code, value, log_mode); 133988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 134088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois 1341868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames template <typename T> 1342868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames T ReadRegister(Register reg) const { 1343868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames return ReadRegister<T>(reg.GetCode(), Reg31IsZeroRegister); 1344868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames } 1345868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames 1346868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames template <typename T> 1347868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames void WriteRegister(Register reg, 1348868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames T value, 1349868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames RegLogMode log_mode = LogRegWrites) { 1350868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames WriteRegister<T>(reg.GetCode(), value, log_mode, Reg31IsZeroRegister); 1351868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames } 1352868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames 1353868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames template <typename T> 1354868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames T ReadVRegister(VRegister vreg) const { 1355868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames return ReadVRegister<T>(vreg.GetCode()); 1356868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames } 1357868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames 1358868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames template <typename T> 1359868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames void WriteVRegister(VRegister vreg, 1360868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames T value, 1361868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames RegLogMode log_mode = LogRegWrites) { 1362868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames WriteVRegister<T>(vreg.GetCode(), value, log_mode); 1363868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames } 1364868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames 1365868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames template <typename T> 1366868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames T ReadCPURegister(CPURegister reg) const { 1367868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames if (reg.IsVRegister()) { 1368868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames return ReadVRegister<T>(VRegister(reg)); 1369868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames } else { 1370868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames return ReadRegister<T>(Register(reg)); 1371868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames } 1372868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames } 1373868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames 1374868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames template <typename T> 1375868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames void WriteCPURegister(CPURegister reg, 1376868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames T value, 1377868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames RegLogMode log_mode = LogRegWrites) { 1378868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames if (reg.IsVRegister()) { 1379868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames WriteVRegister<T>(VRegister(reg), value, log_mode); 1380868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames } else { 1381868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames WriteRegister<T>(Register(reg), value, log_mode); 1382868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames } 1383868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames } 1384868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames 1385868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames uint64_t ComputeMemOperandAddress(const MemOperand& mem_op) const; 1386868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames 1387868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames template <typename T> 1388868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames T ReadGenericOperand(GenericOperand operand) const { 1389868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames if (operand.IsCPURegister()) { 1390868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames return ReadCPURegister<T>(operand.GetCPURegister()); 1391868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames } else { 1392868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames VIXL_ASSERT(operand.IsMemOperand()); 1393868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames return Memory::Read<T>(ComputeMemOperandAddress(operand.GetMemOperand())); 1394868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames } 1395868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames } 1396868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames 1397868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames template <typename T> 1398868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames void WriteGenericOperand(GenericOperand operand, 1399868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames T value, 1400868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames RegLogMode log_mode = LogRegWrites) { 1401868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames if (operand.IsCPURegister()) { 1402868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames WriteCPURegister<T>(operand.GetCPURegister(), value, log_mode); 1403868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames } else { 1404868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames VIXL_ASSERT(operand.IsMemOperand()); 1405868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames Memory::Write(ComputeMemOperandAddress(operand.GetMemOperand()), value); 1406868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames } 1407868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames } 1408868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames 140988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois bool ReadN() const { return nzcv_.GetN() != 0; } 141088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadN", bool N() const) { return ReadN(); } 1411ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 141288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois bool ReadZ() const { return nzcv_.GetZ() != 0; } 141388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadZ", bool Z() const) { return ReadZ(); } 141488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois 141588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois bool ReadC() const { return nzcv_.GetC() != 0; } 141688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadC", bool C() const) { return ReadC(); } 141788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois 141888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois bool ReadV() const { return nzcv_.GetV() != 0; } 141988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadV", bool V() const) { return ReadV(); } 142088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois 142188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois SimSystemRegister& ReadNzcv() { return nzcv_; } 142288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadNzcv", SimSystemRegister& nzcv()) { return ReadNzcv(); } 1423578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 14245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // TODO: Find a way to make the fpcr_ members return the proper types, so 14255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // these accessors are not necessary. 142688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois FPRounding ReadRMode() const { 142788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return static_cast<FPRounding>(fpcr_.GetRMode()); 142888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 142988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadRMode", FPRounding RMode()) { return ReadRMode(); } 143088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois 143188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois bool ReadDN() const { return fpcr_.GetDN() != 0; } 143288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadDN", bool DN()) { return ReadDN(); } 143388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois 143488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois SimSystemRegister& ReadFpcr() { return fpcr_; } 143588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadFpcr", SimSystemRegister& fpcr()) { return ReadFpcr(); } 1436ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 14375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Specify relevant register formats for Print(V)Register and related helpers. 14385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl enum PrintRegisterFormat { 14395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // The lane size. 14405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintRegLaneSizeB = 0 << 0, 14415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintRegLaneSizeH = 1 << 0, 14425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintRegLaneSizeS = 2 << 0, 14435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintRegLaneSizeW = kPrintRegLaneSizeS, 14445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintRegLaneSizeD = 3 << 0, 14455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintRegLaneSizeX = kPrintRegLaneSizeD, 14465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintRegLaneSizeQ = 4 << 0, 14475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 14485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintRegLaneSizeOffset = 0, 14495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintRegLaneSizeMask = 7 << 0, 14505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 14515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // The lane count. 14525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintRegAsScalar = 0, 14535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintRegAsDVector = 1 << 3, 14545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintRegAsQVector = 2 << 3, 14555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 14565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintRegAsVectorMask = 3 << 3, 14575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 14585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Indicate floating-point format lanes. (This flag is only supported for S- 14595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // and D-sized lanes.) 14605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintRegAsFP = 1 << 5, 14615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 14625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Supported combinations. 14635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 14645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintXReg = kPrintRegLaneSizeX | kPrintRegAsScalar, 14655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintWReg = kPrintRegLaneSizeW | kPrintRegAsScalar, 14665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintSReg = kPrintRegLaneSizeS | kPrintRegAsScalar | kPrintRegAsFP, 14675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintDReg = kPrintRegLaneSizeD | kPrintRegAsScalar | kPrintRegAsFP, 14685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 14695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintReg1B = kPrintRegLaneSizeB | kPrintRegAsScalar, 14705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintReg8B = kPrintRegLaneSizeB | kPrintRegAsDVector, 14715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintReg16B = kPrintRegLaneSizeB | kPrintRegAsQVector, 14725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintReg1H = kPrintRegLaneSizeH | kPrintRegAsScalar, 14735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintReg4H = kPrintRegLaneSizeH | kPrintRegAsDVector, 14745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintReg8H = kPrintRegLaneSizeH | kPrintRegAsQVector, 14755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintReg1S = kPrintRegLaneSizeS | kPrintRegAsScalar, 14765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintReg2S = kPrintRegLaneSizeS | kPrintRegAsDVector, 14775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintReg4S = kPrintRegLaneSizeS | kPrintRegAsQVector, 14785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintReg1SFP = kPrintRegLaneSizeS | kPrintRegAsScalar | kPrintRegAsFP, 14795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintReg2SFP = kPrintRegLaneSizeS | kPrintRegAsDVector | kPrintRegAsFP, 14805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintReg4SFP = kPrintRegLaneSizeS | kPrintRegAsQVector | kPrintRegAsFP, 14815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintReg1D = kPrintRegLaneSizeD | kPrintRegAsScalar, 14825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintReg2D = kPrintRegLaneSizeD | kPrintRegAsQVector, 14835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintReg1DFP = kPrintRegLaneSizeD | kPrintRegAsScalar | kPrintRegAsFP, 14845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintReg2DFP = kPrintRegLaneSizeD | kPrintRegAsQVector | kPrintRegAsFP, 14855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintReg1Q = kPrintRegLaneSizeQ | kPrintRegAsScalar 14865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl }; 14875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 14885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl unsigned GetPrintRegLaneSizeInBytesLog2(PrintRegisterFormat format) { 14895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return (format & kPrintRegLaneSizeMask) >> kPrintRegLaneSizeOffset; 14905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 14915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 14925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl unsigned GetPrintRegLaneSizeInBytes(PrintRegisterFormat format) { 14935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return 1 << GetPrintRegLaneSizeInBytesLog2(format); 14945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 14955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 14965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl unsigned GetPrintRegSizeInBytesLog2(PrintRegisterFormat format) { 14975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (format & kPrintRegAsDVector) return kDRegSizeInBytesLog2; 14985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (format & kPrintRegAsQVector) return kQRegSizeInBytesLog2; 14995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 15005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Scalar types. 15015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return GetPrintRegLaneSizeInBytesLog2(format); 15025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 15035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 15045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl unsigned GetPrintRegSizeInBytes(PrintRegisterFormat format) { 15055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return 1 << GetPrintRegSizeInBytesLog2(format); 15065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 15075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 15085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl unsigned GetPrintRegLaneCount(PrintRegisterFormat format) { 15095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl unsigned reg_size_log2 = GetPrintRegSizeInBytesLog2(format); 15105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl unsigned lane_size_log2 = GetPrintRegLaneSizeInBytesLog2(format); 15115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(reg_size_log2 >= lane_size_log2); 15125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return 1 << (reg_size_log2 - lane_size_log2); 15135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 15145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 15155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl PrintRegisterFormat GetPrintRegisterFormatForSize(unsigned reg_size, 15165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl unsigned lane_size); 15175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 15185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl PrintRegisterFormat GetPrintRegisterFormatForSize(unsigned size) { 15195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return GetPrintRegisterFormatForSize(size, size); 15205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 15215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 15225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl PrintRegisterFormat GetPrintRegisterFormatForSizeFP(unsigned size) { 15235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl switch (size) { 15240f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl default: 15250f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl VIXL_UNREACHABLE(); 15260f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl return kPrintDReg; 15270f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case kDRegSizeInBytes: 15280f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl return kPrintDReg; 15290f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case kSRegSizeInBytes: 15300f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl return kPrintSReg; 15315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 15325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 15335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 15345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl PrintRegisterFormat GetPrintRegisterFormatTryFP(PrintRegisterFormat format) { 15355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if ((GetPrintRegLaneSizeInBytes(format) == kSRegSizeInBytes) || 15365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl (GetPrintRegLaneSizeInBytes(format) == kDRegSizeInBytes)) { 15375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return static_cast<PrintRegisterFormat>(format | kPrintRegAsFP); 15385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 15395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return format; 15405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 15415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 15420f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl template <typename T> 15435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl PrintRegisterFormat GetPrintRegisterFormat(T value) { 15445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return GetPrintRegisterFormatForSize(sizeof(value)); 15455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 15465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 15475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl PrintRegisterFormat GetPrintRegisterFormat(double value) { 15485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_STATIC_ASSERT(sizeof(value) == kDRegSizeInBytes); 15495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return GetPrintRegisterFormatForSizeFP(sizeof(value)); 15505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 15515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 15525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl PrintRegisterFormat GetPrintRegisterFormat(float value) { 15535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_STATIC_ASSERT(sizeof(value) == kSRegSizeInBytes); 15545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return GetPrintRegisterFormatForSizeFP(sizeof(value)); 15555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 15565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 15575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl PrintRegisterFormat GetPrintRegisterFormat(VectorFormat vform); 15580f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl PrintRegisterFormat GetPrintRegisterFormatFP(VectorFormat vform); 15595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 1560330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl // Print all registers of the specified types. 1561330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl void PrintRegisters(); 15625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void PrintVRegisters(); 1563330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl void PrintSystemRegisters(); 1564330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl 15655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // As above, but only print the registers that have been updated. 15665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void PrintWrittenRegisters(); 15675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void PrintWrittenVRegisters(); 15685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 15695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // As above, but respect LOG_REG and LOG_VREG. 15705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void LogWrittenRegisters() { 157188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois if (GetTraceParameters() & LOG_REGS) PrintWrittenRegisters(); 1572330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl } 15735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void LogWrittenVRegisters() { 157488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois if (GetTraceParameters() & LOG_VREGS) PrintWrittenVRegisters(); 1575330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl } 15765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void LogAllWrittenRegisters() { 15775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogWrittenRegisters(); 15785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogWrittenVRegisters(); 1579330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl } 1580330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl 1581330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl // Print individual register values (after update). 1582330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl void PrintRegister(unsigned code, Reg31Mode r31mode = Reg31IsStackPointer); 15835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void PrintVRegister(unsigned code, PrintRegisterFormat format); 1584330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl void PrintSystemRegister(SystemRegister id); 1585e79723a010a6f42fe78e2515c7b0eb9308b93093Jacob Bramley void PrintTakenBranch(const Instruction* target); 1586330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl 158788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois // Like Print* (above), but respect GetTraceParameters(). 1588330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl void LogRegister(unsigned code, Reg31Mode r31mode = Reg31IsStackPointer) { 158988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois if (GetTraceParameters() & LOG_REGS) PrintRegister(code, r31mode); 1590330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl } 15915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void LogVRegister(unsigned code, PrintRegisterFormat format) { 159288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois if (GetTraceParameters() & LOG_VREGS) PrintVRegister(code, format); 1593330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl } 1594330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl void LogSystemRegister(SystemRegister id) { 159588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois if (GetTraceParameters() & LOG_SYSREGS) PrintSystemRegister(id); 1596330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl } 1597e79723a010a6f42fe78e2515c7b0eb9308b93093Jacob Bramley void LogTakenBranch(const Instruction* target) { 1598e79723a010a6f42fe78e2515c7b0eb9308b93093Jacob Bramley if (GetTraceParameters() & LOG_BRANCH) PrintTakenBranch(target); 1599e79723a010a6f42fe78e2515c7b0eb9308b93093Jacob Bramley } 1600330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl 1601330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl // Print memory accesses. 16020f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl void PrintRead(uintptr_t address, 16030f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl unsigned reg_code, 16045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl PrintRegisterFormat format); 16050f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl void PrintWrite(uintptr_t address, 16060f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl unsigned reg_code, 16070f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl PrintRegisterFormat format); 16080f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl void PrintVRead(uintptr_t address, 16090f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl unsigned reg_code, 16100f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl PrintRegisterFormat format, 16110f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl unsigned lane); 16120f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl void PrintVWrite(uintptr_t address, 16130f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl unsigned reg_code, 16140f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl PrintRegisterFormat format, 16150f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl unsigned lane); 1616330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl 161788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois // Like Print* (above), but respect GetTraceParameters(). 16180f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl void LogRead(uintptr_t address, 16190f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl unsigned reg_code, 16205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl PrintRegisterFormat format) { 162188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois if (GetTraceParameters() & LOG_REGS) PrintRead(address, reg_code, format); 1622330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl } 16230f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl void LogWrite(uintptr_t address, 16240f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl unsigned reg_code, 16255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl PrintRegisterFormat format) { 162688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois if (GetTraceParameters() & LOG_WRITE) PrintWrite(address, reg_code, format); 1627330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl } 16280f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl void LogVRead(uintptr_t address, 16290f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl unsigned reg_code, 16300f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl PrintRegisterFormat format, 16310f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl unsigned lane = 0) { 163288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois if (GetTraceParameters() & LOG_VREGS) { 16335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl PrintVRead(address, reg_code, format, lane); 16345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 1635330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl } 16360f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl void LogVWrite(uintptr_t address, 16370f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl unsigned reg_code, 16380f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl PrintRegisterFormat format, 16390f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl unsigned lane = 0) { 164088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois if (GetTraceParameters() & LOG_WRITE) { 16415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl PrintVWrite(address, reg_code, format, lane); 16425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 1643330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl } 1644330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl 16455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Helper functions for register tracing. 16460f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl void PrintRegisterRawHelper(unsigned code, 16470f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl Reg31Mode r31mode, 16485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int size_in_bytes = kXRegSizeInBytes); 16490f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl void PrintVRegisterRawHelper(unsigned code, 16500f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl int bytes = kQRegSizeInBytes, 16515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int lsb = 0); 16520f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl void PrintVRegisterFPHelper(unsigned code, 16530f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl unsigned lane_size_in_bytes, 16540f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl int lane_count = 1, 16550f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl int rightmost_lane = 0); 16565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 1657684cd2a7f5845539b58d0da7e012e39df49ceff0armvixl VIXL_NO_RETURN void DoUnreachable(const Instruction* instr); 1658330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl void DoTrace(const Instruction* instr); 1659330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl void DoLog(const Instruction* instr); 1660ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 1661ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl static const char* WRegNameForCode(unsigned code, 1662ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl Reg31Mode mode = Reg31IsZeroRegister); 1663ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl static const char* XRegNameForCode(unsigned code, 1664ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl Reg31Mode mode = Reg31IsZeroRegister); 1665ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl static const char* SRegNameForCode(unsigned code); 1666ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl static const char* DRegNameForCode(unsigned code); 1667ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl static const char* VRegNameForCode(unsigned code); 1668ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 166988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois bool IsColouredTrace() const { return coloured_trace_; } 167088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("IsColouredTrace", bool coloured_trace() const) { 167188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return IsColouredTrace(); 167288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 1673ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 167488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void SetColouredTrace(bool value); 167588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("SetColouredTrace", void set_coloured_trace(bool value)) { 167688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois SetColouredTrace(value); 167788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 1678330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl 1679d3832965c62a8ad461b9ea9eb0994ca6b0a3da2cAlexandre Rames // Values for traces parameters defined in simulator-constants-aarch64.h in 168088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois // enum TraceParameters. 168188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int GetTraceParameters() const { return trace_parameters_; } 168288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("GetTraceParameters", int trace_parameters() const) { 168388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return GetTraceParameters(); 168488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 168588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois 168688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void SetTraceParameters(int parameters); 168788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("SetTraceParameters", 168888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void set_trace_parameters(int parameters)) { 168988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois SetTraceParameters(parameters); 169088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 169188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois 169288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void SetInstructionStats(bool value); 169388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("SetInstructionStats", 169488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void set_instruction_stats(bool value)) { 169588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois SetInstructionStats(value); 169688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 1697ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 16984a102baf640077d6794c0b33bb976f94b86c532barmvixl // Clear the simulated local monitor to force the next store-exclusive 16994a102baf640077d6794c0b33bb976f94b86c532barmvixl // instruction to fail. 17000f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl void ClearLocalMonitor() { local_monitor_.Clear(); } 17014a102baf640077d6794c0b33bb976f94b86c532barmvixl 1702330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl void SilenceExclusiveAccessWarning() { 17034a102baf640077d6794c0b33bb976f94b86c532barmvixl print_exclusive_access_warning_ = false; 17044a102baf640077d6794c0b33bb976f94b86c532barmvixl } 17054a102baf640077d6794c0b33bb976f94b86c532barmvixl 1706064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames// Runtime call emulation support. 1707064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames// It requires VIXL's ABI features, and C++11 or greater. 1708482d4df29d1466ff87d94e74034f1a8659f1b354Jacob Bramley// Also, the initialisation of the tuples in RuntimeCall(Non)Void is incorrect 1709482d4df29d1466ff87d94e74034f1a8659f1b354Jacob Bramley// in GCC before 4.9.1: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=51253 1710482d4df29d1466ff87d94e74034f1a8659f1b354Jacob Bramley#if defined(VIXL_HAS_ABI_SUPPORT) && __cplusplus >= 201103L && \ 1711482d4df29d1466ff87d94e74034f1a8659f1b354Jacob Bramley (defined(__clang__) || GCC_VERSION_OR_NEWER(4, 9, 1)) 1712064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames 1713ca73ba046c11d65b6dce59cfd26847d14aba06abAlexandre Rames#define VIXL_HAS_SIMULATED_RUNTIME_CALL_SUPPORT 1714064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames 1715064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames// The implementation of the runtime call helpers require the functionality 1716064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames// provided by `std::index_sequence`. It is only available from C++14, but 1717064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames// we want runtime call simulation to work from C++11, so we emulate if 1718064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames// necessary. 1719064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames#if __cplusplus >= 201402L 1720064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames template <std::size_t... I> 1721064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames using local_index_sequence = std::index_sequence<I...>; 1722064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames template <typename... P> 1723064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames using __local_index_sequence_for = std::index_sequence_for<P...>; 1724064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames#else 1725064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames // Emulate the behaviour of `std::index_sequence` and 1726064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames // `std::index_sequence_for`. 1727064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames // Naming follow the `std` names, prefixed with `emulated_`. 1728064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames template <size_t... I> 1729064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames struct emulated_index_sequence {}; 1730064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames 1731064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames // A recursive template to create a sequence of indexes. 1732064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames // The base case (for `N == 0`) is declared outside of the class scope, as 1733064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames // required by C++. 1734064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames template <std::size_t N, size_t... I> 1735064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames struct emulated_make_index_sequence_helper 1736064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames : emulated_make_index_sequence_helper<N - 1, N - 1, I...> {}; 1737064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames 1738064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames template <std::size_t N> 1739064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames struct emulated_make_index_sequence : emulated_make_index_sequence_helper<N> { 1740064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames }; 1741064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames 1742064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames template <typename... P> 1743064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames struct emulated_index_sequence_for 1744064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames : emulated_make_index_sequence<sizeof...(P)> {}; 1745064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames 1746064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames template <std::size_t... I> 1747064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames using local_index_sequence = emulated_index_sequence<I...>; 1748064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames template <typename... P> 1749064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames using __local_index_sequence_for = emulated_index_sequence_for<P...>; 1750064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames#endif 1751064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames 1752064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames // Expand the argument tuple and perform the call. 1753064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames template <typename R, typename... P, std::size_t... I> 1754064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames R DoRuntimeCall(R (*function)(P...), 1755064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames std::tuple<P...> arguments, 1756064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames local_index_sequence<I...>) { 1757064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames return function(std::get<I>(arguments)...); 1758064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames } 1759064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames 1760064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames template <typename R, typename... P> 1761064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames void RuntimeCallNonVoid(R (*function)(P...)) { 1762064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames ABI abi; 1763064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames std::tuple<P...> argument_operands{ 1764064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames ReadGenericOperand<P>(abi.GetNextParameterGenericOperand<P>())...}; 1765064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames R return_value = DoRuntimeCall(function, 1766064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames argument_operands, 1767064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames __local_index_sequence_for<P...>{}); 1768064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames WriteGenericOperand(abi.GetReturnGenericOperand<R>(), return_value); 1769064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames } 1770064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames 1771064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames template <typename R, typename... P> 1772064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames void RuntimeCallVoid(R (*function)(P...)) { 1773064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames ABI abi; 1774064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames std::tuple<P...> argument_operands{ 1775064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames ReadGenericOperand<P>(abi.GetNextParameterGenericOperand<P>())...}; 1776064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames DoRuntimeCall(function, 1777064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames argument_operands, 1778064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames __local_index_sequence_for<P...>{}); 1779064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames } 1780064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames 1781064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames // We use `struct` for `void` return type specialisation. 1782064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames template <typename R, typename... P> 1783064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames struct RuntimeCallStructHelper { 1784482d4df29d1466ff87d94e74034f1a8659f1b354Jacob Bramley static void Wrapper(Simulator* simulator, uintptr_t function_pointer) { 1785064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames R (*function)(P...) = reinterpret_cast<R (*)(P...)>(function_pointer); 1786064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames simulator->RuntimeCallNonVoid(function); 1787064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames } 1788064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames }; 1789064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames 1790064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames // Partial specialization when the return type is `void`. 1791064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames template <typename... P> 1792064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames struct RuntimeCallStructHelper<void, P...> { 1793482d4df29d1466ff87d94e74034f1a8659f1b354Jacob Bramley static void Wrapper(Simulator* simulator, uintptr_t function_pointer) { 1794064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames void (*function)(P...) = 1795064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames reinterpret_cast<void (*)(P...)>(function_pointer); 1796064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames simulator->RuntimeCallVoid(function); 1797064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames } 1798064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames }; 1799064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames#endif 1800064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames 1801ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl protected: 1802b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl const char* clr_normal; 1803b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl const char* clr_flag_name; 1804b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl const char* clr_flag_value; 1805b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl const char* clr_reg_name; 1806b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl const char* clr_reg_value; 18075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const char* clr_vreg_name; 18085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const char* clr_vreg_value; 1809b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl const char* clr_memory_address; 18104a102baf640077d6794c0b33bb976f94b86c532barmvixl const char* clr_warning; 18114a102baf640077d6794c0b33bb976f94b86c532barmvixl const char* clr_warning_message; 1812b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl const char* clr_printf; 1813e79723a010a6f42fe78e2515c7b0eb9308b93093Jacob Bramley const char* clr_branch_marker; 1814b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 1815ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // Simulation helpers ------------------------------------ 1816ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl bool ConditionPassed(Condition cond) { 1817ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl switch (cond) { 1818ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl case eq: 181988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadZ(); 1820ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl case ne: 182188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return !ReadZ(); 1822ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl case hs: 182388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadC(); 1824ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl case lo: 182588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return !ReadC(); 1826ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl case mi: 182788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadN(); 1828ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl case pl: 182988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return !ReadN(); 1830ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl case vs: 183188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadV(); 1832ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl case vc: 183388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return !ReadV(); 1834ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl case hi: 183588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadC() && !ReadZ(); 1836ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl case ls: 183788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return !(ReadC() && !ReadZ()); 1838ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl case ge: 183988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadN() == ReadV(); 1840ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl case lt: 184188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadN() != ReadV(); 1842ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl case gt: 184388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return !ReadZ() && (ReadN() == ReadV()); 1844ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl case le: 184588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return !(!ReadZ() && (ReadN() == ReadV())); 18466e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl case nv: 18476e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl VIXL_FALLTHROUGH(); 1848ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl case al: 1849ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl return true; 1850ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl default: 1851b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_UNREACHABLE(); 1852ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl return false; 1853ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 1854ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 1855ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 18564a102baf640077d6794c0b33bb976f94b86c532barmvixl bool ConditionPassed(Instr cond) { 18574a102baf640077d6794c0b33bb976f94b86c532barmvixl return ConditionPassed(static_cast<Condition>(cond)); 18584a102baf640077d6794c0b33bb976f94b86c532barmvixl } 18594a102baf640077d6794c0b33bb976f94b86c532barmvixl 18600f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl bool ConditionFailed(Condition cond) { return !ConditionPassed(cond); } 1861ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 1862c68cb64496485710cdb5b8480f8fee287058c93farmvixl void AddSubHelper(const Instruction* instr, int64_t op2); 1863684cd2a7f5845539b58d0da7e012e39df49ceff0armvixl uint64_t AddWithCarry(unsigned reg_size, 1864684cd2a7f5845539b58d0da7e012e39df49ceff0armvixl bool set_flags, 1865684cd2a7f5845539b58d0da7e012e39df49ceff0armvixl uint64_t left, 1866684cd2a7f5845539b58d0da7e012e39df49ceff0armvixl uint64_t right, 1867684cd2a7f5845539b58d0da7e012e39df49ceff0armvixl int carry_in = 0); 1868c68cb64496485710cdb5b8480f8fee287058c93farmvixl void LogicalHelper(const Instruction* instr, int64_t op2); 1869c68cb64496485710cdb5b8480f8fee287058c93farmvixl void ConditionalCompareHelper(const Instruction* instr, int64_t op2); 1870c68cb64496485710cdb5b8480f8fee287058c93farmvixl void LoadStoreHelper(const Instruction* instr, 1871ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl int64_t offset, 1872ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl AddrMode addrmode); 1873c68cb64496485710cdb5b8480f8fee287058c93farmvixl void LoadStorePairHelper(const Instruction* instr, AddrMode addrmode); 1874330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl uintptr_t AddressModeHelper(unsigned addr_reg, 1875330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl int64_t offset, 1876330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl AddrMode addrmode); 18775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void NEONLoadStoreMultiStructHelper(const Instruction* instr, 18785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl AddrMode addr_mode); 18795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void NEONLoadStoreSingleStructHelper(const Instruction* instr, 18805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl AddrMode addr_mode); 1881330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl 18820f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl uint64_t AddressUntag(uint64_t address) { return address & ~kAddressTagMask; } 1883ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 18844a102baf640077d6794c0b33bb976f94b86c532barmvixl template <typename T> 1885330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl T* AddressUntag(T* address) { 1886330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl uintptr_t address_raw = reinterpret_cast<uintptr_t>(address); 1887330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl return reinterpret_cast<T*>(AddressUntag(address_raw)); 18884a102baf640077d6794c0b33bb976f94b86c532barmvixl } 1889ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 1890ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl int64_t ShiftOperand(unsigned reg_size, 1891ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl int64_t value, 1892ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl Shift shift_type, 1893868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames unsigned amount) const; 1894ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl int64_t ExtendValue(unsigned reg_width, 1895ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl int64_t value, 1896ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl Extend extend_type, 1897868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames unsigned left_shift = 0) const; 1898868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames uint16_t PolynomialMult(uint8_t op1, uint8_t op2) const; 18995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 19000f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl void ld1(VectorFormat vform, LogicVRegister dst, uint64_t addr); 19010f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl void ld1(VectorFormat vform, LogicVRegister dst, int index, uint64_t addr); 19020f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl void ld1r(VectorFormat vform, LogicVRegister dst, uint64_t addr); 19035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void ld2(VectorFormat vform, 19045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst1, 19055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst2, 19065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr); 19075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void ld2(VectorFormat vform, 19085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst1, 19095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst2, 19105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index, 19115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr); 19125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void ld2r(VectorFormat vform, 19130f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst1, 19140f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst2, 19150f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl uint64_t addr); 19165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void ld3(VectorFormat vform, 19175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst1, 19185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst2, 19195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst3, 19205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr); 19215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void ld3(VectorFormat vform, 19225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst1, 19235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst2, 19245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst3, 19255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index, 19265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr); 19275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void ld3r(VectorFormat vform, 19280f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst1, 19290f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst2, 19300f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst3, 19310f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl uint64_t addr); 19325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void ld4(VectorFormat vform, 19335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst1, 19345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst2, 19355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst3, 19365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst4, 19375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr); 19385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void ld4(VectorFormat vform, 19395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst1, 19405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst2, 19415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst3, 19425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst4, 19435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index, 19445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr); 19455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void ld4r(VectorFormat vform, 19460f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst1, 19470f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst2, 19480f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst3, 19490f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst4, 19500f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl uint64_t addr); 19510f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl void st1(VectorFormat vform, LogicVRegister src, uint64_t addr); 19520f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl void st1(VectorFormat vform, LogicVRegister src, int index, uint64_t addr); 19535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void st2(VectorFormat vform, 19545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister src, 19555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister src2, 19565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr); 19575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void st2(VectorFormat vform, 19585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister src, 19595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister src2, 19605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index, 19615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr); 19625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void st3(VectorFormat vform, 19635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister src, 19645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister src2, 19655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister src3, 19665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr); 19675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void st3(VectorFormat vform, 19685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister src, 19695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister src2, 19705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister src3, 19715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index, 19725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr); 19735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void st4(VectorFormat vform, 19745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister src, 19755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister src2, 19765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister src3, 19775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister src4, 19785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr); 19795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void st4(VectorFormat vform, 19805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister src, 19815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister src2, 19825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister src3, 19835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister src4, 19845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index, 19855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr); 19865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister cmp(VectorFormat vform, 19875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 19885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 19895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 19905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Condition cond); 19915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister cmp(VectorFormat vform, 19925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 19935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 19945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int imm, 19955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Condition cond); 19965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister cmptst(VectorFormat vform, 19975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 19985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 19995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 20005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister add(VectorFormat vform, 20015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 20025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 20035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 20045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister addp(VectorFormat vform, 20055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 20065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 20075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 20085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister mla(VectorFormat vform, 20095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 20105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 20115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 20125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister mls(VectorFormat vform, 20135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 20145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 20155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 20165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister mul(VectorFormat vform, 20175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 20185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 20195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 20205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister mul(VectorFormat vform, 20215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 20225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 20235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 20245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 20255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister mla(VectorFormat vform, 20265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 20275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 20285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 20295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 20305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister mls(VectorFormat vform, 20315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 20325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 20335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 20345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 20355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister pmul(VectorFormat vform, 20365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 20375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 20385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 20395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 20405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl typedef LogicVRegister (Simulator::*ByElementOp)(VectorFormat vform, 20415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 20425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 20435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 20445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 20455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fmul(VectorFormat vform, 20465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 20475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 20485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 20495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 20505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fmla(VectorFormat vform, 20515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 20525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 20535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 20545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 20555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fmls(VectorFormat vform, 20565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 20575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 20585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 20595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 20605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fmulx(VectorFormat vform, 20615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 20625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 20635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 20645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 20655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister smull(VectorFormat vform, 20665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 20675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 20685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 20695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 20705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister smull2(VectorFormat vform, 20715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 20725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 20735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 20745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 20755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister umull(VectorFormat vform, 20765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 20775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 20785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 20795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 20805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister umull2(VectorFormat vform, 20815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 20825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 20835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 20845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 20855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister smlal(VectorFormat vform, 20865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 20875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 20885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 20895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 20905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister smlal2(VectorFormat vform, 20915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 20925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 20935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 20945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 20955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister umlal(VectorFormat vform, 20965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 20975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 20985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 20995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 21005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister umlal2(VectorFormat vform, 21015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 21035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 21045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 21055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister smlsl(VectorFormat vform, 21065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 21085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 21095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 21105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister smlsl2(VectorFormat vform, 21115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 21135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 21145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 21155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister umlsl(VectorFormat vform, 21165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 21185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 21195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 21205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister umlsl2(VectorFormat vform, 21215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 21235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 21245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 21255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sqdmull(VectorFormat vform, 21265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 21285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 21295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 21305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sqdmull2(VectorFormat vform, 21315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 21335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 21345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 21355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sqdmlal(VectorFormat vform, 21365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 21385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 21395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 21405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sqdmlal2(VectorFormat vform, 21415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 21435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 21445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 21455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sqdmlsl(VectorFormat vform, 21465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 21485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 21495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 21505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sqdmlsl2(VectorFormat vform, 21515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 21535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 21545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 21555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sqdmulh(VectorFormat vform, 21565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 21585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 21595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 21605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sqrdmulh(VectorFormat vform, 21615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 21635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 21645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 21655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sub(VectorFormat vform, 21665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 21685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 21695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister and_(VectorFormat vform, 21705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 21725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 21735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister orr(VectorFormat vform, 21745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 21765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 21775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister orn(VectorFormat vform, 21785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 21805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 21815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister eor(VectorFormat vform, 21825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 21845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 21855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister bic(VectorFormat vform, 21865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 21885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 21895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister bic(VectorFormat vform, 21905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 21925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t imm); 21935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister bif(VectorFormat vform, 21945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 21965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 21975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister bit(VectorFormat vform, 21985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 22005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 22015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister bsl(VectorFormat vform, 22025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 22045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 22055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister cls(VectorFormat vform, 22065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 22085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister clz(VectorFormat vform, 22095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 22115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister cnt(VectorFormat vform, 22125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 22145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister not_(VectorFormat vform, 22155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 22175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister rbit(VectorFormat vform, 22185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 22205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister rev(VectorFormat vform, 22215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 22235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int revSize); 22245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister rev16(VectorFormat vform, 22255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 22275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister rev32(VectorFormat vform, 22285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 22305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister rev64(VectorFormat vform, 22315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 22335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister addlp(VectorFormat vform, 22345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 22365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl bool is_signed, 22375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl bool do_accumulate); 22385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister saddlp(VectorFormat vform, 22395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 22415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister uaddlp(VectorFormat vform, 22425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 22445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sadalp(VectorFormat vform, 22455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 22475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister uadalp(VectorFormat vform, 22485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 22505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister ext(VectorFormat vform, 22515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 22535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 22545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 22555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister ins_element(VectorFormat vform, 22565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int dst_index, 22585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 22595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int src_index); 22605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister ins_immediate(VectorFormat vform, 22615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int dst_index, 22635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t imm); 22645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dup_element(VectorFormat vform, 22655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 22675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int src_index); 22685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dup_immediate(VectorFormat vform, 22695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t imm); 22710f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister movi(VectorFormat vform, LogicVRegister dst, uint64_t imm); 22720f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister mvni(VectorFormat vform, LogicVRegister dst, uint64_t imm); 22735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister orr(VectorFormat vform, 22745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 22765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t imm); 22775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sshl(VectorFormat vform, 22785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 22805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 22815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister ushl(VectorFormat vform, 22825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 22845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 22855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sminmax(VectorFormat vform, 22865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 22885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 22895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl bool max); 22905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister smax(VectorFormat vform, 22910f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst, 22920f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src1, 22930f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src2); 22945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister smin(VectorFormat vform, 22950f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst, 22960f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src1, 22970f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src2); 22985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sminmaxp(VectorFormat vform, 22995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 2300b953ea8255b36e27834f17941429cd17af12f6f2Martyn Capewell const LogicVRegister& src1, 2301b953ea8255b36e27834f17941429cd17af12f6f2Martyn Capewell const LogicVRegister& src2, 23025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl bool max); 23035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister smaxp(VectorFormat vform, 23045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 23055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 23065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 23075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sminp(VectorFormat vform, 23085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 23095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 23105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 23115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister addp(VectorFormat vform, 23125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 23135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 23145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister addv(VectorFormat vform, 23155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 23165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 23175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister uaddlv(VectorFormat vform, 23185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 23195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 23205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister saddlv(VectorFormat vform, 23215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 23225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 23235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sminmaxv(VectorFormat vform, 23245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 23255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 23265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl bool max); 23275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister smaxv(VectorFormat vform, 23285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 23295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 23305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sminv(VectorFormat vform, 23315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 23325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 23335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister uxtl(VectorFormat vform, 23345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 23355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 23365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister uxtl2(VectorFormat vform, 23375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 23385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 23395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sxtl(VectorFormat vform, 23405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 23415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 23425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sxtl2(VectorFormat vform, 23435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 23445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 23455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister tbl(VectorFormat vform, 23465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 23475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab, 23485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& ind); 23495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister tbl(VectorFormat vform, 23505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 23515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab, 23525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab2, 23535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& ind); 23545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister tbl(VectorFormat vform, 23555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 23565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab, 23575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab2, 23585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab3, 23595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& ind); 23605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister tbl(VectorFormat vform, 23615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 23625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab, 23635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab2, 23645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab3, 23655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab4, 23665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& ind); 2367b953ea8255b36e27834f17941429cd17af12f6f2Martyn Capewell LogicVRegister Table(VectorFormat vform, 2368b953ea8255b36e27834f17941429cd17af12f6f2Martyn Capewell LogicVRegister dst, 2369b953ea8255b36e27834f17941429cd17af12f6f2Martyn Capewell const LogicVRegister& ind, 2370b953ea8255b36e27834f17941429cd17af12f6f2Martyn Capewell bool zero_out_of_bounds, 2371b953ea8255b36e27834f17941429cd17af12f6f2Martyn Capewell const LogicVRegister* tab1, 2372b953ea8255b36e27834f17941429cd17af12f6f2Martyn Capewell const LogicVRegister* tab2 = NULL, 2373b953ea8255b36e27834f17941429cd17af12f6f2Martyn Capewell const LogicVRegister* tab3 = NULL, 2374b953ea8255b36e27834f17941429cd17af12f6f2Martyn Capewell const LogicVRegister* tab4 = NULL); 23755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister tbx(VectorFormat vform, 23765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 23775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab, 23785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& ind); 23795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister tbx(VectorFormat vform, 23805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 23815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab, 23825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab2, 23835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& ind); 23845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister tbx(VectorFormat vform, 23855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 23865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab, 23875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab2, 23885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab3, 23895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& ind); 23905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister tbx(VectorFormat vform, 23915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 23925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab, 23935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab2, 23945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab3, 23955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab4, 23965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& ind); 23975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister uaddl(VectorFormat vform, 23985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 23995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 24005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 24015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister uaddl2(VectorFormat vform, 24025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 24045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 24055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister uaddw(VectorFormat vform, 24065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 24085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 24095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister uaddw2(VectorFormat vform, 24105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 24125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 24135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister saddl(VectorFormat vform, 24145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 24165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 24175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister saddl2(VectorFormat vform, 24185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 24205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 24215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister saddw(VectorFormat vform, 24225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 24245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 24255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister saddw2(VectorFormat vform, 24265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 24285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 24295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister usubl(VectorFormat vform, 24300f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst, 24310f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src1, 24320f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src2); 24335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister usubl2(VectorFormat vform, 24345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 24365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 24375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister usubw(VectorFormat vform, 24385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 24405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 24415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister usubw2(VectorFormat vform, 24425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 24445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 24455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister ssubl(VectorFormat vform, 24465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 24485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 24495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister ssubl2(VectorFormat vform, 24505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 24525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 24535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister ssubw(VectorFormat vform, 24545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 24565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 24575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister ssubw2(VectorFormat vform, 24585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 24605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 24615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister uminmax(VectorFormat vform, 24625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 24645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 24655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl bool max); 24665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister umax(VectorFormat vform, 24670f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst, 24680f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src1, 24690f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src2); 24705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister umin(VectorFormat vform, 24710f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst, 24720f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src1, 24730f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src2); 24745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister uminmaxp(VectorFormat vform, 24755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 2476b953ea8255b36e27834f17941429cd17af12f6f2Martyn Capewell const LogicVRegister& src1, 2477b953ea8255b36e27834f17941429cd17af12f6f2Martyn Capewell const LogicVRegister& src2, 24785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl bool max); 24795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister umaxp(VectorFormat vform, 24805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 24825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 24835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister uminp(VectorFormat vform, 24845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 24865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 24875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister uminmaxv(VectorFormat vform, 24885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 24905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl bool max); 24915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister umaxv(VectorFormat vform, 24925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 24945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister uminv(VectorFormat vform, 24955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 24975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister trn1(VectorFormat vform, 24985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 25005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 25015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister trn2(VectorFormat vform, 25025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 25045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 25055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister zip1(VectorFormat vform, 25065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 25085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 25095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister zip2(VectorFormat vform, 25105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 25125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 25135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister uzp1(VectorFormat vform, 25145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 25165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 25175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister uzp2(VectorFormat vform, 25185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 25205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 25215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister shl(VectorFormat vform, 25225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 25245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 25255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister scvtf(VectorFormat vform, 25265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 25285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int fbits, 25295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl FPRounding rounding_mode); 25305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister ucvtf(VectorFormat vform, 25315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 25335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int fbits, 25345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl FPRounding rounding_mode); 25355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sshll(VectorFormat vform, 25365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 25385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 25395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sshll2(VectorFormat vform, 25405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 25425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 25435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister shll(VectorFormat vform, 25445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 25465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister shll2(VectorFormat vform, 25475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 25495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister ushll(VectorFormat vform, 25505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 25525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 25535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister ushll2(VectorFormat vform, 25545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 25565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 25575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sli(VectorFormat vform, 25585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 25605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 25615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sri(VectorFormat vform, 25625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 25645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 25655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sshr(VectorFormat vform, 25665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 25685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 25695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister ushr(VectorFormat vform, 25705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 25725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 25735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister ssra(VectorFormat vform, 25745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 25765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 25775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister usra(VectorFormat vform, 25785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 25805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 25815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister srsra(VectorFormat vform, 25825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 25845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 25855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister ursra(VectorFormat vform, 25865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 25885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 25895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister suqadd(VectorFormat vform, 25900f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst, 25910f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src); 25925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister usqadd(VectorFormat vform, 25930f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst, 25940f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src); 25955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sqshl(VectorFormat vform, 25965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 25985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 25995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister uqshl(VectorFormat vform, 26005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 26015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 26025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 26035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sqshlu(VectorFormat vform, 26045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 26055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 26065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 26075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister abs(VectorFormat vform, 26085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 26095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 26105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister neg(VectorFormat vform, 26115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 26125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 26135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister extractnarrow(VectorFormat vform, 26145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 26155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl bool dstIsSigned, 26165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 26175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl bool srcIsSigned); 26185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister xtn(VectorFormat vform, 26195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 26205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 26215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sqxtn(VectorFormat vform, 26225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 26235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 26245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister uqxtn(VectorFormat vform, 26255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 26265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 26275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sqxtun(VectorFormat vform, 26285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 26295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 26305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister absdiff(VectorFormat vform, 26315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 26325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 26335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 26345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl bool issigned); 26355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister saba(VectorFormat vform, 26365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 26375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 26385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 26395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister uaba(VectorFormat vform, 26405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 26415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 26425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 26435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister shrn(VectorFormat vform, 26445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 26455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 26465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 26475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister shrn2(VectorFormat vform, 26480f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst, 26490f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src, 26500f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl int shift); 26515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister rshrn(VectorFormat vform, 26525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 26535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 26545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 26555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister rshrn2(VectorFormat vform, 26565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 26575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 26585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 26595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister uqshrn(VectorFormat vform, 26605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 26615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 26625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 26635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister uqshrn2(VectorFormat vform, 26645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 26655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 26665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 26675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister uqrshrn(VectorFormat vform, 26685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 26695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 26705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 26715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister uqrshrn2(VectorFormat vform, 26725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 26735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 26745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 26755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sqshrn(VectorFormat vform, 26765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 26775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 26785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 26795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sqshrn2(VectorFormat vform, 26805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 26815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 26825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 26835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sqrshrn(VectorFormat vform, 26845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 26855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 26865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 26875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sqrshrn2(VectorFormat vform, 26885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 26895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 26905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 26915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sqshrun(VectorFormat vform, 26925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 26935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 26945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 26955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sqshrun2(VectorFormat vform, 26965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 26975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 26985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 26995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sqrshrun(VectorFormat vform, 27005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 27015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 27025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 27035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sqrshrun2(VectorFormat vform, 27045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 27055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 27065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 27075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sqrdmulh(VectorFormat vform, 27085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 27095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 27105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 27115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl bool round = true); 27125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sqdmulh(VectorFormat vform, 27135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 27145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 27155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 27160f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl#define NEON_3VREG_LOGIC_LIST(V) \ 27170f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(addhn) \ 27180f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(addhn2) \ 27190f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(raddhn) \ 27200f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(raddhn2) \ 27210f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(subhn) \ 27220f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(subhn2) \ 27230f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(rsubhn) \ 27240f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(rsubhn2) \ 27250f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(pmull) \ 27260f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(pmull2) \ 27270f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(sabal) \ 27280f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(sabal2) \ 27290f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(uabal) \ 27300f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(uabal2) \ 27310f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(sabdl) \ 27320f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(sabdl2) \ 27330f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(uabdl) \ 27340f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(uabdl2) \ 27350f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(smull) \ 27360f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(smull2) \ 27370f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(umull) \ 27380f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(umull2) \ 27390f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(smlal) \ 27400f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(smlal2) \ 27410f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(umlal) \ 27420f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(umlal2) \ 27430f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(smlsl) \ 27440f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(smlsl2) \ 27450f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(umlsl) \ 27460f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(umlsl2) \ 27470f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(sqdmlal) \ 27480f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(sqdmlal2) \ 27490f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(sqdmlsl) \ 27500f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(sqdmlsl2) \ 27510f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(sqdmull) \ 27520f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(sqdmull2) 27530f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl 27540f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl#define DEFINE_LOGIC_FUNC(FXN) \ 27550f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister FXN(VectorFormat vform, \ 27560f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst, \ 27570f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src1, \ 27580f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src2); 27595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl NEON_3VREG_LOGIC_LIST(DEFINE_LOGIC_FUNC) 27600f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl#undef DEFINE_LOGIC_FUNC 27610f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl 27620f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl#define NEON_FP3SAME_LIST(V) \ 27630f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(fadd, FPAdd, false) \ 27640f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(fsub, FPSub, true) \ 27650f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(fmul, FPMul, true) \ 27660f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(fmulx, FPMulx, true) \ 27670f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(fdiv, FPDiv, true) \ 27680f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(fmax, FPMax, false) \ 27690f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(fmin, FPMin, false) \ 27700f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(fmaxnm, FPMaxNM, false) \ 27710f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(fminnm, FPMinNM, false) 27720f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl 27730f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl#define DECLARE_NEON_FP_VECTOR_OP(FN, OP, PROCNAN) \ 27740f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl template <typename T> \ 27750f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister FN(VectorFormat vform, \ 27760f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst, \ 27770f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src1, \ 27780f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src2); \ 27790f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister FN(VectorFormat vform, \ 27800f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst, \ 27810f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src1, \ 27820f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src2); 27835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl NEON_FP3SAME_LIST(DECLARE_NEON_FP_VECTOR_OP) 27840f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl#undef DECLARE_NEON_FP_VECTOR_OP 27850f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl 27860f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl#define NEON_FPPAIRWISE_LIST(V) \ 27870f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(faddp, fadd, FPAdd) \ 27880f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(fmaxp, fmax, FPMax) \ 27890f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(fmaxnmp, fmaxnm, FPMaxNM) \ 27900f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(fminp, fmin, FPMin) \ 27910f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(fminnmp, fminnm, FPMinNM) 27920f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl 27930f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl#define DECLARE_NEON_FP_PAIR_OP(FNP, FN, OP) \ 27940f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister FNP(VectorFormat vform, \ 27950f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst, \ 27960f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src1, \ 27970f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src2); \ 27980f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister FNP(VectorFormat vform, \ 27990f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst, \ 28000f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src); 28015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl NEON_FPPAIRWISE_LIST(DECLARE_NEON_FP_PAIR_OP) 28020f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl#undef DECLARE_NEON_FP_PAIR_OP 28035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 28045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl template <typename T> 28055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister frecps(VectorFormat vform, 28065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 28085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 28095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister frecps(VectorFormat vform, 28105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 28125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 28135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl template <typename T> 28145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister frsqrts(VectorFormat vform, 28155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 28175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 28185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister frsqrts(VectorFormat vform, 28195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 28215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 28225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl template <typename T> 28235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fmla(VectorFormat vform, 28245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 28265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 28275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fmla(VectorFormat vform, 28285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 28305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 28315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl template <typename T> 28325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fmls(VectorFormat vform, 28335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 28355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 28365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fmls(VectorFormat vform, 28375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 28395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 28405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fnmul(VectorFormat vform, 28415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 28435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 28445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 28455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl template <typename T> 28465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fcmp(VectorFormat vform, 28475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 28495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 28505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Condition cond); 28515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fcmp(VectorFormat vform, 28525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 28545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 28555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Condition cond); 28565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fabscmp(VectorFormat vform, 28575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 28595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 28605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Condition cond); 28615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fcmp_zero(VectorFormat vform, 28625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 28645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Condition cond); 28655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 28665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl template <typename T> 28675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fneg(VectorFormat vform, 28685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 28705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fneg(VectorFormat vform, 28715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 28735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl template <typename T> 28745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister frecpx(VectorFormat vform, 28755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 28775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister frecpx(VectorFormat vform, 28785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 28805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl template <typename T> 28815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fabs_(VectorFormat vform, 28825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 28845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fabs_(VectorFormat vform, 28855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 28875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fabd(VectorFormat vform, 28885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 28905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 28915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister frint(VectorFormat vform, 28925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 28945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl FPRounding rounding_mode, 28955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl bool inexact_exception = false); 28965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fcvts(VectorFormat vform, 28975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 28995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl FPRounding rounding_mode, 29005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int fbits = 0); 29015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fcvtu(VectorFormat vform, 29025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 29035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 29045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl FPRounding rounding_mode, 29055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int fbits = 0); 29065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fcvtl(VectorFormat vform, 29075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 29085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 29095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fcvtl2(VectorFormat vform, 29105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 29115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 29125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fcvtn(VectorFormat vform, 29135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 29145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 29155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fcvtn2(VectorFormat vform, 29165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 29175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 29185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fcvtxn(VectorFormat vform, 29195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 29205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 29215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fcvtxn2(VectorFormat vform, 29225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 29235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 29245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fsqrt(VectorFormat vform, 29255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 29265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 29275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister frsqrte(VectorFormat vform, 29285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 29295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 29305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister frecpe(VectorFormat vform, 29315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 29325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 29335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl FPRounding rounding); 29345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister ursqrte(VectorFormat vform, 29355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 29365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 29375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister urecpe(VectorFormat vform, 29385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 29395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 29405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 29415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl typedef float (Simulator::*FPMinMaxOp)(float a, float b); 29425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 29435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fminmaxv(VectorFormat vform, 29445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 29455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 29465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl FPMinMaxOp Op); 29475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 29485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fminv(VectorFormat vform, 29495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 29505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 29515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fmaxv(VectorFormat vform, 29525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 29535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 29545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fminnmv(VectorFormat vform, 29555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 29565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 29575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fmaxnmv(VectorFormat vform, 29585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 29595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 29605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 29610f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl static const uint32_t CRC32_POLY = 0x04C11DB7; 29625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl static const uint32_t CRC32C_POLY = 0x1EDC6F41; 29635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint32_t Poly32Mod2(unsigned n, uint64_t data, uint32_t poly); 29645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl template <typename T> 29655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint32_t Crc32Checksum(uint32_t acc, T val, uint32_t poly); 29665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint32_t Crc32Checksum(uint32_t acc, uint64_t val, uint32_t poly); 29675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 29685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void SysOp_W(int op, int64_t val); 2969ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 2970b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl template <typename T> 29715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl T FPRecipSqrtEstimate(T op); 29725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl template <typename T> 29735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl T FPRecipEstimate(T op, FPRounding rounding); 29745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl template <typename T, typename R> 29755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl R FPToFixed(T op, int fbits, bool is_signed, FPRounding rounding); 2976b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 29776e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl void FPCompare(double val0, double val1, FPTrapFlags trap); 2978ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl double FPRoundInt(double value, FPRounding round_mode); 2979578645f14e122d2b87d907e298cda7e7d0babf1farmvixl double FPToDouble(float value); 2980578645f14e122d2b87d907e298cda7e7d0babf1farmvixl float FPToFloat(double value, FPRounding round_mode); 29815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl float FPToFloat(float16 value); 29825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl float16 FPToFloat16(float value, FPRounding round_mode); 29835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl float16 FPToFloat16(double value, FPRounding round_mode); 29845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl double recip_sqrt_estimate(double a); 29855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl double recip_estimate(double a); 29865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl double FPRecipSqrtEstimate(double a); 29875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl double FPRecipEstimate(double a); 2988578645f14e122d2b87d907e298cda7e7d0babf1farmvixl double FixedToDouble(int64_t src, int fbits, FPRounding round_mode); 2989578645f14e122d2b87d907e298cda7e7d0babf1farmvixl double UFixedToDouble(uint64_t src, int fbits, FPRounding round_mode); 2990578645f14e122d2b87d907e298cda7e7d0babf1farmvixl float FixedToFloat(int64_t src, int fbits, FPRounding round_mode); 2991578645f14e122d2b87d907e298cda7e7d0babf1farmvixl float UFixedToFloat(uint64_t src, int fbits, FPRounding round_mode); 2992ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl int32_t FPToInt32(double value, FPRounding rmode); 2993ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl int64_t FPToInt64(double value, FPRounding rmode); 2994ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl uint32_t FPToUInt32(double value, FPRounding rmode); 2995ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl uint64_t FPToUInt64(double value, FPRounding rmode); 2996f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl 2997f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl template <typename T> 2998b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl T FPAdd(T op1, T op2); 2999f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl 3000f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl template <typename T> 3001b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl T FPDiv(T op1, T op2); 3002b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 3003b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl template <typename T> 3004b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl T FPMax(T a, T b); 3005f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl 3006f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl template <typename T> 3007f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl T FPMaxNM(T a, T b); 3008f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl 3009f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl template <typename T> 3010b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl T FPMin(T a, T b); 3011b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 3012b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl template <typename T> 3013f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl T FPMinNM(T a, T b); 3014ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 3015b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl template <typename T> 3016b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl T FPMul(T op1, T op2); 3017b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 3018b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl template <typename T> 30195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl T FPMulx(T op1, T op2); 30205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 30215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl template <typename T> 3022b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl T FPMulAdd(T a, T op1, T op2); 3023b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 3024b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl template <typename T> 3025b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl T FPSqrt(T op); 3026b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 3027b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl template <typename T> 3028b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl T FPSub(T op1, T op2); 3029b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 30305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl template <typename T> 30315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl T FPRecipStepFused(T op1, T op2); 30325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 30335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl template <typename T> 30345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl T FPRSqrtStepFused(T op1, T op2); 30355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 3036b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl // This doesn't do anything at the moment. We'll need it if we want support 3037b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl // for cumulative exception bits or floating-point exceptions. 30380f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl void FPProcessException() {} 3039b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 3040c68cb64496485710cdb5b8480f8fee287058c93farmvixl bool FPProcessNaNs(const Instruction* instr); 3041b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 3042ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // Pseudo Printf instruction 3043c68cb64496485710cdb5b8480f8fee287058c93farmvixl void DoPrintf(const Instruction* instr); 3044ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 3045064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames// Simulate a runtime call. 3046ca73ba046c11d65b6dce59cfd26847d14aba06abAlexandre Rames#ifndef VIXL_HAS_SIMULATED_RUNTIME_CALL_SUPPORT 3047064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames VIXL_NO_RETURN_IN_DEBUG_MODE 3048064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames#endif 3049064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames void DoRuntimeCall(const Instruction* instr); 3050064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames 3051ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // Processor state --------------------------------------- 3052ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 30534a102baf640077d6794c0b33bb976f94b86c532barmvixl // Simulated monitors for exclusive access instructions. 30544a102baf640077d6794c0b33bb976f94b86c532barmvixl SimExclusiveLocalMonitor local_monitor_; 30554a102baf640077d6794c0b33bb976f94b86c532barmvixl SimExclusiveGlobalMonitor global_monitor_; 30564a102baf640077d6794c0b33bb976f94b86c532barmvixl 3057ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // Output stream. 3058ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FILE* stream_; 3059ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl PrintDisassembler* print_disasm_; 3060ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 3061578645f14e122d2b87d907e298cda7e7d0babf1farmvixl // Instruction statistics instrumentation. 3062578645f14e122d2b87d907e298cda7e7d0babf1farmvixl Instrument* instrumentation_; 3063578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 3064ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // General purpose registers. Register 31 is the stack pointer. 3065ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl SimRegister registers_[kNumberOfRegisters]; 3066ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 30675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Vector registers 30685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister vregisters_[kNumberOfVRegisters]; 3069ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 3070ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // Program Status Register. 3071ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // bits[31, 27]: Condition flags N, Z, C, and V. 3072ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // (Negative, Zero, Carry, Overflow) 3073578645f14e122d2b87d907e298cda7e7d0babf1farmvixl SimSystemRegister nzcv_; 3074578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 3075578645f14e122d2b87d907e298cda7e7d0babf1farmvixl // Floating-Point Control Register 3076578645f14e122d2b87d907e298cda7e7d0babf1farmvixl SimSystemRegister fpcr_; 3077578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 3078578645f14e122d2b87d907e298cda7e7d0babf1farmvixl // Only a subset of FPCR features are supported by the simulator. This helper 3079578645f14e122d2b87d907e298cda7e7d0babf1farmvixl // checks that the FPCR settings are supported. 3080578645f14e122d2b87d907e298cda7e7d0babf1farmvixl // 3081578645f14e122d2b87d907e298cda7e7d0babf1farmvixl // This is checked when floating-point instructions are executed, not when 3082578645f14e122d2b87d907e298cda7e7d0babf1farmvixl // FPCR is set. This allows generated code to modify FPCR for external 3083578645f14e122d2b87d907e298cda7e7d0babf1farmvixl // functions, or to save and restore it when entering and leaving generated 3084578645f14e122d2b87d907e298cda7e7d0babf1farmvixl // code. 3085578645f14e122d2b87d907e298cda7e7d0babf1farmvixl void AssertSupportedFPCR() { 308688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois // No flush-to-zero support. 308788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_ASSERT(ReadFpcr().GetFZ() == 0); 308888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois // Ties-to-even rounding only. 308988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_ASSERT(ReadFpcr().GetRMode() == FPTieEven); 3090578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 309188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois // The simulator does not support half-precision operations so 309288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois // GetFpcr().AHP() is irrelevant, and is not checked here. 3093578645f14e122d2b87d907e298cda7e7d0babf1farmvixl } 3094ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 3095330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl static int CalcNFlag(uint64_t result, unsigned reg_size) { 3096578645f14e122d2b87d907e298cda7e7d0babf1farmvixl return (result >> (reg_size - 1)) & 1; 3097ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 3098ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 30990f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl static int CalcZFlag(uint64_t result) { return (result == 0) ? 1 : 0; } 3100ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 3101ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl static const uint32_t kConditionFlagsMask = 0xf0000000; 3102ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 3103ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // Stack 3104ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl byte* stack_; 3105ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl static const int stack_protection_size_ = 256; 3106ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // 2 KB stack. 3107ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl static const int stack_size_ = 2 * 1024 + 2 * stack_protection_size_; 3108ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl byte* stack_limit_; 3109ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 3110ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl Decoder* decoder_; 3111ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // Indicates if the pc has been modified by the instruction and should not be 3112ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // automatically incremented. 3113ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl bool pc_modified_; 3114c68cb64496485710cdb5b8480f8fee287058c93farmvixl const Instruction* pc_; 3115ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 3116ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl static const char* xreg_names[]; 3117ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl static const char* wreg_names[]; 3118ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl static const char* sreg_names[]; 3119ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl static const char* dreg_names[]; 3120ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl static const char* vreg_names[]; 3121ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 3122ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl private: 31236e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl template <typename T> 31246e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl static T FPDefaultNaN(); 31256e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 31266e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // Standard NaN processing. 31276e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl template <typename T> 31286e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl T FPProcessNaN(T op) { 31296e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl VIXL_ASSERT(std::isnan(op)); 31306e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if (IsSignallingNaN(op)) { 31316e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl FPProcessException(); 31326e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 313388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadDN() ? FPDefaultNaN<T>() : ToQuietNaN(op); 31346e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 31356e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 31366e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl template <typename T> 31376e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl T FPProcessNaNs(T op1, T op2) { 31386e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if (IsSignallingNaN(op1)) { 31396e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return FPProcessNaN(op1); 31406e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } else if (IsSignallingNaN(op2)) { 31416e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return FPProcessNaN(op2); 31426e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } else if (std::isnan(op1)) { 31436e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl VIXL_ASSERT(IsQuietNaN(op1)); 31446e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return FPProcessNaN(op1); 31456e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } else if (std::isnan(op2)) { 31466e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl VIXL_ASSERT(IsQuietNaN(op2)); 31476e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return FPProcessNaN(op2); 31486e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } else { 31496e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return 0.0; 31506e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 31516e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 31526e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 31536e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl template <typename T> 31546e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl T FPProcessNaNs3(T op1, T op2, T op3) { 31556e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if (IsSignallingNaN(op1)) { 31566e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return FPProcessNaN(op1); 31576e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } else if (IsSignallingNaN(op2)) { 31586e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return FPProcessNaN(op2); 31596e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } else if (IsSignallingNaN(op3)) { 31606e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return FPProcessNaN(op3); 31616e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } else if (std::isnan(op1)) { 31626e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl VIXL_ASSERT(IsQuietNaN(op1)); 31636e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return FPProcessNaN(op1); 31646e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } else if (std::isnan(op2)) { 31656e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl VIXL_ASSERT(IsQuietNaN(op2)); 31666e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return FPProcessNaN(op2); 31676e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } else if (std::isnan(op3)) { 31686e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl VIXL_ASSERT(IsQuietNaN(op3)); 31696e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return FPProcessNaN(op3); 31706e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } else { 31716e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return 0.0; 31726e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 31736e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 31746e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 3175ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl bool coloured_trace_; 3176578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 3177330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl // A set of TraceParameters flags. 3178330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl int trace_parameters_; 3179578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 3180578645f14e122d2b87d907e298cda7e7d0babf1farmvixl // Indicates whether the instruction instrumentation is active. 3181578645f14e122d2b87d907e298cda7e7d0babf1farmvixl bool instruction_stats_; 31824a102baf640077d6794c0b33bb976f94b86c532barmvixl 31834a102baf640077d6794c0b33bb976f94b86c532barmvixl // Indicates whether the exclusive-access warning has been printed. 31844a102baf640077d6794c0b33bb976f94b86c532barmvixl bool print_exclusive_access_warning_; 31854a102baf640077d6794c0b33bb976f94b86c532barmvixl void PrintExclusiveAccessWarning(); 3186ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl}; 3187064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames 3188482d4df29d1466ff87d94e74034f1a8659f1b354Jacob Bramley#if defined(VIXL_HAS_SIMULATED_RUNTIME_CALL_SUPPORT) && __cplusplus < 201402L 3189064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames// Base case of the recursive template used to emulate C++14 3190064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames// `std::index_sequence`. 3191064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Ramestemplate <size_t... I> 3192064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Ramesstruct Simulator::emulated_make_index_sequence_helper<0, I...> 3193064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames : Simulator::emulated_index_sequence<I...> {}; 3194064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames#endif 3195064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames 319688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois} // namespace aarch64 3197ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl} // namespace vixl 3198ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 3199a4055d25c688d1397fc369a40abf57fa4f1ab805Pierre Langlois#endif // VIXL_INCLUDE_SIMULATOR_AARCH64 3200a4055d25c688d1397fc369a40abf57fa4f1ab805Pierre Langlois 3201d3832965c62a8ad461b9ea9eb0994ca6b0a3da2cAlexandre Rames#endif // VIXL_AARCH64_SIMULATOR_AARCH64_H_ 3202